# IBM_PROLOG_BEGIN_TAG
# This is an automatically generated prolog.
#
# $Source: src/usr/diag/prdf/common/plat/nimbus/nimbus_obus.rule $
#
# OpenPOWER HostBoot Project
#
# Contributors Listed Below - COPYRIGHT 2016,2018
# [+] International Business Machines Corp.
#
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
# implied. See the License for the specific language governing
# permissions and limitations under the License.
#
# IBM_PROLOG_END_TAG

chip nimbus_obus
{
    name        "NIMBUS OBUS target";
    targettype  TYPE_OBUS;
    sigoff      0x9000;
    dump        DUMP_CONTENT_HW;
    scomlen     64;

# Import signatures
.include "prdfLaneRepairExtraSig.H";

 #############################################################################
 #                                                                           #
 #  ######                                                                   #
 #  #     #  ######   ####     ###    ####    #####  ######  #####    ####   #
 #  #     #  #       #    #     #    #          #    #       #    #  #       #
 #  ######   #####   #          #     ####      #    #####   #    #   ####   #
 #  #   #    #       #  ###     #         #     #    #       #####        #  #
 #  #    #   #       #    #     #    #    #     #    #       #   #   #    #  #
 #  #     #  ######   ####     ###    ####      #    ######  #    #   ####   #
 #                                                                           #
 #############################################################################

    ############################################################################
    # OB Chiplet FIR
    ############################################################################

    register OB_CHIPLET_CS_FIR
    {
        name        "OB Chiplet Checkstop FIR";
        scomaddr    0x09040000;
        capture     group default;
    };

    register OB_CHIPLET_RE_FIR
    {
        name        "OB Chiplet Recoverable FIR";
        scomaddr    0x09040001;
        capture     group default;
    };

    register OB_CHIPLET_FIR_MASK
    {
        name        "OB Chiplet FIR MASK";
        scomaddr    0x09040002;
        capture     group default;
    };

    ############################################################################
    # OB Chiplet Unit Checkstop FIR
    ############################################################################

    register OB_CHIPLET_UCS_FIR
    {
        name        "OB Chiplet Unit Checkstop FIR";
        scomaddr    0x09040018;
        capture     group default;
    };

    register OB_CHIPLET_UCS_FIR_MASK
    {
        name        "OB Chiplet Unit Checkstop FIR MASK";
        scomaddr    0x09040019;
        capture     group default;
    };

    ############################################################################
    # P9 OBUS target OB_LFIR
    ############################################################################

    register OB_LFIR
    {
        name        "P9 OBUS target OB_LFIR";
        scomaddr    0x0904000a;
        reset       (&, 0x0904000b);
        mask        (|, 0x0904000f);
        capture     group default;
    };

    register OB_LFIR_MASK
    {
        name        "P9 OBUS target OB_LFIR MASK";
        scomaddr    0x0904000d;
        capture     group default;
    };

    register OB_LFIR_ACT0
    {
        name        "P9 OBUS target OB_LFIR ACT0";
        scomaddr    0x09040010;
        capture     group default;
        capture     req nonzero("OB_LFIR");
    };

    register OB_LFIR_ACT1
    {
        name        "P9 OBUS target OB_LFIR ACT1";
        scomaddr    0x09040011;
        capture     group default;
        capture     req nonzero("OB_LFIR");
    };

    ############################################################################
    # P9 OBUS target IOOLFIR
    ############################################################################

    register IOOLFIR
    {
        name        "P9 OBUS target IOOLFIR";
        scomaddr    0x09010800;
        reset       (&, 0x09010801);
        mask        (|, 0x09010805);
        capture     group default;
        capture     group smpCableFFDC;
    };

    register IOOLFIR_MASK
    {
        name        "P9 OBUS target IOOLFIR MASK";
        scomaddr    0x09010803;
        capture     group default;
    };

    register IOOLFIR_ACT0
    {
        name        "P9 OBUS target IOOLFIR ACT0";
        scomaddr    0x09010806;
        capture     group default;
        capture     req nonzero("IOOLFIR");
    };

    register IOOLFIR_ACT1
    {
        name        "P9 OBUS target IOOLFIR ACT1";
        scomaddr    0x09010807;
        capture     group default;
        capture     req nonzero("IOOLFIR");
    };

    ############################################################################
    # P9 OBUS target IOOBFIR
    ############################################################################

    register IOOBFIR
    {
        name        "P9 OBUS target IOOBFIR";
        scomaddr    0x09010c00;
        reset       (&, 0x09010c01);
        mask        (|, 0x09010c05);
        capture     group default;
    };

    register IOOBFIR_MASK
    {
        name        "P9 OBUS target IOOBFIR MASK";
        scomaddr    0x09010c03;
        capture     group default;
    };

    register IOOBFIR_ACT0
    {
        name        "P9 OBUS target IOOBFIR ACT0";
        scomaddr    0x09010c06;
        capture     group default;
        capture     req nonzero("IOOBFIR");
    };

    register IOOBFIR_ACT1
    {
        name        "P9 OBUS target IOOBFIR ACT1";
        scomaddr    0x09010c07;
        capture     group default;
        capture     req nonzero("IOOBFIR");
    };

    ############################################################################
    # P9 OBUS target OBPPEFIR
    ############################################################################

    register OBPPEFIR
    {
        name        "P9 OBUS target OBPPEFIR";
        scomaddr    0x09011040;
        reset       (&, 0x09011041);
        mask        (|, 0x09011045);
        capture     group default;
    };

    register OBPPEFIR_MASK
    {
        name        "P9 OBUS target OBPPEFIR MASK";
        scomaddr    0x09011043;
        capture     group default;
    };

    register OBPPEFIR_ACT0
    {
        name        "P9 OBUS target OBPPEFIR ACT0";
        scomaddr    0x09011046;
        capture     group default;
        capture     req nonzero("OBPPEFIR");
    };

    register OBPPEFIR_ACT1
    {
        name        "P9 OBUS target OBPPEFIR ACT1";
        scomaddr    0x09011047;
        capture     group default;
        capture     req nonzero("OBPPEFIR");
    };

# Include registers not defined by the xml
.include "p9_common_obus_regs.rule";

};

 ##############################################################################
 #                                                                            #
 # ####                                 #                                     #
 # #   # #   # #    #####  ###      #  # #    ##  ##### ###  ###  #   #  ###  #
 # #   # #   # #    #     #        #  #   #  #  #   #    #  #   # ##  # #     #
 # ####  #   # #    ####   ###    #  ####### #      #    #  #   # # # #  ###  #
 # #  #  #   # #    #         #  #   #     # #  #   #    #  #   # #  ##     # #
 # #   #  ###  #### #####  ###  #    #     #  ##    #   ###  ###  #   #  ###  #
 #                                                                            #
 ##############################################################################

################################################################################
# OB Chiplet FIR
################################################################################

rule rOB_CHIPLET_FIR
{
  CHECK_STOP:
     OB_CHIPLET_CS_FIR       & ~OB_CHIPLET_FIR_MASK & `1fffffffffffffff`;
  RECOVERABLE:
    (OB_CHIPLET_RE_FIR >> 2) & ~OB_CHIPLET_FIR_MASK & `1fffffffffffffff`;
};

group gOB_CHIPLET_FIR attntype CHECK_STOP, RECOVERABLE
    filter singlebit
{
    /** OB_CHIPLET_FIR[3]
     *  Attention from OB_LFIR
     */
    (rOB_CHIPLET_FIR, bit(3)) ? analyzeOB_LFIR;

    /** OB_CHIPLET_FIR[4]
     *  Attention from IOOLFIR
     */
    (rOB_CHIPLET_FIR, bit(4)) ? analyzeIOOLFIR;

    /** OB_CHIPLET_FIR[5]
     *  Attention from IOOBFIR
     */
    (rOB_CHIPLET_FIR, bit(5)) ? analyzeIOOBFIR;

    /** OB_CHIPLET_FIR[6]
     *  Attention from OBPPEFIR
     */
    (rOB_CHIPLET_FIR, bit(6)) ? analyzeOBPPEFIR;

};

################################################################################
# OB Chiplet Unit Checkstop FIR
################################################################################

rule rOB_CHIPLET_UCS_FIR
{
  UNIT_CS:
    OB_CHIPLET_UCS_FIR & ~(OB_CHIPLET_UCS_FIR_MASK >> 1) & `7fffffffffffffff`;
};

group gOB_CHIPLET_UCS_FIR attntype UNIT_CS
    filter singlebit
{
    /** OB_CHIPLET_UCS_FIR[2]
     *  Attention from IOOBFIR
     */
    (rOB_CHIPLET_UCS_FIR, bit(2)) ? analyzeIOOBFIR;

    /** OB_CHIPLET_UCS_FIR[3]
     *  Attention from OBPPEFIR
     */
    (rOB_CHIPLET_UCS_FIR, bit(3)) ? analyzeOBPPEFIR;

};

################################################################################
# P9 OBUS target OB_LFIR
################################################################################

rule rOB_LFIR
{
  CHECK_STOP:
    OB_LFIR & ~OB_LFIR_MASK & ~OB_LFIR_ACT0 & ~OB_LFIR_ACT1;
  RECOVERABLE:
    OB_LFIR & ~OB_LFIR_MASK & ~OB_LFIR_ACT0 &  OB_LFIR_ACT1;
};

group gOB_LFIR
    filter singlebit,
           cs_root_cause
{
    /** OB_LFIR[0]
     *  CFIR internal parity error
     */
    (rOB_LFIR, bit(0)) ? self_th_32perDay;

    /** OB_LFIR[1]
     *  Chiplet Control Reg: PCB Access Error
     */
    (rOB_LFIR, bit(1)) ? self_th_32perDay;

    /** OB_LFIR[2]
     *  Clock Controller: PCB Access Error
     */
    (rOB_LFIR, bit(2)) ? self_th_32perDay;

    /** OB_LFIR[3]
     *  Clock Controller: Summarized Error
     */
    (rOB_LFIR, bit(3)) ? self_th_32perDay;

    /** OB_LFIR[4]
     *  PSCOM Logic: PCB Access Error
     */
    (rOB_LFIR, bit(4)) ? defaultMaskedError;

    /** OB_LFIR[5]
     *  PSCOM Logic: Summarized internal errors
     */
    (rOB_LFIR, bit(5)) ? defaultMaskedError;

    /** OB_LFIR[6]
     *  Therm Logic: Summarized internal errors
     */
    (rOB_LFIR, bit(6)) ? defaultMaskedError;

    /** OB_LFIR[7]
     *  Therm Logic: PCB Access Error
     */
    (rOB_LFIR, bit(7)) ? defaultMaskedError;

    /** OB_LFIR[8]
     *  Therm Logic: Temperature critical trip
     */
    (rOB_LFIR, bit(8)) ? defaultMaskedError;

    /** OB_LFIR[9]
     *  Therm Logic: Temperature fatal trip
     */
    (rOB_LFIR, bit(9)) ? defaultMaskedError;

    /** OB_LFIR[10]
     *  UNUSED in P9
     */
    (rOB_LFIR, bit(10)) ? defaultMaskedError;

    /** OB_LFIR[11]
     *  Debug Logic: Scom Satellite Error
     */
    (rOB_LFIR, bit(11)) ? defaultMaskedError;

    /** OB_LFIR[12]
     *  Scom Satellite Error - L3 Trace0
     */
    (rOB_LFIR, bit(12)) ? defaultMaskedError;

    /** OB_LFIR[13]
     *  Scom Satellite Error - L3 Trace0
     */
    (rOB_LFIR, bit(13)) ? defaultMaskedError;

    /** OB_LFIR[14:40]
     *  unused
     */
    (rOB_LFIR, bit(14|15|16|17|18|19|20|21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39|40)) ? defaultMaskedError;

    /** OB_LFIR[41]
     *  Malfunction Alert or Local Checkstop
     */
    (rOB_LFIR, bit(41)) ? defaultMaskedError;

};

################################################################################
# P9 OBUS target IOOLFIR
################################################################################

rule rIOOLFIR
{
  CHECK_STOP:
    IOOLFIR & ~IOOLFIR_MASK & ~IOOLFIR_ACT0 & ~IOOLFIR_ACT1;
  RECOVERABLE:
    IOOLFIR & ~IOOLFIR_MASK & ~IOOLFIR_ACT0 &  IOOLFIR_ACT1;
};

group gIOOLFIR
    filter singlebit,
           cs_root_cause(54,55,56,57,58,59)
{
    /** IOOLFIR[0]
     *  link0 trained
     */
    (rIOOLFIR, bit(0)) ? defaultMaskedError;

    /** IOOLFIR[1]
     *  link1 trained
     */
    (rIOOLFIR, bit(1)) ? defaultMaskedError;

    /** IOOLFIR[2]
     *  link0 op irq
     */
    (rIOOLFIR, bit(2)) ? defaultMaskedError;

    /** IOOLFIR[3]
     *  link1 op irq
     */
    (rIOOLFIR, bit(3)) ? defaultMaskedError;

    /** IOOLFIR[4]
     *  link0 replay threshold
     */
    (rIOOLFIR, bit(4)) ? defaultMaskedError;

    /** IOOLFIR[5]
     *  link1 replay threshold
     */
    (rIOOLFIR, bit(5)) ? defaultMaskedError;

    /** IOOLFIR[6]
     *  link0 crc error
     */
    (rIOOLFIR, bit(6)) ? threshold_and_mask_self;

    /** IOOLFIR[7]
     *  link1 crc error
     */
    (rIOOLFIR, bit(7)) ? threshold_and_mask_self;

    /** IOOLFIR[8]
     *  link0 nak received
     */
    (rIOOLFIR, bit(8)) ? defaultMaskedError;

    /** IOOLFIR[9]
     *  link1 nak received
     */
    (rIOOLFIR, bit(9)) ? defaultMaskedError;

    /** IOOLFIR[10]
     *  link0 replay buffer full
     */
    (rIOOLFIR, bit(10)) ? defaultMaskedError;

    /** IOOLFIR[11]
     *  link1 replay buffer full
     */
    (rIOOLFIR, bit(11)) ? defaultMaskedError;

    /** IOOLFIR[12]
     *  link0 sl ecc threshold
     */
    (rIOOLFIR, bit(12)) ? defaultMaskedError;

    /** IOOLFIR[13]
     *  link1 sl ecc threshold
     */
    (rIOOLFIR, bit(13)) ? defaultMaskedError;

    /** IOOLFIR[14]
     *  link0 sl ecc correctable
     */
    (rIOOLFIR, bit(14)) ? threshold_and_mask_self;

    /** IOOLFIR[15]
     *  link1 sl ecc correctable
     */
    (rIOOLFIR, bit(15)) ? threshold_and_mask_self;

    /** IOOLFIR[16]
     *  link0 sl ecc ue
     */
    (rIOOLFIR, bit(16)) ? threshold_and_mask_self;

    /** IOOLFIR[17]
     *  link1 sl ecc ue
     */
    (rIOOLFIR, bit(17)) ? threshold_and_mask_self;

    /** IOOLFIR[18]
     *  link0 retrain threshold
     */
    (rIOOLFIR, bit(18)) ? defaultMaskedError;

    /** IOOLFIR[19]
     *  link1 retrain threshold
     */
    (rIOOLFIR, bit(19)) ? defaultMaskedError;

    /** IOOLFIR[20]
     *  link0 loss block align
     */
    (rIOOLFIR, bit(20)) ? defaultMaskedError;

    /** IOOLFIR[21]
     *  link1 loss block align
     */
    (rIOOLFIR, bit(21)) ? defaultMaskedError;

    /** IOOLFIR[22]
     *  link0 invalid block
     */
    (rIOOLFIR, bit(22)) ? defaultMaskedError;

    /** IOOLFIR[23]
     *  link1 invalid block
     */
    (rIOOLFIR, bit(23)) ? defaultMaskedError;

    /** IOOLFIR[24]
     *  link0 deskew error
     */
    (rIOOLFIR, bit(24)) ? defaultMaskedError;

    /** IOOLFIR[25]
     *  link1 deskew error
     */
    (rIOOLFIR, bit(25)) ? defaultMaskedError;

    /** IOOLFIR[26]
     *  link0 deskew overflow
     */
    (rIOOLFIR, bit(26)) ? defaultMaskedError;

    /** IOOLFIR[27]
     *  link1 deskew overflow
     */
    (rIOOLFIR, bit(27)) ? defaultMaskedError;

    /** IOOLFIR[28]
     *  link0 sw retrain
     */
    (rIOOLFIR, bit(28)) ? defaultMaskedError;

    /** IOOLFIR[29]
     *  link1 sw retrain
     */
    (rIOOLFIR, bit(29)) ? defaultMaskedError;

    /** IOOLFIR[30]
     *  link0 ack queue overflow
     */
    (rIOOLFIR, bit(30)) ? defaultMaskedError;

    /** IOOLFIR[31]
     *  link1 ack queue overflow
     */
    (rIOOLFIR, bit(31)) ? defaultMaskedError;

    /** IOOLFIR[32]
     *  link0 ack queue underflow
     */
    (rIOOLFIR, bit(32)) ? defaultMaskedError;

    /** IOOLFIR[33]
     *  link1 ack queue underflow
     */
    (rIOOLFIR, bit(33)) ? defaultMaskedError;

    /** IOOLFIR[34]
     *  link0 num replay
     */
    (rIOOLFIR, bit(34)) ? defaultMaskedError;

    /** IOOLFIR[35]
     *  link1 num replay
     */
    (rIOOLFIR, bit(35)) ? defaultMaskedError;

    /** IOOLFIR[36]
     *  link0 training set received
     */
    (rIOOLFIR, bit(36)) ? defaultMaskedError;

    /** IOOLFIR[37]
     *  link1 training set received
     */
    (rIOOLFIR, bit(37)) ? defaultMaskedError;

    /** IOOLFIR[38]
     *  link0 prbs select error
     */
    (rIOOLFIR, bit(38)) ? threshold_and_mask_self;

    /** IOOLFIR[39]
     *  link1 prbs select error
     */
    (rIOOLFIR, bit(39)) ? threshold_and_mask_self;

    /** IOOLFIR[40]
     *  link0 tcomplete bad
     */
    (rIOOLFIR, bit(40)) ? defaultMaskedError;

    /** IOOLFIR[41]
     *  link1 tcomplete bad
     */
    (rIOOLFIR, bit(41)) ? defaultMaskedError;

    /** IOOLFIR[42]
     *  link0 no spare lane available
     */
    (rIOOLFIR, bit(42)) ? obusSmpCallout_L0;

    /** IOOLFIR[43]
     *  link1 no spare lane available
     */
    (rIOOLFIR, bit(43)) ? obusSmpCallout_L1;

    /** IOOLFIR[44]
     *  link0 spare done
     */
    (rIOOLFIR, bit(44)) ? obusSmpCallout_th32_L0;

    /** IOOLFIR[45]
     *  link1 spare done
     */
    (rIOOLFIR, bit(45)) ? obusSmpCallout_th32_L1;

    /** IOOLFIR[46]
     *  link0 too many crc errors
     */
    (rIOOLFIR, bit(46)) ? obusSmpCallout_L0;

    /** IOOLFIR[47]
     *  link1 too many crc errors
     */
    (rIOOLFIR, bit(47)) ? obusSmpCallout_L1;

    /** IOOLFIR[48]
     *  link0 npu error
     */
    (rIOOLFIR, bit(48)) ? threshold_and_mask_self;

    /** IOOLFIR[49]
     *  link1 npu error
     */
    (rIOOLFIR, bit(49)) ? threshold_and_mask_self;

    /** IOOLFIR[50]
     *  linkx npu error
     */
    (rIOOLFIR, bit(50)) ? threshold_and_mask_self;

    /** IOOLFIR[51]
     *  osc switch
     */
    (rIOOLFIR, bit(51)) ? threshold_and_mask_self;

    /** IOOLFIR[52]
     *  link0 correctable array error
     */
    (rIOOLFIR, bit(52)) ? obusSmpCallout_th32_L0;

    /** IOOLFIR[53]
     *  link1 correctable array error
     */
    (rIOOLFIR, bit(53)) ? obusSmpCallout_th32_L1;

    /** IOOLFIR[54]
     *  link0 uncorrectable array error
     */
    (rIOOLFIR, bit(54)) ? obusSmpCallout_th32_L0;

    /** IOOLFIR[55]
     *  link1 uncorrectable array error
     */
    (rIOOLFIR, bit(55)) ? obusSmpCallout_th32_L1;

    /** IOOLFIR[56]
     *  link0 training failed
     */
    (rIOOLFIR, bit(56)) ? obusSmpFailure_L0;

    /** IOOLFIR[57]
     *  link1 training failed
     */
    (rIOOLFIR, bit(57)) ? obusSmpFailure_L1;

    /** IOOLFIR[58]
     *  link0 unrecoverable error
     */
    (rIOOLFIR, bit(58)) ? obusSmpCallout_th32_L0;

    /** IOOLFIR[59]
     *  link1 unrecoverable error
     */
    (rIOOLFIR, bit(59)) ? obusSmpCallout_th32_L1;

    /** IOOLFIR[60]
     *  link0 internal error
     */
    (rIOOLFIR, bit(60)) ? self_th_32perDay;

    /** IOOLFIR[61]
     *  link1 internal error
     */
    (rIOOLFIR, bit(61)) ? self_th_32perDay;

    /** IOOLFIR[62]
     *  fir scom err dup
     */
    (rIOOLFIR, bit(62)) ? defaultMaskedError;

    /** IOOLFIR[63]
     *  fir scom err
     */
    (rIOOLFIR, bit(63)) ? defaultMaskedError;

};

################################################################################
# P9 OBUS target IOOBFIR
################################################################################

rule rIOOBFIR
{
  CHECK_STOP:
    IOOBFIR & ~IOOBFIR_MASK & ~IOOBFIR_ACT0 & ~IOOBFIR_ACT1;
  RECOVERABLE:
    IOOBFIR & ~IOOBFIR_MASK & ~IOOBFIR_ACT0 &  IOOBFIR_ACT1;
  UNIT_CS:
    IOOBFIR & ~IOOBFIR_MASK &  IOOBFIR_ACT0 &  IOOBFIR_ACT1;
};

group gIOOBFIR
    filter singlebit,
           cs_root_cause
{
    /** IOOBFIR[0]
     *  A RX state machine error
     */
    (rIOOBFIR, bit(0)) ? defaultMaskedError;

    /** IOOBFIR[1]
     *  A TX state machine error
     */
    (rIOOBFIR, bit(1)) ? defaultMaskedError;

    /** IOOBFIR[2]
     *  The per-bus GCR ring hang detector error
     */
    (rIOOBFIR, bit(2)) ? self_th_1;

    /** IOOBFIR[3:47]
     *  spare
     */
    (rIOOBFIR, bit(3|4|5|6|7|8|9|10|11|12|13|14|15|16|17|18|19|20|21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39|40|41|42|43|44|45|46|47)) ? defaultMaskedError;

    /** IOOBFIR[48]
     *  scom error
     */
    (rIOOBFIR, bit(48)) ? defaultMaskedError;

    /** IOOBFIR[49]
     *  scom error
     */
    (rIOOBFIR, bit(49)) ? defaultMaskedError;

};

################################################################################
# P9 OBUS target OBPPEFIR
################################################################################

rule rOBPPEFIR
{
  CHECK_STOP:
    OBPPEFIR & ~OBPPEFIR_MASK & ~OBPPEFIR_ACT0 & ~OBPPEFIR_ACT1;
  RECOVERABLE:
    OBPPEFIR & ~OBPPEFIR_MASK & ~OBPPEFIR_ACT0 &  OBPPEFIR_ACT1;
  UNIT_CS:
    OBPPEFIR & ~OBPPEFIR_MASK &  OBPPEFIR_ACT0 &  OBPPEFIR_ACT1;
};

group gOBPPEFIR
    filter singlebit,
           cs_root_cause
{
    /** OBPPEFIR[0:3]
     *  PPE general error.
     */
    (rOBPPEFIR, bit(0|1|2|3)) ? threshold_and_mask_self;

    /** OBPPEFIR[4]
     *  PPE halted.
     */
    (rOBPPEFIR, bit(4)) ? defaultMaskedError;

    /** OBPPEFIR[5]
     *  PPE watchdog timer timed out.
     */
    (rOBPPEFIR, bit(5)) ? defaultMaskedError;

    /** OBPPEFIR[6]
     *  PPE MMIO data in error.
     */
    (rOBPPEFIR, bit(6)) ? defaultMaskedError;

    /** OBPPEFIR[7]
     *  PPE Arb missed scrub tick.
     */
    (rOBPPEFIR, bit(7)) ? threshold_and_mask_self;

    /** OBPPEFIR[8]
     *  PPE  Arb ary ue error.
     */
    (rOBPPEFIR, bit(8)) ? self_th_1;

    /** OBPPEFIR[9]
     *  PPE Arb ary ce error.
     */
    (rOBPPEFIR, bit(9)) ? threshold_and_mask_self;

    /** OBPPEFIR[10]
     *  spare
     */
    (rOBPPEFIR, bit(10)) ? defaultMaskedError;

    /** OBPPEFIR[11]
     *  scom error
     */
    (rOBPPEFIR, bit(11)) ? defaultMaskedError;

    /** OBPPEFIR[12]
     *  scom error
     */
    (rOBPPEFIR, bit(12)) ? defaultMaskedError;

};

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# Include the actions defined for this target
.include "p9_common_actions.rule";
.include "p9_common_obus_actions.rule";