# IBM_PROLOG_BEGIN_TAG
# This is an automatically generated prolog.
#
# $Source: src/usr/diag/prdf/common/plat/nimbus/nimbus_ec.rule $
#
# OpenPOWER HostBoot Project
#
# Contributors Listed Below - COPYRIGHT 2016,2018
# [+] International Business Machines Corp.
#
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
# implied. See the License for the specific language governing
# permissions and limitations under the License.
#
# IBM_PROLOG_END_TAG

chip nimbus_ec
{
    name        "NIMBUS EC target";
    targettype  TYPE_CORE;
    sigoff      0x9000;
    dump        DUMP_CONTENT_HW;
    scomlen     64;

 #############################################################################
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 #############################################################################

    ############################################################################
    # EC Chiplet FIR
    ############################################################################

    register EC_CHIPLET_CS_FIR
    {
        name        "EC Chiplet Checkstop FIR";
        scomaddr    0x20040000;
        capture     group default;
    };

    register EC_CHIPLET_RE_FIR
    {
        name        "EC Chiplet Recoverable FIR";
        scomaddr    0x20040001;
        capture     group default;
    };

    register EC_CHIPLET_FIR_MASK
    {
        name        "EC Chiplet FIR MASK";
        scomaddr    0x20040002;
        capture     group default;
    };

    ############################################################################
    # EC Chiplet Unit Checkstop FIR
    ############################################################################

    register EC_CHIPLET_UCS_FIR
    {
        name        "EC Chiplet Unit Checkstop FIR";
        scomaddr    0x20040018;
        capture     group default;
    };

    register EC_CHIPLET_UCS_FIR_MASK
    {
        name        "EC Chiplet Unit Checkstop FIR MASK";
        scomaddr    0x20040019;
        capture     group default;
    };

    ############################################################################
    # P9 EC target EC_LFIR
    ############################################################################

    register EC_LFIR
    {
        name        "P9 EC target EC_LFIR";
        scomaddr    0x2004000a;
        reset       (&, 0x2004000b);
        mask        (|, 0x2004000f);
        capture     group default;
    };

    register EC_LFIR_MASK
    {
        name        "P9 EC target EC_LFIR MASK";
        scomaddr    0x2004000d;
        capture     group default;
    };

    register EC_LFIR_ACT0
    {
        name        "P9 EC target EC_LFIR ACT0";
        scomaddr    0x20040010;
        capture     group default;
        capture     req nonzero("EC_LFIR");
    };

    register EC_LFIR_ACT1
    {
        name        "P9 EC target EC_LFIR ACT1";
        scomaddr    0x20040011;
        capture     group default;
        capture     req nonzero("EC_LFIR");
    };

    ############################################################################
    # P9 EC target COREFIR
    ############################################################################

    register COREFIR
    {
        name        "P9 EC target COREFIR";
        scomaddr    0x20010a40;
        mask        (|, 0x20010a45);
        capture     group default;
    };

    register COREFIR_MASK
    {
        name        "P9 EC target COREFIR MASK";
        scomaddr    0x20010a43;
        capture     group default;
    };

    register COREFIR_ACT0
    {
        name        "P9 EC target COREFIR ACT0";
        scomaddr    0x20010a46;
        capture     group default;
    };

    register COREFIR_ACT1
    {
        name        "P9 EC target COREFIR ACT1";
        scomaddr    0x20010a47;
        capture     group default;
    };

    register COREFIR_WOF
    {
        name        "P9 EC target COREFIR WOF";
        scomaddr    0x20010a48;
        reset       (|, 0x20010a48);
        capture     group default;
    };

# Include registers not defined by the xml
.include "p9_common_ec_regs.rule";

};

 ##############################################################################
 #                                                                            #
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 # #   # #   # #    #####  ###      #  # #    ##  ##### ###  ###  #   #  ###  #
 # #   # #   # #    #     #        #  #   #  #  #   #    #  #   # ##  # #     #
 # ####  #   # #    ####   ###    #  ####### #      #    #  #   # # # #  ###  #
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 # #   #  ###  #### #####  ###  #    #     #  ##    #   ###  ###  #   #  ###  #
 #                                                                            #
 ##############################################################################

################################################################################
# EC Chiplet FIR
################################################################################

rule rEC_CHIPLET_FIR
{
  CHECK_STOP:
     EC_CHIPLET_CS_FIR       & ~EC_CHIPLET_FIR_MASK & `1fffffffffffffff`;
  RECOVERABLE:
    (EC_CHIPLET_RE_FIR >> 2) & ~EC_CHIPLET_FIR_MASK & `3fffffffffffffff`;
};

group gEC_CHIPLET_FIR attntype CHECK_STOP, RECOVERABLE
    filter singlebit
{
    /** EC_CHIPLET_FIR[2]
     *  Unit Checkstop from COREFIR (bit0 in RER)
     */
    (rEC_CHIPLET_FIR, bit(2)) ? analyzeCOREFIR;

    /** EC_CHIPLET_FIR[3]
     *  Attention from EC_LFIR
     */
    (rEC_CHIPLET_FIR, bit(3)) ? analyzeEC_LFIR;

    /** EC_CHIPLET_FIR[4]
     *  Attention from COREFIR
     */
    (rEC_CHIPLET_FIR, bit(4)) ? analyzeCOREFIR;

};

################################################################################
# EC Chiplet Unit Checkstop FIR
################################################################################

rule rEC_CHIPLET_UCS_FIR
{
  UNIT_CS:
    EC_CHIPLET_UCS_FIR & ~(EC_CHIPLET_UCS_FIR_MASK >> 1) & `7fffffffffffffff`;
};

group gEC_CHIPLET_UCS_FIR attntype UNIT_CS
    filter singlebit
{
    /** EC_CHIPLET_UCS_FIR[1]
     *  Attention from COREFIR
     */
    (rEC_CHIPLET_UCS_FIR, bit(1)) ? analyzeCOREFIR;

};

################################################################################
# P9 EC target EC_LFIR
################################################################################

rule rEC_LFIR
{
  CHECK_STOP:
    EC_LFIR & ~EC_LFIR_MASK & ~EC_LFIR_ACT0 & ~EC_LFIR_ACT1;
  RECOVERABLE:
    EC_LFIR & ~EC_LFIR_MASK & ~EC_LFIR_ACT0 &  EC_LFIR_ACT1;
};

group gEC_LFIR
    filter singlebit,
           cs_root_cause
{
    /** EC_LFIR[0]
     *  CFIR internal parity error
     */
    (rEC_LFIR, bit(0)) ? self_th_32perDay;

    /** EC_LFIR[1]
     *  Chiplet Control Reg: PCB Access Error
     */
    (rEC_LFIR, bit(1)) ? self_th_32perDay;

    /** EC_LFIR[2]
     *  Clock Controller: PCB Access Error
     */
    (rEC_LFIR, bit(2)) ? self_th_32perDay;

    /** EC_LFIR[3]
     *  Clock Controller: Summarized Error
     */
    (rEC_LFIR, bit(3)) ? self_th_32perDay;

    /** EC_LFIR[4]
     *  PSCOM Logic: PCB Access Error
     */
    (rEC_LFIR, bit(4)) ? defaultMaskedError;

    /** EC_LFIR[5]
     *  PSCOM Logic: Summarized internal errors
     */
    (rEC_LFIR, bit(5)) ? defaultMaskedError;

    /** EC_LFIR[6]
     *  Therm Logic: Summarized internal errors
     */
    (rEC_LFIR, bit(6)) ? defaultMaskedError;

    /** EC_LFIR[7]
     *  Therm Logic: PCB Access Error
     */
    (rEC_LFIR, bit(7)) ? defaultMaskedError;

    /** EC_LFIR[8]
     *  Therm Logic: Temperature critical trip
     */
    (rEC_LFIR, bit(8)) ? defaultMaskedError;

    /** EC_LFIR[9]
     *  Therm Logic: Temperature fatal trip
     */
    (rEC_LFIR, bit(9)) ? defaultMaskedError;

    /** EC_LFIR[10]
     *  UNUSED in P9
     */
    (rEC_LFIR, bit(10)) ? defaultMaskedError;

    /** EC_LFIR[11]
     *  Debug Logic: Scom Satellite Error
     */
    (rEC_LFIR, bit(11)) ? defaultMaskedError;

    /** EC_LFIR[12:40]
     *  spare
     */
    (rEC_LFIR, bit(12|13|14|15|16|17|18|19|20|21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39|40)) ? defaultMaskedError;

    /** EC_LFIR[41]
     *  Malfunction Alert or Local Checkstop
     */
    (rEC_LFIR, bit(41)) ? defaultMaskedError;

};

################################################################################
# P9 EC target COREFIR
################################################################################

rule rCOREFIR
{
  CHECK_STOP:
    COREFIR & ~COREFIR_MASK & ~COREFIR_ACT0 & ~COREFIR_ACT1;
  RECOVERABLE:
    COREFIR_WOF & ~COREFIR_MASK & ~COREFIR_ACT0 &  COREFIR_ACT1;
  UNIT_CS:
    COREFIR & ~COREFIR_MASK &  COREFIR_ACT0 &  COREFIR_ACT1;
};

group gCOREFIR
    filter priority(0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,58,59,60,61,62,63,57),
           cs_root_cause
{
    /** COREFIR[0]
     *  IFU SRAM Recoverable error
     */
    (rCOREFIR, bit(0)) ? self_th_5perHour;

    /** COREFIR[1]
     *  TC Checkstop
     */
    (rCOREFIR, bit(1)) ? self_th_1;

    /** COREFIR[2]
     *  Regfile Recoverable error from IFU
     */
    (rCOREFIR, bit(2)) ? self_th_5perHour;

    /** COREFIR[3]
     *  Regfile core checkstop
     */
    (rCOREFIR, bit(3)) ? self_th_1;

    /** COREFIR[4]
     *  IF Logic Recovery Err
     */
    (rCOREFIR, bit(4)) ? self_th_5perHour;

    /** COREFIR[5]
     *  If Logic Checkstop
     */
    (rCOREFIR, bit(5)) ? self_th_1;

    /** COREFIR[6:7]
     *  spare
     */
    (rCOREFIR, bit(6|7)) ? defaultMaskedError;

    /** COREFIR[8]
     *  Recovery core checkstop
     */
    (rCOREFIR, bit(8)) ? self_th_1;

    /** COREFIR[9]
     *  ISU Register File Recoverable Error
     */
    (rCOREFIR, bit(9)) ? self_th_5perHour;

    /** COREFIR[10]
     *  ISU Regifle Core Checkstop Err
     */
    (rCOREFIR, bit(10)) ? self_th_1;

    /** COREFIR[11]
     *  ISU Logic Recoverable Error
     */
    (rCOREFIR, bit(11)) ? self_th_5perHour;

    /** COREFIR[12]
     *  ISU Logic Core Checkstop Err
     */
    (rCOREFIR, bit(12)) ? self_th_1;

    /** COREFIR[13]
     *  ISU errr, recov if not in mt window
     */
    (rCOREFIR, bit(13)) ? self_th_5perHour;

    /** COREFIR[14]
     *  Machine check and ME = 0 Err
     */
    (rCOREFIR, bit(14)) ? self_th_1_SUE;

    /** COREFIR[15]
     *  LSU or IFU detected UE from L2
     */
    (rCOREFIR, bit(15)) ? defaultMaskedError;

    /** COREFIR[16]
     *  L2 UE over threshold error
     */
    (rCOREFIR, bit(16)) ? defaultMaskedError;

    /** COREFIR[17]
     *  UE on a cache inhibited operation
     */
    (rCOREFIR, bit(17)) ? defaultMaskedError;

    /** COREFIR[18]
     *  SW initiated reboot with diagnostics
     */
    (rCOREFIR, bit(18)) ? level2_th_1;

    /** COREFIR[19]
     *  spare
     */
    (rCOREFIR, bit(19)) ? defaultMaskedError;

    /** COREFIR[20]
     *  ISU checkstop MSR corrupted
     */
    (rCOREFIR, bit(20)) ? self_th_1;

    /** COREFIR[21:23]
     *  spare
     */
    (rCOREFIR, bit(21|22|23)) ? defaultMaskedError;

    /** COREFIR[24]
     *  VSU recoverable logic error
     */
    (rCOREFIR, bit(24)) ? self_th_5perHour;

    /** COREFIR[25]
     *  VS Logic core checkstop
     */
    (rCOREFIR, bit(25)) ? self_th_1;

    /** COREFIR[26]
     *  Core errors while in maintenance mode
     */
    (rCOREFIR, bit(26)) ? level2_th_1;

    /** COREFIR[27]
     *  DFU recoverable error
     */
    (rCOREFIR, bit(27)) ? self_th_5perHour;

    /** COREFIR[28]
     *  PC System Checkstop (recovery disabled)
     */
    (rCOREFIR, bit(28)) ? self_th_1;

    /** COREFIR[29]
     *  LSU SRAM recoverable error
     */
    (rCOREFIR, bit(29)) ? self_th_5perHour;

    /** COREFIR[30]
     *  LSU Set Delete Err
     */
    (rCOREFIR, bit(30)) ? self_th_1;

    /** COREFIR[31]
     *  LSU Reg File Recoverable
     */
    (rCOREFIR, bit(31)) ? self_th_5perHour;

    /** COREFIR[32]
     *  LSU Reg core checkstop
     */
    (rCOREFIR, bit(32)) ? self_th_1;

    /** COREFIR[33]
     *  Special recovery error, tlb multi-hit
     */
    (rCOREFIR, bit(33)) ? threshold_and_mask_self;

    /** COREFIR[34]
     *  LSU SLB multihit error
     */
    (rCOREFIR, bit(34)) ? threshold_and_mask_self;

    /** COREFIR[35]
     *  LSU ERAT multihit error
     */
    (rCOREFIR, bit(35)) ? threshold_and_mask_self;

    /** COREFIR[36]
     *  Forward Progress Error
     */
    (rCOREFIR, bit(36)) ? self_th_1;

    /** COREFIR[37]
     *  LSU logic recoverable error
     */
    (rCOREFIR, bit(37)) ? self_th_5perHour;

    /** COREFIR[38]
     *  LSU logic core checkstop error
     */
    (rCOREFIR, bit(38)) ? self_th_1;

    /** COREFIR[39]
     *  LSU err, recov if not in mt window
     */
    (rCOREFIR, bit(39)) ? self_th_5perHour;

    /** COREFIR[40]
     *  spare
     */
    (rCOREFIR, bit(40)) ? defaultMaskedError;

    /** COREFIR[41]
     *  LSU system checkstop
     */
    (rCOREFIR, bit(41)) ? self_th_1;

    /** COREFIR[42]
     *  spare
     */
    (rCOREFIR, bit(42)) ? defaultMaskedError;

    /** COREFIR[43]
     *  Thread Hang caused recovery
     */
    (rCOREFIR, bit(43)) ? self_level2_th_5perHour;

    /** COREFIR[44]
     *  spare
     */
    (rCOREFIR, bit(44)) ? defaultMaskedError;

    /** COREFIR[45]
     *  PC core cs
     */
    (rCOREFIR, bit(45)) ? self_th_1;

    /** COREFIR[46]
     *  spare
     */
    (rCOREFIR, bit(46)) ? defaultMaskedError;

    /** COREFIR[47]
     *  Timebase facility unrecoverable error.
     */
    (rCOREFIR, bit(47)) ? defaultMaskedError;

    /** COREFIR[48]
     *  Hypervisor resource parity error
     */
    (rCOREFIR, bit(48)) ? self_th_1;

    /** COREFIR[49:51]
     *  spare
     */
    (rCOREFIR, bit(49|50|51)) ? defaultMaskedError;

    /** COREFIR[52]
     *  Core Hang, recovery failed
     */
    (rCOREFIR, bit(52)) ? self_th_1;

    /** COREFIR[53]
     *  Internal Core Hang, recovery attemped
     */
    (rCOREFIR, bit(53)) ? defaultMaskedError;

    /** COREFIR[54]
     *  spare
     */
    (rCOREFIR, bit(54)) ? defaultMaskedError;

    /** COREFIR[55]
     *  Nest hang detected, recovery attempted
     */
    (rCOREFIR, bit(55)) ? self_M_level2_L_th_1;

    /** COREFIR[56]
     *  Other Core Recoverable error
     */
    (rCOREFIR, bit(56)) ? defaultMaskedError;

    /** COREFIR[57]
     *  Other Core Core Checkstop
     */
    (rCOREFIR, bit(57)) ? self_th_1;

    /** COREFIR[58]
     *  Other Core System Checkstop
     */
    (rCOREFIR, bit(58)) ? defaultMaskedError;

    /** COREFIR[59]
     *  SCOM error handling
     */
    (rCOREFIR, bit(59)) ? defaultMaskedError;

    /** COREFIR[60]
     *  debug checkstop on trigger
     */
    (rCOREFIR, bit(60)) ? defaultMaskedError;

    /** COREFIR[61]
     *  SCOM or Recoverable error inject
     */
    (rCOREFIR, bit(61)) ? defaultMaskedError;

    /** COREFIR[62]
     *  Firmware injected checkstop
     */
    (rCOREFIR, bit(62)) ? defaultMaskedError;

    /** COREFIR[63]
     *  PHYP injected core checkstop
     */
    (rCOREFIR, bit(63)) ? level2_th_1;

};

 ##############################################################################
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 ##############################################################################

# Include the actions defined for this target
.include "p9_common_actions.rule";
.include "p9_common_ec_actions.rule";