# IBM_PROLOG_BEGIN_TAG
# This is an automatically generated prolog.
#
# $Source: src/usr/diag/prdf/common/plat/explorer/explorer_ocmb.rule $
#
# OpenPOWER HostBoot Project
#
# Contributors Listed Below - COPYRIGHT 2018,2019
# [+] International Business Machines Corp.
#
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
# implied. See the License for the specific language governing
# permissions and limitations under the License.
#
# IBM_PROLOG_END_TAG

chip explorer_ocmb
{
    name        "EXPLORER OCMB target";
    targettype  TYPE_OCMB_CHIP;
    sigoff      0x9000;
    dump        DUMP_CONTENT_HW;
    scomlen     64;

 #############################################################################
 #                                                                           #
 #  ######                                                                   #
 #  #     #  ######   ####     ###    ####    #####  ######  #####    ####   #
 #  #     #  #       #    #     #    #          #    #       #    #  #       #
 #  ######   #####   #          #     ####      #    #####   #    #   ####   #
 #  #   #    #       #  ###     #         #     #    #       #####        #  #
 #  #    #   #       #    #     #    #    #     #    #       #   #   #    #  #
 #  #     #  ######   ####     ###    ####      #    ######  #    #   ####   #
 #                                                                           #
 #############################################################################

    ############################################################################
    # OCMB Chiplet FIR
    ############################################################################

    register OCMB_CHIPLET_CS_FIR
    {
        name        "OCMB Chiplet Checkstop FIR";
        scomaddr    0x08040000;
        capture     group default;
    };

    register OCMB_CHIPLET_RE_FIR
    {
        name        "OCMB Chiplet Recoverable FIR";
        scomaddr    0x08040001;
        capture     group default;
    };

    register OCMB_CHIPLET_FIR_MASK
    {
        name        "OCMB Chiplet FIR MASK";
        scomaddr    0x08040002;
        capture     group default;
    };

    ############################################################################
    # OCMB Chiplet Special Attention FIR
    ############################################################################

    register OCMB_CHIPLET_SPA_FIR
    {
        name        "OCMB Chiplet Special Attention FIR";
        scomaddr    0x08040004;
        capture     group default;
    };

    register OCMB_CHIPLET_SPA_FIR_MASK
    {
        name        "OCMB Chiplet Special Attention FIR MASK";
        scomaddr    0x08040007;
        capture     group default;
    };

    ############################################################################
    # Explorer chip OCMB_LFIR
    ############################################################################

    register OCMB_LFIR
    {
        name        "Explorer chip OCMB_LFIR";
        scomaddr    0x0804000a;
        reset       (&, 0x0804000b);
        mask        (|, 0x0804000f);
        capture     group default;
    };

    register OCMB_LFIR_MASK
    {
        name        "Explorer chip OCMB_LFIR MASK";
        scomaddr    0x0804000d;
        capture     group default;
    };

    register OCMB_LFIR_ACT0
    {
        name        "Explorer chip OCMB_LFIR ACT0";
        scomaddr    0x08040010;
        capture     group default;
        capture     req nonzero("OCMB_LFIR");
    };

    register OCMB_LFIR_ACT1
    {
        name        "Explorer chip OCMB_LFIR ACT1";
        scomaddr    0x08040011;
        capture     group default;
        capture     req nonzero("OCMB_LFIR");
    };

    ############################################################################
    # Explorer chip MMIOFIR
    ############################################################################

    register MMIOFIR
    {
        name        "Explorer chip MMIOFIR";
        scomaddr    0x08010870;
        reset       (&, 0x08010871);
        mask        (|, 0x08010875);
        capture     group default;
    };

    register MMIOFIR_MASK
    {
        name        "Explorer chip MMIOFIR MASK";
        scomaddr    0x08010873;
        capture     group default;
    };

    register MMIOFIR_ACT0
    {
        name        "Explorer chip MMIOFIR ACT0";
        scomaddr    0x08010876;
        capture     group default;
        capture     req nonzero("MMIOFIR");
    };

    register MMIOFIR_ACT1
    {
        name        "Explorer chip MMIOFIR ACT1";
        scomaddr    0x08010877;
        capture     group default;
        capture     req nonzero("MMIOFIR");
    };

    ############################################################################
    # Explorer chip SRQFIR
    ############################################################################

    register SRQFIR
    {
        name        "Explorer chip SRQFIR";
        scomaddr    0x08011400;
        reset       (&, 0x08011401);
        mask        (|, 0x08011405);
        capture     group default;
    };

    register SRQFIR_MASK
    {
        name        "Explorer chip SRQFIR MASK";
        scomaddr    0x08011403;
        capture     group default;
    };

    register SRQFIR_ACT0
    {
        name        "Explorer chip SRQFIR ACT0";
        scomaddr    0x08011406;
        capture     group default;
        capture     req nonzero("SRQFIR");
    };

    register SRQFIR_ACT1
    {
        name        "Explorer chip SRQFIR ACT1";
        scomaddr    0x08011407;
        capture     group default;
        capture     req nonzero("SRQFIR");
    };

    ############################################################################
    # Explorer chip MCBISTFIR
    ############################################################################

    register MCBISTFIR
    {
        name        "Explorer chip MCBISTFIR";
        scomaddr    0x08011800;
        reset       (&, 0x08011801);
        mask        (|, 0x08011805);
        capture     group default;
    };

    register MCBISTFIR_MASK
    {
        name        "Explorer chip MCBISTFIR MASK";
        scomaddr    0x08011803;
        capture     group default;
    };

    register MCBISTFIR_ACT0
    {
        name        "Explorer chip MCBISTFIR ACT0";
        scomaddr    0x08011806;
        capture     group default;
        capture     req nonzero("MCBISTFIR");
    };

    register MCBISTFIR_ACT1
    {
        name        "Explorer chip MCBISTFIR ACT1";
        scomaddr    0x08011807;
        capture     group default;
        capture     req nonzero("MCBISTFIR");
    };

    ############################################################################
    # Explorer chip RDFFIR
    ############################################################################

    register RDFFIR
    {
        name        "Explorer chip RDFFIR";
        scomaddr    0x08011c00;
        reset       (&, 0x08011c01);
        mask        (|, 0x08011c05);
        capture     group default;
    };

    register RDFFIR_MASK
    {
        name        "Explorer chip RDFFIR MASK";
        scomaddr    0x08011c03;
        capture     group default;
    };

    register RDFFIR_ACT0
    {
        name        "Explorer chip RDFFIR ACT0";
        scomaddr    0x08011c06;
        capture     group default;
        capture     req nonzero("RDFFIR");
    };

    register RDFFIR_ACT1
    {
        name        "Explorer chip RDFFIR ACT1";
        scomaddr    0x08011c07;
        capture     group default;
        capture     req nonzero("RDFFIR");
    };

    ############################################################################
    # Explorer chip TLXFIR
    ############################################################################

    register TLXFIR
    {
        name        "Explorer chip TLXFIR";
        scomaddr    0x08012400;
        reset       (&, 0x08012401);
        mask        (|, 0x08012405);
        capture     group default;
    };

    register TLXFIR_MASK
    {
        name        "Explorer chip TLXFIR MASK";
        scomaddr    0x08012403;
        capture     group default;
    };

    register TLXFIR_ACT0
    {
        name        "Explorer chip TLXFIR ACT0";
        scomaddr    0x08012406;
        capture     group default;
        capture     req nonzero("TLXFIR");
    };

    register TLXFIR_ACT1
    {
        name        "Explorer chip TLXFIR ACT1";
        scomaddr    0x08012407;
        capture     group default;
        capture     req nonzero("TLXFIR");
    };

    ############################################################################
    # Explorer chip OMIDLFIR
    ############################################################################

    register OMIDLFIR
    {
        name        "Explorer chip OMIDLFIR";
        scomaddr    0x08012800;
        reset       (&, 0x08012801);
        mask        (|, 0x08012805);
        capture     group default;
    };

    register OMIDLFIR_MASK
    {
        name        "Explorer chip OMIDLFIR MASK";
        scomaddr    0x08012803;
        capture     group default;
    };

    register OMIDLFIR_ACT0
    {
        name        "Explorer chip OMIDLFIR ACT0";
        scomaddr    0x08012806;
        capture     group default;
        capture     req nonzero("OMIDLFIR");
    };

    register OMIDLFIR_ACT1
    {
        name        "Explorer chip OMIDLFIR ACT1";
        scomaddr    0x08012807;
        capture     group default;
        capture     req nonzero("OMIDLFIR");
    };

# Include registers not defined by the xml
.include "explorer_ocmb_regs.rule";

};

 ##############################################################################
 #                                                                            #
 # ####                                 #                                     #
 # #   # #   # #    #####  ###      #  # #    ##  ##### ###  ###  #   #  ###  #
 # #   # #   # #    #     #        #  #   #  #  #   #    #  #   # ##  # #     #
 # ####  #   # #    ####   ###    #  ####### #      #    #  #   # # # #  ###  #
 # #  #  #   # #    #         #  #   #     # #  #   #    #  #   # #  ##     # #
 # #   #  ###  #### #####  ###  #    #     #  ##    #   ###  ###  #   #  ###  #
 #                                                                            #
 ##############################################################################

################################################################################
# OCMB Chiplet FIR
################################################################################

rule rOCMB_CHIPLET_FIR
{
  UNIT_CS:
     OCMB_CHIPLET_CS_FIR       & ~OCMB_CHIPLET_FIR_MASK & `1fffffffffffffff`;
  RECOVERABLE:
    (OCMB_CHIPLET_RE_FIR >> 2) & ~OCMB_CHIPLET_FIR_MASK & `1fffffffffffffff`;
};

# NOTE: RDFFIR[14|34] are possible side effects of OCMB_LFIR[38], as such,
#       OCMB_LFIR must be analyzed first for correct handling. If changes are
#       made so the RDFFIR is analyzed first, additional changes to the handling
#       of those bits will be required.
group gOCMB_CHIPLET_FIR attntype UNIT_CS, RECOVERABLE
    filter singlebit
{
    /** OCMB_CHIPLET_FIR[3]
     *  Attention from OCMB_LFIR
     */
    (rOCMB_CHIPLET_FIR, bit(3)) ? analyzeOCMB_LFIR;

    /** OCMB_CHIPLET_FIR[4]
     *  Attention from MMIOFIR
     */
    (rOCMB_CHIPLET_FIR, bit(4)) ? analyzeMMIOFIR;

    /** OCMB_CHIPLET_FIR[7]
     *  Attention from SRQFIR
     */
    (rOCMB_CHIPLET_FIR, bit(7)) ? analyzeSRQFIR;

    /** OCMB_CHIPLET_FIR[8]
     *  Attention from MCBISTFIR
     */
    (rOCMB_CHIPLET_FIR, bit(8)) ? analyzeMCBISTFIR;

    /** OCMB_CHIPLET_FIR[9]
     *  Attention from RDFFIR
     */
    (rOCMB_CHIPLET_FIR, bit(9)) ? analyzeRDFFIR;

    /** OCMB_CHIPLET_FIR[11]
     *  Attention from TLXFIR
     */
    (rOCMB_CHIPLET_FIR, bit(11)) ? analyzeTLXFIR;

    /** OCMB_CHIPLET_FIR[12]
     *  Attention from OMIDLFIR
     */
    (rOCMB_CHIPLET_FIR, bit(12)) ? analyzeOMIDLFIR;

};

################################################################################
# OCMB Chiplet Special Attention FIR
################################################################################

rule rOCMB_CHIPLET_SPA_FIR
{
  HOST_ATTN:
    OCMB_CHIPLET_SPA_FIR & ~OCMB_CHIPLET_SPA_FIR_MASK;
};

group gOCMB_CHIPLET_SPA_FIR attntype HOST_ATTN
    filter singlebit
{
    /** OCMB_CHIPLET_SPA_FIR[1]
     *  Attention from MMIOFIR
     */
    (rOCMB_CHIPLET_SPA_FIR, bit(1)) ? analyzeMMIOFIR;

    /** OCMB_CHIPLET_SPA_FIR[4]
     *  Attention from SRQFIR
     */
    (rOCMB_CHIPLET_SPA_FIR, bit(4)) ? analyzeSRQFIR;

    /** OCMB_CHIPLET_SPA_FIR[5]
     *  Attention from MCBISTFIR
     */
    (rOCMB_CHIPLET_SPA_FIR, bit(5)) ? analyzeMCBISTFIR;

    /** OCMB_CHIPLET_SPA_FIR[6]
     *  Attention from RDFFIR
     */
    (rOCMB_CHIPLET_SPA_FIR, bit(6)) ? analyzeRDFFIR;

    /** OCMB_CHIPLET_SPA_FIR[8]
     *  Attention from TLXFIR
     */
    (rOCMB_CHIPLET_SPA_FIR, bit(8)) ? analyzeTLXFIR;

    /** OCMB_CHIPLET_SPA_FIR[9]
     *  Attention from OMIDLFIR
     */
    (rOCMB_CHIPLET_SPA_FIR, bit(9)) ? analyzeOMIDLFIR;

};

################################################################################
# Explorer chip OCMB_LFIR
################################################################################

rule rOCMB_LFIR
{
  UNIT_CS:
    OCMB_LFIR & ~OCMB_LFIR_MASK & ~OCMB_LFIR_ACT0 & ~OCMB_LFIR_ACT1;
  RECOVERABLE:
    OCMB_LFIR & ~OCMB_LFIR_MASK & ~OCMB_LFIR_ACT0 &  OCMB_LFIR_ACT1;
};

group gOCMB_LFIR
    filter singlebit,
           cs_root_cause
{
    /** OCMB_LFIR[0]
     *  CFIR access PCB error
     */
    (rOCMB_LFIR, bit(0)) ? self_th_32perDay;

    /** OCMB_LFIR[1]
     *  CFIR internal parity error
     */
    (rOCMB_LFIR, bit(1)) ? self_th_32perDay;

    /** OCMB_LFIR[2]
     *  LFIR internal parity error
     */
    (rOCMB_LFIR, bit(2)) ? self_th_32perDay;

    /** OCMB_LFIR[3]
     *  Debug scom satellite error
     */
    (rOCMB_LFIR, bit(3)) ? defaultMaskedError;

    /** OCMB_LFIR[4]
     *  PSCOM Logic: PCB Access Error
     */
    (rOCMB_LFIR, bit(4)) ? defaultMaskedError;

    /** OCMB_LFIR[5]
     *  PSCOM Logic: Summarized internal errors
     */
    (rOCMB_LFIR, bit(5)) ? defaultMaskedError;

    /** OCMB_LFIR[6]
     *  Trace Logic : Scom Satellite Error - Trace0
     */
    (rOCMB_LFIR, bit(6)) ? defaultMaskedError;

    /** OCMB_LFIR[7]
     *  Trace Logic : Scom Satellite Error - Trace1
     */
    (rOCMB_LFIR, bit(7)) ? defaultMaskedError;

    /** OCMB_LFIR[8]
     *  PIB2GIF parity error on FSM or Registers
     */
    (rOCMB_LFIR, bit(8)) ? self_th_32perDay;

    /** OCMB_LFIR[9]
     *  MSG access PCB error
     */
    (rOCMB_LFIR, bit(9)) ? defaultMaskedError;

    /** OCMB_LFIR[10:18]
     *  unused
     */
    (rOCMB_LFIR, bit(10|11|12|13|14|15|16|17|18)) ? defaultMaskedError;

    /** OCMB_LFIR[19]
     *  DLL IRQ
     */
    (rOCMB_LFIR, bit(19)) ? defaultMaskedError;

    /** OCMB_LFIR[20]
     *  Watchdog timer interrupt
     */
    (rOCMB_LFIR, bit(20)) ? self_th_1;

    /** OCMB_LFIR[21]
     *  internal temp sensor tripped a threshold
     */
    (rOCMB_LFIR, bit(21)) ? defaultMaskedError;

    /** OCMB_LFIR[22]
     *  GPBC_FATAL_ERROR
     */
    (rOCMB_LFIR, bit(22)) ? self_th_1;

    /** OCMB_LFIR[23]
     *  GPBC_NON_FATAL_ERROR
     */
    (rOCMB_LFIR, bit(23)) ? self_th_1;

    /** OCMB_LFIR[24]
     *  early power off warning
     */
    (rOCMB_LFIR, bit(24)) ? defaultMaskedError;

    /** OCMB_LFIR[25]
     *  TOP fatal interrupts
     */
    (rOCMB_LFIR, bit(25)) ? self_th_1;

    /** OCMB_LFIR[26]
     *  TOP non fatal interrupts
     */
    (rOCMB_LFIR, bit(26)) ? level2_M_self_L_th_1;

    /** OCMB_LFIR[27:34]
     *  Interrupt from OPSe to OCMB
     */
    (rOCMB_LFIR, bit(27|28|29|30|31|32|33|34)) ? defaultMaskedError;

    /** OCMB_LFIR[35]
     *  DDR thermal event
     */
    (rOCMB_LFIR, bit(35)) ? defaultMaskedError;

    /** OCMB_LFIR[36]
     *  DDR4 PHY fatal
     */
    (rOCMB_LFIR, bit(36)) ? self_th_1;

    /** OCMB_LFIR[37]
     *  DDR4 PHY non fatal
     */
    (rOCMB_LFIR, bit(37)) ? self_th_32perDay;

    /** OCMB_LFIR[38]
     *  DDR4 PHY interrupt
     */
    (rOCMB_LFIR, bit(38)) ? ddr4_phy_interrupt;

    /** OCMB_LFIR[39:46]
     *  foxhound fatal
     */
    (rOCMB_LFIR, bit(39|40|41|42|43|44|45|46)) ? foxhound_fatal;

    /** OCMB_LFIR[47:54]
     *  foxhound non fatal
     */
    (rOCMB_LFIR, bit(47|48|49|50|51|52|53|54)) ? defaultMaskedError;

    /** OCMB_LFIR[55:62]
     *  foxhound serdes interrupt
     */
    (rOCMB_LFIR, bit(55|56|57|58|59|60|61|62)) ? defaultMaskedError;

    /** OCMB_LFIR[63]
     *  GIF2PCB parity error on FSM or Registers
     */
    (rOCMB_LFIR, bit(63)) ? self_th_32perDay;

};

################################################################################
# Explorer chip MMIOFIR
################################################################################

rule rMMIOFIR
{
  UNIT_CS:
    MMIOFIR & ~MMIOFIR_MASK & ~MMIOFIR_ACT0 & ~MMIOFIR_ACT1;
  RECOVERABLE:
    MMIOFIR & ~MMIOFIR_MASK & ~MMIOFIR_ACT0 &  MMIOFIR_ACT1;
  HOST_ATTN:
    MMIOFIR & ~MMIOFIR_MASK &  MMIOFIR_ACT0 & ~MMIOFIR_ACT1;
};

group gMMIOFIR
    filter singlebit,
           cs_root_cause
{
    /** MMIOFIR[0]
     *  AFU desc unimp
     */
    (rMMIOFIR, bit(0)) ? defaultMaskedError;

    /** MMIOFIR[1]
     *  MMIO err
     */
    (rMMIOFIR, bit(1)) ? defaultMaskedError;

    /** MMIOFIR[2]
     *  SCOM err
     */
    (rMMIOFIR, bit(2)) ? self_th_32perDay;

    /** MMIOFIR[3]
     *  FSM perr
     */
    (rMMIOFIR, bit(3)) ? self_th_1;

    /** MMIOFIR[4]
     *  FIFO overflow
     */
    (rMMIOFIR, bit(4)) ? self_th_1;

    /** MMIOFIR[5]
     *  Ctl reg parity err
     */
    (rMMIOFIR, bit(5)) ? self_th_1;

    /** MMIOFIR[6]
     *  Info reg parity error
     */
    (rMMIOFIR, bit(6)) ? self_th_1;

    /** MMIOFIR[7]
     *  SNSC both starts err
     */
    (rMMIOFIR, bit(7)) ? defaultMaskedError;

    /** MMIOFIR[8]
     *  SNSC mult seq parity err
     */
    (rMMIOFIR, bit(8)) ? defaultMaskedError;

    /** MMIOFIR[9]
     *  SNSC FSM parity err
     */
    (rMMIOFIR, bit(9)) ? defaultMaskedError;

    /** MMIOFIR[10]
     *  SNSC reg parity err
     */
    (rMMIOFIR, bit(10)) ? defaultMaskedError;

    /** MMIOFIR[11]
     *  acTAG PASID cfg err
     */
    (rMMIOFIR, bit(11)) ? defaultMaskedError;

};

################################################################################
# Explorer chip SRQFIR
################################################################################

rule rSRQFIR
{
  UNIT_CS:
    SRQFIR & ~SRQFIR_MASK & ~SRQFIR_ACT0 & ~SRQFIR_ACT1;
  RECOVERABLE:
    SRQFIR & ~SRQFIR_MASK & ~SRQFIR_ACT0 &  SRQFIR_ACT1;
  HOST_ATTN:
    SRQFIR & ~SRQFIR_MASK &  SRQFIR_ACT0 & ~SRQFIR_ACT1;
};

group gSRQFIR
    filter singlebit,
           cs_root_cause(18)
{
    /** SRQFIR[0]
     *  SRQ recoverable error
     */
    (rSRQFIR, bit(0)) ? mem_port_th_1;

    /** SRQFIR[1]
     *  SRQ nonrecoverable error
     */
    (rSRQFIR, bit(1)) ? mem_port_th_1;

    /** SRQFIR[2]
     *  Refresh overrun
     */
    (rSRQFIR, bit(2)) ? mem_port_th_32perDay;

    /** SRQFIR[3]
     *  WAT error
     */
    (rSRQFIR, bit(3)) ? defaultMaskedError;

    /** SRQFIR[4]
     *  RCD parity error
     */
    (rSRQFIR, bit(4)) ? srq_rcd_parity_error;

    /** SRQFIR[5]
     *  MCB logic error
     */
    (rSRQFIR, bit(5)) ? mem_port_th_1;

    /** SRQFIR[6]
     *  Emergency throttle
     */
    (rSRQFIR, bit(6)) ? defaultMaskedError;

    /** SRQFIR[7]
     *  NCF MCB parity error
     */
    (rSRQFIR, bit(7)) ? mem_port_th_1;

    /** SRQFIR[8]
     *  DDR MBA event n
     */
    (rSRQFIR, bit(8)) ? defaultMaskedError;

    /** SRQFIR[9]
     *  WRQ RRQ hang err
     */
    (rSRQFIR, bit(9)) ? mem_port_th_1;

    /** SRQFIR[10]
     *  SM one hot error
     */
    (rSRQFIR, bit(10)) ? mem_port_th_1;

    /** SRQFIR[11]
     *  Reg parity error
     */
    (rSRQFIR, bit(11)) ? mem_port_th_1;

    /** SRQFIR[12]
     *  Cmd parity error
     */
    (rSRQFIR, bit(12)) ? mem_port_th_1;

    /** SRQFIR[13]
     *  Port fail
     */
    (rSRQFIR, bit(13)) ? mem_port_failure;

    /** SRQFIR[14]
     *  informational register parity error bit
     */
    (rSRQFIR, bit(14)) ? threshold_and_mask_mem_port;

    /** SRQFIR[15]
     *  Debug parity error
     */
    (rSRQFIR, bit(15)) ? threshold_and_mask_mem_port;

    /** SRQFIR[16]
     *  WDF unrecoverable mainline error
     */
    (rSRQFIR, bit(16)) ? mem_port_th_1;

    /** SRQFIR[17]
     *  WDF mmio error
     */
    (rSRQFIR, bit(17)) ? mem_port_th_1;

    /** SRQFIR[18]
     *  WDF array UE on mainline operations (SUE put in mem)
     */
    (rSRQFIR, bit(18)) ? mem_port_th_1_UERE;

    /** SRQFIR[19]
     *  WDF mainline dataflow error (SUE not reliably put in mem)
     */
    (rSRQFIR, bit(19)) ? mem_port_th_1;

    /** SRQFIR[20]
     *  WDF scom register parity err, affecting mainline config
     */
    (rSRQFIR, bit(20)) ? mem_port_th_1;

    /** SRQFIR[21]
     *  WDF scom register parity err, affecting scom ops only
     */
    (rSRQFIR, bit(21)) ? mem_port_th_1;

    /** SRQFIR[22]
     *  WDF SCOM fsm parity error
     */
    (rSRQFIR, bit(22)) ? mem_port_th_1;

    /** SRQFIR[23]
     *  WDF write buffer array CE
     */
    (rSRQFIR, bit(23)) ? mem_port_th_32perDay;

    /** SRQFIR[24]
     *  NCF UE
     */
    (rSRQFIR, bit(24)) ? mem_port_th_1;

    /** SRQFIR[25]
     *  TBD
     */
    (rSRQFIR, bit(25)) ? defaultMaskedError;

    /** SRQFIR[26]
     *  NCF logic error
     */
    (rSRQFIR, bit(26)) ? mem_port_th_1;

    /** SRQFIR[27]
     *  NCF parity error
     */
    (rSRQFIR, bit(27)) ? mem_port_th_1;

    /** SRQFIR[28]
     *  NCF correctable error
     */
    (rSRQFIR, bit(28)) ? mem_port_th_32perDay;

    /** SRQFIR[29]
     *  Internal scom error
     */
    (rSRQFIR, bit(29)) ? defaultMaskedError;

    /** SRQFIR[30]
     *  Internal scom error copy
     */
    (rSRQFIR, bit(30)) ? defaultMaskedError;

};

################################################################################
# Explorer chip MCBISTFIR
################################################################################

rule rMCBISTFIR
{
  UNIT_CS:
    MCBISTFIR & ~MCBISTFIR_MASK & ~MCBISTFIR_ACT0 & ~MCBISTFIR_ACT1;
  RECOVERABLE:
    MCBISTFIR & ~MCBISTFIR_MASK & ~MCBISTFIR_ACT0 &  MCBISTFIR_ACT1;
  HOST_ATTN:
    MCBISTFIR & ~MCBISTFIR_MASK &  MCBISTFIR_ACT0 & ~MCBISTFIR_ACT1;
};

group gMCBISTFIR
    filter singlebit,
           cs_root_cause
{
    /** MCBISTFIR[0]
     *  Invalid maint address
     */
    (rMCBISTFIR, bit(0)) ? defaultMaskedError;

    /** MCBISTFIR[1]
     *  Command address timeout
     */
    (rMCBISTFIR, bit(1)) ? self_th_1;

    /** MCBISTFIR[2]
     *  Internal FSM error
     */
    (rMCBISTFIR, bit(2)) ? self_th_1;

    /** MCBISTFIR[3]
     *  MCBIST broadcast out of sync
     */
    (rMCBISTFIR, bit(3)) ? self_th_1;

    /** MCBISTFIR[4]
     *  MCBIST data error
     */
    (rMCBISTFIR, bit(4)) ? defaultMaskedError;

    /** MCBISTFIR[5]
     *  Hard NCE ETE attn
     */
    (rMCBISTFIR, bit(5)) ? defaultMaskedError;

    /** MCBISTFIR[6]
     *  Soft NCE ETE attn
     */
    (rMCBISTFIR, bit(6)) ? defaultMaskedError;

    /** MCBISTFIR[7]
     *  Int NCE ETE attn
     */
    (rMCBISTFIR, bit(7)) ? defaultMaskedError;

    /** MCBISTFIR[8]
     *  RCE ETE attn
     */
    (rMCBISTFIR, bit(8)) ? defaultMaskedError;

    /** MCBISTFIR[9]
     *  ICE (IMPE) ETE attn
     */
    (rMCBISTFIR, bit(9)) ? defaultMaskedError;

    /** MCBISTFIR[10]
     *  MCBIST program complete
     */
    (rMCBISTFIR, bit(10)) ? mcbist_program_complete;

    /** MCBISTFIR[11]
     *  MCBIST CCS subtest done
     */
    (rMCBISTFIR, bit(11)) ? defaultMaskedError;

    /** MCBISTFIR[12]
     *  WAT debug bus attn
     */
    (rMCBISTFIR, bit(12)) ? defaultMaskedError;

    /** MCBISTFIR[13]
     *  SCOM recoverable register parity error
     */
    (rMCBISTFIR, bit(13)) ? self_th_1;

    /** MCBISTFIR[14]
     *  SCOM fatal reg parity error
     */
    (rMCBISTFIR, bit(14)) ? self_th_1;

    /** MCBISTFIR[15]
     *  SCOM WAT and debug reg parity error
     */
    (rMCBISTFIR, bit(15)) ? defaultMaskedError;

    /** MCBISTFIR[16]
     *  Reserved
     */
    (rMCBISTFIR, bit(16)) ? defaultMaskedError;

    /** MCBISTFIR[17]
     *  Reserved
     */
    (rMCBISTFIR, bit(17)) ? defaultMaskedError;

    /** MCBISTFIR[18]
     *  Internal SCOM error
     */
    (rMCBISTFIR, bit(18)) ? defaultMaskedError;

    /** MCBISTFIR[19]
     *  Internal SCOM error clone
     */
    (rMCBISTFIR, bit(19)) ? defaultMaskedError;

};

################################################################################
# Explorer chip RDFFIR
################################################################################

rule rRDFFIR
{
  UNIT_CS:
    RDFFIR & ~RDFFIR_MASK & ~RDFFIR_ACT0 & ~RDFFIR_ACT1;
  RECOVERABLE:
    RDFFIR & ~RDFFIR_MASK & ~RDFFIR_ACT0 &  RDFFIR_ACT1;
  HOST_ATTN:
    RDFFIR & ~RDFFIR_MASK &  RDFFIR_ACT0 & ~RDFFIR_ACT1;
};

group gRDFFIR
    filter singlebit,
           cs_root_cause(14,15,17,35,37)
{
    /** RDFFIR[0]
     *  Mainline read MPE on rank 0
     */
    (rRDFFIR, bit(0)) ? verify_chip_mark_0;

    /** RDFFIR[1]
     *  Mainline read MPE on rank 1
     */
    (rRDFFIR, bit(1)) ? verify_chip_mark_1;

    /** RDFFIR[2]
     *  Mainline read MPE on rank 2
     */
    (rRDFFIR, bit(2)) ? verify_chip_mark_2;

    /** RDFFIR[3]
     *  Mainline read MPE on rank 3
     */
    (rRDFFIR, bit(3)) ? verify_chip_mark_3;

    /** RDFFIR[4]
     *  Mainline read MPE on rank 4
     */
    (rRDFFIR, bit(4)) ? verify_chip_mark_4;

    /** RDFFIR[5]
     *  Mainline read MPE on rank 5
     */
    (rRDFFIR, bit(5)) ? verify_chip_mark_5;

    /** RDFFIR[6]
     *  Mainline read MPE on rank 6
     */
    (rRDFFIR, bit(6)) ? verify_chip_mark_6;

    /** RDFFIR[7]
     *  Mainline read MPE on rank 7
     */
    (rRDFFIR, bit(7)) ? verify_chip_mark_7;

    /** RDFFIR[8]
     *  Mainline read NCE
     */
    (rRDFFIR, bit(8)) ? mainline_nce_tce_handling;

    /** RDFFIR[9]
     *  Mainline read TCE
     */
    (rRDFFIR, bit(9)) ? mainline_nce_tce_handling;

    /** RDFFIR[10]
     *  Mainline read SCE
     */
    (rRDFFIR, bit(10)) ? defaultMaskedError;

    /** RDFFIR[11]
     *  Mainline read MCE
     */
    (rRDFFIR, bit(11)) ? defaultMaskedError;

    /** RDFFIR[12]
     *  Mainline read SUE
     */
    (rRDFFIR, bit(12)) ? defaultMaskedError;

    /** RDFFIR[13]
     *  Mainline read AUE
     */
    (rRDFFIR, bit(13)) ? mainline_aue_iaue_handling;

    /** RDFFIR[14]
     *  Mainline read UE
     */
    (rRDFFIR, bit(14)) ? mainline_ue_handling_UERE;

    /** RDFFIR[15]
     *  Mainline read RCD
     */
    (rRDFFIR, bit(15)) ? rdf_rcd_parity_error_UERE;

    /** RDFFIR[16]
     *  Mainline read IAUE
     */
    (rRDFFIR, bit(16)) ? mainline_aue_iaue_handling;

    /** RDFFIR[17]
     *  Mainline read IUE
     */
    (rRDFFIR, bit(17)) ? mainline_iue_handling;

    /** RDFFIR[18]
     *  Mainline read IRCD
     */
    (rRDFFIR, bit(18)) ? defaultMaskedError;

    /** RDFFIR[19]
     *  Mainline read IMPE
     */
    (rRDFFIR, bit(19)) ? memory_impe_handling;

    /** RDFFIR[20:27]
     *  Maintenance MPE
     */
    (rRDFFIR, bit(20|21|22|23|24|25|26|27)) ? defaultMaskedError;

    /** RDFFIR[28]
     *  Maintenance NCE
     */
    (rRDFFIR, bit(28)) ? defaultMaskedError;

    /** RDFFIR[29]
     *  Maintenance TCE
     */
    (rRDFFIR, bit(29)) ? defaultMaskedError;

    /** RDFFIR[30]
     *  Maintenance SCE
     */
    (rRDFFIR, bit(30)) ? defaultMaskedError;

    /** RDFFIR[31]
     *  Maintenance MCE
     */
    (rRDFFIR, bit(31)) ? defaultMaskedError;

    /** RDFFIR[32]
     *  Maintenance SUE
     */
    (rRDFFIR, bit(32)) ? defaultMaskedError;

    /** RDFFIR[33]
     *  Maintenance AUE
     */
    (rRDFFIR, bit(33)) ? maintenance_aue_handling;

    /** RDFFIR[34]
     *  Maintenance UE
     */
    (rRDFFIR, bit(34)) ? defaultMaskedError;

    /** RDFFIR[35]
     *  Maintenance RCD
     */
    (rRDFFIR, bit(35)) ? rdf_rcd_parity_error_UERE;

    /** RDFFIR[36]
     *  Maintenance IAUE
     */
    (rRDFFIR, bit(36)) ? maintenance_iaue_handling;

    /** RDFFIR[37]
     *  Maintenance IUE
     */
    (rRDFFIR, bit(37)) ? maintenance_iue_handling;

    /** RDFFIR[38]
     *  Maintenance  IRCD
     */
    (rRDFFIR, bit(38)) ? defaultMaskedError;

    /** RDFFIR[39]
     *  Maintenance IMPE
     */
    (rRDFFIR, bit(39)) ? memory_impe_handling;

    /** RDFFIR[40]
     *  RDDATA valid error
     */
    (rRDFFIR, bit(40)) ? mem_port_th_32perDay;

    /** RDFFIR[41]
     *  SCOM status register parity error
     */
    (rRDFFIR, bit(41)) ? threshold_and_mask_mem_port;

    /** RDFFIR[42]
     *  SCOM recoverable register parity error
     */
    (rRDFFIR, bit(42)) ? mem_port_th_1;

    /** RDFFIR[43]
     *  SCOM unrecoverable register parity error
     */
    (rRDFFIR, bit(43)) ? mem_port_th_1;

    /** RDFFIR[44]
     *  ECC corrector internal parity error
     */
    (rRDFFIR, bit(44)) ? mem_port_th_1;

    /** RDFFIR[45]
     *  Rd Buff ECC CHK Cor CE DW0 Detected
     */
    (rRDFFIR, bit(45)) ? mem_port_th_32perDay;

    /** RDFFIR[46]
     *  Rd Buff ECC CHK Cor CE DW1 Detected
     */
    (rRDFFIR, bit(46)) ? mem_port_th_32perDay;

    /** RDFFIR[47]
     *  Rd Buff ECC CHK Cor UE DW0 Detected
     */
    (rRDFFIR, bit(47)) ? mem_port_th_1;

    /** RDFFIR[48]
     *  Rd Buff ECC CHK Cor UE DW1 Detected
     */
    (rRDFFIR, bit(48)) ? mem_port_th_1;

    /** RDFFIR[49:59]
     *  Reserved
     */
    (rRDFFIR, bit(49|50|51|52|53|54|55|56|57|58|59)) ? defaultMaskedError;

    /** RDFFIR[60]
     *  SCOM register parity error for debug/wat control
     */
    (rRDFFIR, bit(60)) ? defaultMaskedError;

    /** RDFFIR[61]
     *  Reserved
     */
    (rRDFFIR, bit(61)) ? defaultMaskedError;

    /** RDFFIR[62]
     *  Internal SCOM error
     */
    (rRDFFIR, bit(62)) ? defaultMaskedError;

    /** RDFFIR[63]
     *  Internal SCOM error copy
     */
    (rRDFFIR, bit(63)) ? defaultMaskedError;

};

################################################################################
# Explorer chip TLXFIR
################################################################################

rule rTLXFIR
{
  UNIT_CS:
    TLXFIR & ~TLXFIR_MASK & ~TLXFIR_ACT0 & ~TLXFIR_ACT1;
  RECOVERABLE:
    TLXFIR & ~TLXFIR_MASK & ~TLXFIR_ACT0 &  TLXFIR_ACT1;
  HOST_ATTN:
    TLXFIR & ~TLXFIR_MASK &  TLXFIR_ACT0 & ~TLXFIR_ACT1;
};

group gTLXFIR
    filter singlebit,
           cs_root_cause
{
    /** TLXFIR[0]
     *  Info reg parity error
     */
    (rTLXFIR, bit(0)) ? threshold_and_mask_self;

    /** TLXFIR[1]
     *  Ctrl reg parity error
     */
    (rTLXFIR, bit(1)) ? self_th_1;

    /** TLXFIR[2]
     *  TLX VC0 return credit counter overflow
     */
    (rTLXFIR, bit(2)) ? omi_bus_th_1;

    /** TLXFIR[3]
     *  TLX VC1 return credit counter overflow
     */
    (rTLXFIR, bit(3)) ? omi_bus_th_1;

    /** TLXFIR[4]
     *  TLX dcp0 return credit counter overflow
     */
    (rTLXFIR, bit(4)) ? omi_bus_th_1;

    /** TLXFIR[5]
     *  TLX dcp1 return credit counter overflow
     */
    (rTLXFIR, bit(5)) ? omi_bus_th_1;

    /** TLXFIR[6]
     *  TLX credit management block error
     */
    (rTLXFIR, bit(6)) ? self_th_1;

    /** TLXFIR[7]
     *  TLX credit management block parity error
     */
    (rTLXFIR, bit(7)) ? self_th_1;

    /** TLXFIR[8]
     *  TLXT fatal parity error
     */
    (rTLXFIR, bit(8)) ? self_th_1;

    /** TLXFIR[9]
     *  TLXT recoverable error
     */
    (rTLXFIR, bit(9)) ? analyzeTLXERR1;

    /** TLXFIR[10]
     *  TLXT configuration error
     */
    (rTLXFIR, bit(10)) ? level2_M_self_L_th_1;

    /** TLXFIR[11]
     *  TLXT informational parity error
     */
    (rTLXFIR, bit(11)) ? self_th_1;

    /** TLXFIR[12]
     *  TLXT hard error
     */
    (rTLXFIR, bit(12)) ? self_th_1;

    /** TLXFIR[13:15]
     *  Reserved
     */
    (rTLXFIR, bit(13|14|15)) ? defaultMaskedError;

    /** TLXFIR[16]
     *  Corrupted pad mem pattern
     */
    (rTLXFIR, bit(16)) ? defaultMaskedError;

    /** TLXFIR[17]
     *  Downstream OC parity error
     */
    (rTLXFIR, bit(17)) ? defaultMaskedError;

    /** TLXFIR[18]
     *  OC malformed
     */
    (rTLXFIR, bit(18)) ? omi_bus_th_1;

    /** TLXFIR[19]
     *  OC protocol error
     */
    (rTLXFIR, bit(19)) ? omi_th_1;

    /** TLXFIR[20]
     *  Address translate error
     */
    (rTLXFIR, bit(20)) ? self_th_1;

    /** TLXFIR[21]
     *  Metadata unc or data parity error
     */
    (rTLXFIR, bit(21)) ? self_th_1;

    /** TLXFIR[22]
     *  OC unsupported group 2
     */
    (rTLXFIR, bit(22)) ? omi_bus_th_1;

    /** TLXFIR[23]
     *  OC unsupported group 1
     */
    (rTLXFIR, bit(23)) ? omi_bus_th_1;

    /** TLXFIR[24]
     *  Bit flip control error
     */
    (rTLXFIR, bit(24)) ? self_th_1;

    /** TLXFIR[25]
     *  Control HW error
     */
    (rTLXFIR, bit(25)) ? self_th_1;

    /** TLXFIR[26]
     *  ECC corrected and others
     */
    (rTLXFIR, bit(26)) ? self_th_32perDay;

    /** TLXFIR[27]
     *  Trace stop
     */
    (rTLXFIR, bit(27)) ? defaultMaskedError;

    /** TLXFIR[28]
     *  Internal SCOM error
     */
    (rTLXFIR, bit(28)) ? defaultMaskedError;

    /** TLXFIR[29]
     *  Internal SCOM error clone
     */
    (rTLXFIR, bit(29)) ? defaultMaskedError;

};

rule rTLX_ERR1_REPORT
{
  RECOVERABLE:
    TLX_ERR1_REPORT & ~TLX_ERR1_REPORT_MASK;
};

group gTLX_ERR1_REPORT
    filter singlebit,
           cs_root_cause
{
    /** TLX_ERR1_REPORT[37]
     *  TLXT FIFO CE
     */
    (rTLXFIR, bit(37)) ? self_th_32perDay;

    /** TLX_ERR1_REPORT[39]
     *  Unexpected Interrupt Response
     */
    (rTLXFIR, bit(39)) ? parent_proc_th_32perDay;

    /** TLX_ERR1_REPORT[40]
     *  BDI Poisoned
     */
    (rTLXFIR, bit(40)) ? self_th_1;

    /** TLX_ERR1_REPORT[41]
     *  TLXT Metadata UE
     */
    (rTLXFIR, bit(41)) ? self_th_1;
};

################################################################################
# Explorer chip OMIDLFIR
################################################################################

rule rOMIDLFIR
{
  UNIT_CS:
    OMIDLFIR & ~OMIDLFIR_MASK & ~OMIDLFIR_ACT0 & ~OMIDLFIR_ACT1;
  RECOVERABLE:
    OMIDLFIR & ~OMIDLFIR_MASK & ~OMIDLFIR_ACT0 &  OMIDLFIR_ACT1;
  HOST_ATTN:
    OMIDLFIR & ~OMIDLFIR_MASK &  OMIDLFIR_ACT0 & ~OMIDLFIR_ACT1;
};

group gOMIDLFIR
    filter singlebit,
           cs_root_cause
{
    /** OMIDLFIR[0]
     *  OMI-DL0 fatal error
     */
    (rOMIDLFIR, bit(0)) ? dl_fatal_error;

    /** OMIDLFIR[1]
     *  OMI-DL0 UE on data flit
     */
    (rOMIDLFIR, bit(1)) ? self_th_1;

    /** OMIDLFIR[2]
     *  OMI-DL0 CE on TL flit
     */
    (rOMIDLFIR, bit(2)) ? self_th_32perDay;

    /** OMIDLFIR[3]
     *  OMI-DL0 detected a CRC error
     */
    (rOMIDLFIR, bit(3)) ? defaultMaskedError;

    /** OMIDLFIR[4]
     *  OMI-DL0 received a nack
     */
    (rOMIDLFIR, bit(4)) ? defaultMaskedError;

    /** OMIDLFIR[5]
     *  OMI-DL0 running in degraded mode
     */
    (rOMIDLFIR, bit(5)) ? omi_bus_th_1;

    /** OMIDLFIR[6]
     *  OMI-DL0 parity error detection on a lane
     */
    (rOMIDLFIR, bit(6)) ? defaultMaskedError;

    /** OMIDLFIR[7]
     *  OMI-DL0 retrained due to no forward progress
     */
    (rOMIDLFIR, bit(7)) ? omi_bus_th_32perDay;

    /** OMIDLFIR[8]
     *  OMI-DL0 remote side initiated a retrain
     */
    (rOMIDLFIR, bit(8)) ? defaultMaskedError;

    /** OMIDLFIR[9]
     *  OMI-DL0 retrain due to internal error or software initiated
     */
    (rOMIDLFIR, bit(9)) ? omi_bus_th_32perDay;

    /** OMIDLFIR[10]
     *  OMI-DL0 threshold reached
     */
    (rOMIDLFIR, bit(10)) ? omi_bus_th_32perDay;

    /** OMIDLFIR[11]
     *  OMI-DL0 trained
     */
    (rOMIDLFIR, bit(11)) ? defaultMaskedError;

    /** OMIDLFIR[12]
     *  OMI-DL0 endpoint error bit 0
     */
    (rOMIDLFIR, bit(12)) ? defaultMaskedError;

    /** OMIDLFIR[13]
     *  OMI-DL0 endpoint error bit 1
     */
    (rOMIDLFIR, bit(13)) ? defaultMaskedError;

    /** OMIDLFIR[14]
     *  OMI-DL0 endpoint error bit 2
     */
    (rOMIDLFIR, bit(14)) ? defaultMaskedError;

    /** OMIDLFIR[15]
     *  OMI-DL0 endpoint error bit 3
     */
    (rOMIDLFIR, bit(15)) ? defaultMaskedError;

    /** OMIDLFIR[16]
     *  OMI-DL0 endpoint error bit 4
     */
    (rOMIDLFIR, bit(16)) ? defaultMaskedError;

    /** OMIDLFIR[17]
     *  OMI-DL0 endpoint error bit 5
     */
    (rOMIDLFIR, bit(17)) ? defaultMaskedError;

    /** OMIDLFIR[18]
     *  OMI-DL0 endpoint error bit 6
     */
    (rOMIDLFIR, bit(18)) ? defaultMaskedError;

    /** OMIDLFIR[19]
     *  OMI-DL0 endpoint error bit 7
     */
    (rOMIDLFIR, bit(19)) ? defaultMaskedError;

    /** OMIDLFIR[20:39]
     *  OMI-DL1 reserved
     */
    (rOMIDLFIR, bit(20|21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39)) ? defaultMaskedError;

    /** OMIDLFIR[40:59]
     *  OMI-DL2 reserved
     */
    (rOMIDLFIR, bit(40|41|42|43|44|45|46|47|48|49|50|51|52|53|54|55|56|57|58|59)) ? defaultMaskedError;

    /** OMIDLFIR[60]
     *  Performance monitor wrapped
     */
    (rOMIDLFIR, bit(60)) ? defaultMaskedError;

    /** OMIDLFIR[61]
     *  reserved
     */
    (rOMIDLFIR, bit(61)) ? defaultMaskedError;

    /** OMIDLFIR[62]
     *  LFIR internal parity error
     */
    (rOMIDLFIR, bit(62)) ? defaultMaskedError;

    /** OMIDLFIR[63]
     *  SCOM Satellite Error
     */
    (rOMIDLFIR, bit(63)) ? defaultMaskedError;

};

 ##############################################################################
 #                                                                            #
 #    #                                  ###                                  #
 #   # #    ##  ##### ###  ###  #   #   #   # #     #    ###   ###  ###  ###  #
 #  #   #  #  #   #    #  #   # ##  #   #     #    # #  #     #     #   #     #
 # ####### #      #    #  #   # # # #   #     #   #####  ###   ###  ##   ###  #
 # #     # #  #   #    #  #   # #  ##   #   # #   #   #     #     # #       # #
 # #     #  ##    #   ###  ###  #   #    ###  ### #   #  ###   ###  ###  ###  #
 #                                                                            #
 ##############################################################################

# Include the actions defined for this target
.include "explorer_ocmb_actions.rule";