# IBM_PROLOG_BEGIN_TAG
# This is an automatically generated prolog.
#
# $Source: src/usr/diag/prdf/common/plat/cumulus/cumulus_mc.rule $
#
# OpenPOWER HostBoot Project
#
# Contributors Listed Below - COPYRIGHT 2016,2018
# [+] International Business Machines Corp.
#
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
# implied. See the License for the specific language governing
# permissions and limitations under the License.
#
# IBM_PROLOG_END_TAG

chip cumulus_mc
{
    name        "CUMULUS MC target";
    targettype  TYPE_MC;
    sigoff      0x9200;
    dump        DUMP_CONTENT_HW;
    scomlen     64;

# Import signatures
.include "prdfLaneRepairExtraSig.H";

 #############################################################################
 #                                                                           #
 #  ######                                                                   #
 #  #     #  ######   ####     ###    ####    #####  ######  #####    ####   #
 #  #     #  #       #    #     #    #          #    #       #    #  #       #
 #  ######   #####   #          #     ####      #    #####   #    #   ####   #
 #  #   #    #       #  ###     #         #     #    #       #####        #  #
 #  #    #   #       #    #     #    #    #     #    #       #   #   #    #  #
 #  #     #  ######   ####     ###    ####      #    ######  #    #   ####   #
 #                                                                           #
 #############################################################################

    ############################################################################
    # MC Chiplet FIR
    ############################################################################

    register MC_CHIPLET_CS_FIR
    {
        name        "MC Chiplet Checkstop FIR";
        scomaddr    0x07040000;
        capture     group default;
    };

    register MC_CHIPLET_RE_FIR
    {
        name        "MC Chiplet Recoverable FIR";
        scomaddr    0x07040001;
        capture     group default;
    };

    register MC_CHIPLET_FIR_MASK
    {
        name        "MC Chiplet FIR MASK";
        scomaddr    0x07040002;
        capture     group default;
    };

    ############################################################################
    # MC Chiplet Unit Checkstop FIR
    ############################################################################

    register MC_CHIPLET_UCS_FIR
    {
        name        "MC Chiplet Unit Checkstop FIR";
        scomaddr    0x07040018;
        capture     group default;
    };

    register MC_CHIPLET_UCS_FIR_MASK
    {
        name        "MC Chiplet Unit Checkstop FIR MASK";
        scomaddr    0x07040019;
        capture     group default;
    };

    ############################################################################
    # MC Chiplet Host Attention FIR
    ############################################################################

    register MC_CHIPLET_HA_FIR
    {
        name        "MC Chiplet Host Attention FIR";
        scomaddr    0x07040009;
        capture     group default;
    };

    register MC_CHIPLET_HA_FIR_MASK
    {
        name        "MC Chiplet Host Attention FIR MASK";
        scomaddr    0x0704001a;
        capture     group default;
    };

    ############################################################################
    # P9 chip MC_LFIR
    ############################################################################

    register MC_LFIR
    {
        name        "P9 chip MC_LFIR";
        scomaddr    0x0704000a;
        reset       (&, 0x0704000b);
        mask        (|, 0x0704000f);
        capture     group default;
    };

    register MC_LFIR_MASK
    {
        name        "P9 chip MC_LFIR MASK";
        scomaddr    0x0704000d;
        capture     group default;
    };

    register MC_LFIR_ACT0
    {
        name        "P9 chip MC_LFIR ACT0";
        scomaddr    0x07040010;
        capture     group default;
        capture     req nonzero("MC_LFIR");
    };

    register MC_LFIR_ACT1
    {
        name        "P9 chip MC_LFIR ACT1";
        scomaddr    0x07040011;
        capture     group default;
        capture     req nonzero("MC_LFIR");
    };

    ############################################################################
    # P9 MC target IOMCFIR
    ############################################################################

    register IOMCFIR
    {
        name        "P9 MC target IOMCFIR";
        scomaddr    0x07011000;
        reset       (&, 0x07011001);
        mask        (|, 0x07011005);
        capture     group default;
    };

    register IOMCFIR_MASK
    {
        name        "P9 MC target IOMCFIR MASK";
        scomaddr    0x07011003;
        capture     group default;
    };

    register IOMCFIR_ACT0
    {
        name        "P9 MC target IOMCFIR ACT0";
        scomaddr    0x07011006;
        capture     group default;
        capture     req nonzero("IOMCFIR");
    };

    register IOMCFIR_ACT1
    {
        name        "P9 MC target IOMCFIR ACT1";
        scomaddr    0x07011007;
        capture     group default;
        capture     req nonzero("IOMCFIR");
    };

    ############################################################################
    # P9 MC target MCPPEFIR
    ############################################################################

    register MCPPEFIR
    {
        name        "P9 MC target MCPPEFIR";
        scomaddr    0x07011440;
        reset       (&, 0x07011441);
        mask        (|, 0x07011445);
        capture     group default;
    };

    register MCPPEFIR_MASK
    {
        name        "P9 MC target MCPPEFIR MASK";
        scomaddr    0x07011443;
        capture     group default;
    };

    register MCPPEFIR_ACT0
    {
        name        "P9 MC target MCPPEFIR ACT0";
        scomaddr    0x07011446;
        capture     group default;
        capture     req nonzero("MCPPEFIR");
    };

    register MCPPEFIR_ACT1
    {
        name        "P9 MC target MCPPEFIR ACT1";
        scomaddr    0x07011447;
        capture     group default;
        capture     req nonzero("MCPPEFIR");
    };

    ############################################################################
    # P9 MC target MCBISTFIR
    ############################################################################

    register MCBISTFIR
    {
        name        "P9 MC target MCBISTFIR";
        scomaddr    0x07012300;
        reset       (&, 0x07012301);
        mask        (|, 0x07012305);
        capture     group default;
    };

    register MCBISTFIR_MASK
    {
        name        "P9 MC target MCBISTFIR MASK";
        scomaddr    0x07012303;
        capture     group default;
    };

    register MCBISTFIR_ACT0
    {
        name        "P9 MC target MCBISTFIR ACT0";
        scomaddr    0x07012306;
        capture     group default;
        capture     req nonzero("MCBISTFIR");
    };

    register MCBISTFIR_ACT1
    {
        name        "P9 MC target MCBISTFIR ACT1";
        scomaddr    0x07012307;
        capture     group default;
        capture     req nonzero("MCBISTFIR");
    };

# Include registers not defined by the xml
.include "cumulus_mc_regs.rule";

};

 ##############################################################################
 #                                                                            #
 # ####                                 #                                     #
 # #   # #   # #    #####  ###      #  # #    ##  ##### ###  ###  #   #  ###  #
 # #   # #   # #    #     #        #  #   #  #  #   #    #  #   # ##  # #     #
 # ####  #   # #    ####   ###    #  ####### #      #    #  #   # # # #  ###  #
 # #  #  #   # #    #         #  #   #     # #  #   #    #  #   # #  ##     # #
 # #   #  ###  #### #####  ###  #    #     #  ##    #   ###  ###  #   #  ###  #
 #                                                                            #
 ##############################################################################

################################################################################
# MC Chiplet FIR
################################################################################

rule rMC_CHIPLET_FIR
{
  CHECK_STOP:
     MC_CHIPLET_CS_FIR       & ~MC_CHIPLET_FIR_MASK & `1fffffffffffffff`;
  RECOVERABLE:
    (MC_CHIPLET_RE_FIR >> 2) & ~MC_CHIPLET_FIR_MASK & `1fffffffffffffff`;
};

group gMC_CHIPLET_FIR attntype CHECK_STOP, RECOVERABLE
    filter singlebit
{
    /** MC_CHIPLET_FIR[3]
     *  Attention from MC_LFIR
     */
    (rMC_CHIPLET_FIR, bit(3)) ? analyzeMC_LFIR;

    /** MC_CHIPLET_FIR[4]
     *  Attention from CHIFIR 0
     */
    (rMC_CHIPLET_FIR, bit(4)) ? analyzeConnectedDMI0;

    /** MC_CHIPLET_FIR[6]
     *  Attention from CHIFIR 1
     */
    (rMC_CHIPLET_FIR, bit(6)) ? analyzeConnectedDMI1;

    /** MC_CHIPLET_FIR[8]
     *  Attention from CHIFIR 2
     */
    (rMC_CHIPLET_FIR, bit(8)) ? analyzeConnectedDMI2;

    /** MC_CHIPLET_FIR[10]
     *  Attention from CHIFIR 3
     */
    (rMC_CHIPLET_FIR, bit(10)) ? analyzeConnectedDMI3;

    /** MC_CHIPLET_FIR[12]
     *  Attention from MCBISTFIR
     */
    (rMC_CHIPLET_FIR, bit(12)) ? analyzeMCBISTFIR;

    /** MC_CHIPLET_FIR[13]
     *  Attention from IOMCFIR
     */
    (rMC_CHIPLET_FIR, bit(13)) ? analyzeIOMCFIR;

    /** MC_CHIPLET_FIR[14]
     *  Attention from MCPPEFIR
     */
    (rMC_CHIPLET_FIR, bit(14)) ? analyzeMCPPEFIR;

};

################################################################################
# MC Chiplet Unit Checkstop FIR
################################################################################

rule rMC_CHIPLET_UCS_FIR
{
  UNIT_CS:
    MC_CHIPLET_UCS_FIR & ~(MC_CHIPLET_UCS_FIR_MASK >> 1) & `7fffffffffffffff`;
};

# The IOMCFIR has been prioritized over all the other bits in this FIR. See the
# notes in prdfMemUtils.C for the reasons why.
group gMC_CHIPLET_UCS_FIR attntype UNIT_CS
    filter priority(10)
{
    /** MC_CHIPLET_UCS_FIR[1]
     *  Attention from CHIFIR 0
     */
    (rMC_CHIPLET_UCS_FIR, bit(1)) ? analyzeConnectedDMI0;

    /** MC_CHIPLET_UCS_FIR[3]
     *  Attention from CHIFIR 1
     */
    (rMC_CHIPLET_UCS_FIR, bit(3)) ? analyzeConnectedDMI1;

    /** MC_CHIPLET_UCS_FIR[5]
     *  Attention from CHIFIR 2
     */
    (rMC_CHIPLET_UCS_FIR, bit(5)) ? analyzeConnectedDMI2;

    /** MC_CHIPLET_UCS_FIR[7]
     *  Attention from CHIFIR 3
     */
    (rMC_CHIPLET_UCS_FIR, bit(7)) ? analyzeConnectedDMI3;

    /** MC_CHIPLET_UCS_FIR[8]
     *  Attention from MCPPEFIR
     */
    (rMC_CHIPLET_UCS_FIR, bit(8)) ? analyzeMCPPEFIR;

    /** MC_CHIPLET_UCS_FIR[9]
     *  Attention from MCBISTFIR
     */
    (rMC_CHIPLET_UCS_FIR, bit(9)) ? analyzeMCBISTFIR;

    /** MC_CHIPLET_UCS_FIR[10]
     *  Attention from IOMCFIR
     */
    (rMC_CHIPLET_UCS_FIR, bit(10)) ? analyzeIOMCFIR;

};

################################################################################
# MC Chiplet Host Attention FIR
################################################################################

rule rMC_CHIPLET_HA_FIR
{
  HOST_ATTN:
    MC_CHIPLET_HA_FIR & ~(MC_CHIPLET_HA_FIR_MASK >> 1) & `7fffffffffffffff`;
};

group gMC_CHIPLET_HA_FIR attntype HOST_ATTN
    filter singlebit
{
    /** MC_CHIPLET_HA_FIR[1]
     *  Attention from CHIFIR 0
     */
    (rMC_CHIPLET_HA_FIR, bit(1)) ? analyzeConnectedDMI0;

    /** MC_CHIPLET_HA_FIR[3]
     *  Attention from CHIFIR 1
     */
    (rMC_CHIPLET_HA_FIR, bit(3)) ? analyzeConnectedDMI1;

    /** MC_CHIPLET_HA_FIR[5]
     *  Attention from CHIFIR 2
     */
    (rMC_CHIPLET_HA_FIR, bit(5)) ? analyzeConnectedDMI2;

    /** MC_CHIPLET_HA_FIR[7]
     *  Attention from CHIFIR 3
     */
    (rMC_CHIPLET_HA_FIR, bit(7)) ? analyzeConnectedDMI3;

    /** MC_CHIPLET_HA_FIR[9]
     *  Attention from MCBISTFIR
     */
    (rMC_CHIPLET_HA_FIR, bit(9)) ? analyzeMCBISTFIR;

};

################################################################################
# P9 chip MC_LFIR
################################################################################

rule rMC_LFIR
{
  CHECK_STOP:
    MC_LFIR & ~MC_LFIR_MASK & ~MC_LFIR_ACT0 & ~MC_LFIR_ACT1;
  RECOVERABLE:
    MC_LFIR & ~MC_LFIR_MASK & ~MC_LFIR_ACT0 &  MC_LFIR_ACT1;
};

group gMC_LFIR
    filter singlebit,
           cs_root_cause
{
    /** MC_LFIR[0]
     *  CFIR internal parity error
     */
    (rMC_LFIR, bit(0)) ? self_th_32perDay;

    /** MC_LFIR[1]
     *  Chiplet Control Reg: PCB Access Error
     */
    (rMC_LFIR, bit(1)) ? self_th_32perDay;

    /** MC_LFIR[2]
     *  Clock Controller: PCB Access Error
     */
    (rMC_LFIR, bit(2)) ? self_th_32perDay;

    /** MC_LFIR[3]
     *  Clock Controller: Summarized Error
     */
    (rMC_LFIR, bit(3)) ? self_th_32perDay;

    /** MC_LFIR[4]
     *  PSCOM Logic: PCB Access Error
     */
    (rMC_LFIR, bit(4)) ? defaultMaskedError;

    /** MC_LFIR[5]
     *  PSCOM Logic: Summarized internal errors
     */
    (rMC_LFIR, bit(5)) ? defaultMaskedError;

    /** MC_LFIR[6]
     *  Therm Logic: Summarized internal errors
     */
    (rMC_LFIR, bit(6)) ? defaultMaskedError;

    /** MC_LFIR[7]
     *  Therm Logic: PCB Access Error
     */
    (rMC_LFIR, bit(7)) ? defaultMaskedError;

    /** MC_LFIR[8]
     *  Therm Logic: Temperature critical trip
     */
    (rMC_LFIR, bit(8)) ? defaultMaskedError;

    /** MC_LFIR[9]
     *  Therm Logic: Temperature fatal trip
     */
    (rMC_LFIR, bit(9)) ? defaultMaskedError;

    /** MC_LFIR[10]
     *  UNUSED in P9
     */
    (rMC_LFIR, bit(10)) ? defaultMaskedError;

    /** MC_LFIR[11]
     *  Debug Logic: Scom Satellite Error
     */
    (rMC_LFIR, bit(11)) ? defaultMaskedError;

    /** MC_LFIR[12]
     *  Scom Satellite Error - Trace0
     */
    (rMC_LFIR, bit(12)) ? defaultMaskedError;

    /** MC_LFIR[13]
     *  Scom Satellite Error - Trace0
     */
    (rMC_LFIR, bit(13)) ? defaultMaskedError;

    /** MC_LFIR[14]
     *  Scom Satellite Error - Trace1
     */
    (rMC_LFIR, bit(14)) ? defaultMaskedError;

    /** MC_LFIR[15]
     *  Scom Satellite Error - Trace1
     */
    (rMC_LFIR, bit(15)) ? defaultMaskedError;

    /** MC_LFIR[16:40]
     *  spare
     */
    (rMC_LFIR, bit(16|17|18|19|20|21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39|40)) ? defaultMaskedError;

    /** MC_LFIR[41]
     *  Malfunction Alert or Local Checkstop
     */
    (rMC_LFIR, bit(41)) ? defaultMaskedError;

};

################################################################################
# P9 MC target IOMCFIR
################################################################################

rule rIOMCFIR
{
  CHECK_STOP:
    IOMCFIR & ~IOMCFIR_MASK & ~IOMCFIR_ACT0 & ~IOMCFIR_ACT1;
  RECOVERABLE:
    IOMCFIR & ~IOMCFIR_MASK & ~IOMCFIR_ACT0 &  IOMCFIR_ACT1;
  HOST_ATTN:
    IOMCFIR & ~IOMCFIR_MASK &  IOMCFIR_ACT0 & ~IOMCFIR_ACT1;
  UNIT_CS:
    IOMCFIR & ~IOMCFIR_MASK &  IOMCFIR_ACT0 &  IOMCFIR_ACT1;
};

group gIOMCFIR
    filter singlebit,
           cs_root_cause(12,20,28,36)
{
    /** IOMCFIR[0]
     *  RX_INVALID_STATE_OR_PARITY_ERROR
     */
    (rIOMCFIR, bit(0)) ? self_th_1;

    /** IOMCFIR[1]
     *  TX_INVALID_STATE_OR_PARITY_ERROR
     */
    (rIOMCFIR, bit(1)) ? self_th_1;

    /** IOMCFIR[2]
     *  GCR_HANG_ERROR
     */
    (rIOMCFIR, bit(2)) ? self_th_1;

    /** IOMCFIR[3:7]
     *  spare
     */
    (rIOMCFIR, bit(3|4|5|6|7)) ? defaultMaskedError;

    /** IOMCFIR[8]
     *  RX BUS 0 Training Error
     */
    (rIOMCFIR, bit(8)) ? defaultMaskedError;

    /** IOMCFIR[9]
     *  RX BUS 0 Spare Deployed
     */
    (rIOMCFIR, bit(9)) ? spareDeployed_dmi0;

    /** IOMCFIR[10]
     *  RX BUS 0 Max Spares Exceeded
     */
    (rIOMCFIR, bit(10)) ? maxSparesExceeded_dmi0;

    /** IOMCFIR[11]
     *  RX BUS 0 Recal or dynamic repair error
     */
    (rIOMCFIR, bit(11)) ? calloutBusInterface_dmi0_th_1;

    /** IOMCFIR[12]
     *  RX BUS 0 Too Many Bus Errors
     */
    (rIOMCFIR, bit(12)) ? tooManyBusErrors_dmi0_UERE;

    /** IOMCFIR[13:15]
     *  spare
     */
    (rIOMCFIR, bit(13|14|15)) ? defaultMaskedError;

    /** IOMCFIR[16]
     *  RX BUS 1 Training Error
     */
    (rIOMCFIR, bit(16)) ? defaultMaskedError;

    /** IOMCFIR[17]
     *  RX BUS 1 Spare Deployed
     */
    (rIOMCFIR, bit(17)) ? spareDeployed_dmi1;

    /** IOMCFIR[18]
     *  RX BUS 1 Max Spares Exceeded
     */
    (rIOMCFIR, bit(18)) ? maxSparesExceeded_dmi1;

    /** IOMCFIR[19]
     *  RX BUS 1 Recal or dynamic repair error
     */
    (rIOMCFIR, bit(19)) ? calloutBusInterface_dmi1_th_1;

    /** IOMCFIR[20]
     *  RX BUS 1 Too Many Bus Errors
     */
    (rIOMCFIR, bit(20)) ? tooManyBusErrors_dmi1_UERE;

    /** IOMCFIR[21:23]
     *  spare
     */
    (rIOMCFIR, bit(21|22|23)) ? defaultMaskedError;

    /** IOMCFIR[24]
     *  RX BUS 2 Training Error
     */
    (rIOMCFIR, bit(24)) ? defaultMaskedError;

    /** IOMCFIR[25]
     *  RX BUS 2 Spare Deployed
     */
    (rIOMCFIR, bit(25)) ? spareDeployed_dmi2;

    /** IOMCFIR[26]
     *  RX BUS 2 Max Spares Exceeded
     */
    (rIOMCFIR, bit(26)) ? maxSparesExceeded_dmi2;

    /** IOMCFIR[27]
     *  RX BUS 2 Recal or dynamic repair error
     */
    (rIOMCFIR, bit(27)) ? calloutBusInterface_dmi2_th_1;

    /** IOMCFIR[28]
     *  RX BUS 2 Too Many Bus Errors
     */
    (rIOMCFIR, bit(28)) ? tooManyBusErrors_dmi2_UERE;

    /** IOMCFIR[29:31]
     *  spare
     */
    (rIOMCFIR, bit(29|30|31)) ? defaultMaskedError;

    /** IOMCFIR[32]
     *  RX BUS 3 Training Error
     */
    (rIOMCFIR, bit(32)) ? defaultMaskedError;

    /** IOMCFIR[33]
     *  RX BUS 3 Spare Deployed
     */
    (rIOMCFIR, bit(33)) ? spareDeployed_dmi3;

    /** IOMCFIR[34]
     *  RX BUS 3 Max Spares Exceeded
     */
    (rIOMCFIR, bit(34)) ? maxSparesExceeded_dmi3;

    /** IOMCFIR[35]
     *  RX BUS 3 Recal or dynamic repair error
     */
    (rIOMCFIR, bit(35)) ? calloutBusInterface_dmi3_th_1;

    /** IOMCFIR[36]
     *  RX BUS 3 Too Many Bus Errors
     */
    (rIOMCFIR, bit(36)) ? tooManyBusErrors_dmi3_UERE;

    /** IOMCFIR[37:39]
     *  spare
     */
    (rIOMCFIR, bit(37|38|39)) ? defaultMaskedError;

    /** IOMCFIR[40:47]
     *  reserved
     */
    (rIOMCFIR, bit(40|41|42|43|44|45|46|47)) ? defaultMaskedError;

    /** IOMCFIR[48]
     *  SCOM error
     */
    (rIOMCFIR, bit(48)) ? defaultMaskedError;

    /** IOMCFIR[49]
     *  SCOM error clone
     */
    (rIOMCFIR, bit(49)) ? defaultMaskedError;

};

################################################################################
# P9 MC target MCPPEFIR
################################################################################

rule rMCPPEFIR
{
  CHECK_STOP:
    MCPPEFIR & ~MCPPEFIR_MASK & ~MCPPEFIR_ACT0 & ~MCPPEFIR_ACT1;
  RECOVERABLE:
    MCPPEFIR & ~MCPPEFIR_MASK & ~MCPPEFIR_ACT0 &  MCPPEFIR_ACT1;
  HOST_ATTN:
    MCPPEFIR & ~MCPPEFIR_MASK &  MCPPEFIR_ACT0 & ~MCPPEFIR_ACT1;
  UNIT_CS:
    MCPPEFIR & ~MCPPEFIR_MASK &  MCPPEFIR_ACT0 &  MCPPEFIR_ACT1;
};

group gMCPPEFIR
    filter singlebit,
           cs_root_cause
{
    /** MCPPEFIR[0]
     *  PPE general error.
     */
    (rMCPPEFIR, bit(0)) ? defaultMaskedError;

    /** MCPPEFIR[1]
     *  PPE general error.
     */
    (rMCPPEFIR, bit(1)) ? defaultMaskedError;

    /** MCPPEFIR[2]
     *  PPE general error.
     */
    (rMCPPEFIR, bit(2)) ? defaultMaskedError;

    /** MCPPEFIR[3]
     *  PPE general error.
     */
    (rMCPPEFIR, bit(3)) ? defaultMaskedError;

    /** MCPPEFIR[4]
     *  PPE halted.
     */
    (rMCPPEFIR, bit(4)) ? defaultMaskedError;

    /** MCPPEFIR[5]
     *  PPE watchdog timer timed out
     */
    (rMCPPEFIR, bit(5)) ? defaultMaskedError;

    /** MCPPEFIR[6]
     *  MMIO data in error.
     */
    (rMCPPEFIR, bit(6)) ? defaultMaskedError;

    /** MCPPEFIR[7]
     *  Arb missed scrub tick.
     */
    (rMCPPEFIR, bit(7)) ? defaultMaskedError;

    /** MCPPEFIR[8]
     *  Arb ary ue error.
     */
    (rMCPPEFIR, bit(8)) ? defaultMaskedError;

    /** MCPPEFIR[9]
     *  Arb ary ce error.
     */
    (rMCPPEFIR, bit(9)) ? defaultMaskedError;

    /** MCPPEFIR[10]
     *  spare
     */
    (rMCPPEFIR, bit(10)) ? defaultMaskedError;

    /** MCPPEFIR[11]
     *  FIR_SCOMFIR_ERROR
     */
    (rMCPPEFIR, bit(11)) ? defaultMaskedError;

    /** MCPPEFIR[12]
     *  FIR_SCOMFIR_ERROR
     */
    (rMCPPEFIR, bit(12)) ? defaultMaskedError;

};

################################################################################
# P9 MC target MCBISTFIR
################################################################################

rule rMCBISTFIR
{
  CHECK_STOP:
    MCBISTFIR & ~MCBISTFIR_MASK & ~MCBISTFIR_ACT0 & ~MCBISTFIR_ACT1;
  RECOVERABLE:
    MCBISTFIR & ~MCBISTFIR_MASK & ~MCBISTFIR_ACT0 &  MCBISTFIR_ACT1;
  HOST_ATTN:
    MCBISTFIR & ~MCBISTFIR_MASK &  MCBISTFIR_ACT0 & ~MCBISTFIR_ACT1;
  UNIT_CS:
    MCBISTFIR & ~MCBISTFIR_MASK &  MCBISTFIR_ACT0 &  MCBISTFIR_ACT1;
};

group gMCBISTFIR
    filter singlebit,
           cs_root_cause
{
    /** MCBISTFIR[0]
     *  WAT_DEBUG_ATTN
     */
    (rMCBISTFIR, bit(0)) ? defaultMaskedError;

    /** MCBISTFIR[1]
     *  WAT_DEBUG_REG_PE
     */
    (rMCBISTFIR, bit(1)) ? defaultMaskedError;

    /** MCBISTFIR[2]
     *  SCOM_RECOVERABLE_REG_PE
     */
    (rMCBISTFIR, bit(2)) ? self_th_1;

    /** MCBISTFIR[3]
     *  spare
     */
    (rMCBISTFIR, bit(3)) ? defaultMaskedError;

    /** MCBISTFIR[4]
     *  INTERNAL_SCOM_ERROR
     */
    (rMCBISTFIR, bit(4)) ? defaultMaskedError;

    /** MCBISTFIR[5]
     *  INTERNAL_SCOM_ERROR_CLONE
     */
    (rMCBISTFIR, bit(5)) ? defaultMaskedError;

};

 ##############################################################################
 #                                                                            #
 #    #                                  ###                                  #
 #   # #    ##  ##### ###  ###  #   #   #   # #     #    ###   ###  ###  ###  #
 #  #   #  #  #   #    #  #   # ##  #   #     #    # #  #     #     #   #     #
 # ####### #      #    #  #   # # # #   #     #   #####  ###   ###  ##   ###  #
 # #     # #  #   #    #  #   # #  ##   #   # #   #   #     #     # #       # #
 # #     #  ##    #   ###  ###  #   #    ###  ### #   #  ###   ###  ###  ###  #
 #                                                                            #
 ##############################################################################

# Include the actions defined for this target
.include "p9_common_actions.rule";
.include "cumulus_mc_actions.rule";