# IBM_PROLOG_BEGIN_TAG
# This is an automatically generated prolog.
#
# $Source: src/usr/diag/prdf/common/plat/cumulus/cumulus_dmi.rule $
#
# OpenPOWER HostBoot Project
#
# Contributors Listed Below - COPYRIGHT 2016,2018
# [+] International Business Machines Corp.
#
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
# implied. See the License for the specific language governing
# permissions and limitations under the License.
#
# IBM_PROLOG_END_TAG

chip cumulus_dmi
{
    name        "CUMULUS DMI target";
    targettype  TYPE_DMI;
    sigoff      0x9200;
    dump        DUMP_CONTENT_HW;
    scomlen     64;

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    ############################################################################
    # P9 DMI target CHIFIR
    ############################################################################

    register CHIFIR
    {
        name        "P9 DMI target CHIFIR";
        scomaddr    0x07010900;
        reset       (&, 0x07010901);
        mask        (|, 0x07010905);
        capture     group default;
    };

    register CHIFIR_MASK
    {
        name        "P9 DMI target CHIFIR MASK";
        scomaddr    0x07010903;
        capture     group default;
    };

    register CHIFIR_ACT0
    {
        name        "P9 DMI target CHIFIR ACT0";
        scomaddr    0x07010906;
        capture     group default;
        capture     req nonzero("CHIFIR");
    };

    register CHIFIR_ACT1
    {
        name        "P9 DMI target CHIFIR ACT1";
        scomaddr    0x07010907;
        capture     group default;
        capture     req nonzero("CHIFIR");
    };

# Include registers not defined by the xml
.include "cumulus_dmi_regs.rule";

};

 ##############################################################################
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 ##############################################################################

################################################################################
# Summary for DMI
################################################################################

rule rDMI
{
  CHECK_STOP:
    summary( 0, rCHIFIR );

  RECOVERABLE:
    summary( 0, rCHIFIR );

  UNIT_CS:
    summary( 0, rCHIFIR );

  HOST_ATTN:
    summary( 0, rCHIFIR );

};

group gDMI attntype CHECK_STOP, RECOVERABLE, UNIT_CS, HOST_ATTN
    filter singlebit
{
    (rDMI, bit(0)) ? analyzeCHIFIR;
};

################################################################################
# P9 DMI target CHIFIR
################################################################################

rule rCHIFIR
{
  CHECK_STOP:
    CHIFIR & ~CHIFIR_MASK & ~CHIFIR_ACT0 & ~CHIFIR_ACT1;
  RECOVERABLE:
    CHIFIR & ~CHIFIR_MASK & ~CHIFIR_ACT0 &  CHIFIR_ACT1;
  HOST_ATTN:
    CHIFIR & ~CHIFIR_MASK &  CHIFIR_ACT0 & ~CHIFIR_ACT1;
  UNIT_CS:
    CHIFIR & ~CHIFIR_MASK &  CHIFIR_ACT0 &  CHIFIR_ACT1;
};

# Note that CHIFIR[16:21] indicate there was an attention on the Centaur. All
# bits in this FIR must be prioritized over CHIFIR[16:21]. Otherwise, we may
# get stuck in a loop on some conditions.
group gCHIFIR
    filter priority(0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63),
           cs_root_cause(0,2,4,5,6,12,14,15,16,32,36,40,41,42,43,46,61)
{
    /** CHIFIR[0]
     *  PE on internal register
     */
    (rCHIFIR, bit(0)) ? self_th_1;

    /** CHIFIR[1]
     *  PE on internal register
     */
    (rCHIFIR, bit(1)) ? self_th_1;

    /** CHIFIR[2]
     *  Too many EDI replays due to CRC error
     */
    (rCHIFIR, bit(2)) ? dmi_bus_th_1_UERE;

    /** CHIFIR[3]
     *  EDI bus performance degraded by 1%
     */
    (rCHIFIR, bit(3)) ? defaultMaskedError;

    /** CHIFIR[4]
     *  DMI entered failed state
     */
    (rCHIFIR, bit(4)) ? dmi_bus_th_1; # CUMULUS_10

    /** CHIFIR[5]
     *  Channel initialization timeout
     */
    (rCHIFIR, bit(5)) ? defaultMaskedError;

    /** CHIFIR[6]
     *  Channel interlock error
     */
    (rCHIFIR, bit(6)) ? defaultMaskedError;

    /** CHIFIR[7]
     *  FRTL counter overflow
     */
    (rCHIFIR, bit(7)) ? defaultMaskedError;

    /** CHIFIR[8]
     *  CRC error
     */
    (rCHIFIR, bit(8)) ? dmi_bus_th_1; # CUMULUS_10

    /** CHIFIR[9]
     *  No ack error
     */
    (rCHIFIR, bit(9)) ? defaultMaskedError;

    /** CHIFIR[10]
     *  Sequence ID out of order
     */
    (rCHIFIR, bit(10)) ? defaultMaskedError;

    /** CHIFIR[11]
     *  CE on replay buffer read
     */
    (rCHIFIR, bit(11)) ? self_th_32perDay;

    /** CHIFIR[12]
     *  UE on replay buffer read
     */
    (rCHIFIR, bit(12)) ? self_th_1_UERE;

    /** CHIFIR[13]
     *  Multiple replay
     */
    (rCHIFIR, bit(13)) ? defaultMaskedError;

    /** CHIFIR[14]
     *  Replay buffer overrun
     */
    (rCHIFIR, bit(14)) ? self_th_1_UERE;

    /** CHIFIR[15]
     *  PE on MCI dataflow or state machine
     */
    (rCHIFIR, bit(15)) ? self_th_1_UERE;

    /** CHIFIR[16]
     *  Checkstop attn from memory buffer
     */
    (rCHIFIR, bit(16)) ? analyzeConnectedMembuf_UERE;

    /** CHIFIR[17]
     *  Tracestop received from memory buffer
     */
    (rCHIFIR, bit(17)) ? defaultMaskedError;

    /** CHIFIR[18]
     *  FPGA int received from memory buffer
     */
    (rCHIFIR, bit(18)) ? defaultMaskedError;

    /** CHIFIR[19]
     *  Recoverable attn from memory buffer
     */
    (rCHIFIR, bit(19)) ? analyzeConnectedMembuf;

    /** CHIFIR[20]
     *  Special attn from memory buffer
     */
    (rCHIFIR, bit(20)) ? analyzeConnectedMembuf;

    /** CHIFIR[21]
     *  Maintenance complete from memory buffer
     */
    (rCHIFIR, bit(21)) ? defaultMaskedError;

    /** CHIFIR[22:30]
     *  reserved
     */
    (rCHIFIR, bit(22|23|24|25|26|27|28|29|30)) ? defaultMaskedError;

    /** CHIFIR[31]
     *  USDF sequence error
     */
    (rCHIFIR, bit(31)) ? self_th_1;

    /** CHIFIR[32]
     *  DSFF tag overrun
     */
    (rCHIFIR, bit(32)) ? self_th_1_UERE;

    /** CHIFIR[33]
     *  DSFF DS data error
     */
    (rCHIFIR, bit(33)) ? self_th_1;

    /** CHIFIR[34:35]
     *  reserved
     */
    (rCHIFIR, bit(34|35)) ? defaultMaskedError;

    /** CHIFIR[36]
     *  Rdata parity error
     */
    (rCHIFIR, bit(36)) ? self_th_1_UERE;

    /** CHIFIR[37:39]
     *  reserved
     */
    (rCHIFIR, bit(37|38|39)) ? defaultMaskedError;

    /** CHIFIR[40]
     *  DSFF async cmd parity error
     */
    (rCHIFIR, bit(40)) ? self_th_1_UERE;

    /** CHIFIR[41]
     *  DSFF async cmd sequence error
     */
    (rCHIFIR, bit(41)) ? self_th_1_UERE;

    /** CHIFIR[42]
     *  DSFF state machine error
     */
    (rCHIFIR, bit(42)) ? self_th_1_UERE;

    /** CHIFIR[43]
     *  Recoverable parity error on EICR
     */
    (rCHIFIR, bit(43)) ? self_th_1;

    /** CHIFIR[44]
     *  Recoverable parity error on RECR
     */
    (rCHIFIR, bit(44)) ? self_th_1;

    /** CHIFIR[45]
     *  CE on WRT or RMW buffer
     */
    (rCHIFIR, bit(45)) ? self_th_32perDay;

    /** CHIFIR[46]
     *  UE on WRT or RMW buffer
     */
    (rCHIFIR, bit(46)) ? self_th_1_UERE;

    /** CHIFIR[47]
     *  SUE on WRT or RMW buffer
     */
    (rCHIFIR, bit(47)) ? defaultMaskedError;

    /** CHIFIR[48:49]
     *  WDF overrun error
     */
    (rCHIFIR, bit(48|49)) ? self_th_1;

    /** CHIFIR[50]
     *  WDF SCOM sequence error
     */
    (rCHIFIR, bit(50)) ? self_th_1;

    /** CHIFIR[51]
     *  WDF state machine error
     */
    (rCHIFIR, bit(51)) ? self_th_1;

    /** CHIFIR[52]
     *  WDF register parity error
     */
    (rCHIFIR, bit(52)) ? self_th_1;

    /** CHIFIR[53]
     *  WRT SCOM sequence error
     */
    (rCHIFIR, bit(53)) ? self_th_1;

    /** CHIFIR[54]
     *  WRT register parity error.
     */
    (rCHIFIR, bit(54)) ? self_th_1;

    /** CHIFIR[55]
     *  reserved
     */
    (rCHIFIR, bit(55)) ? defaultMaskedError;

    /** CHIFIR[56]
     *  Read buffer overrun
     */
    (rCHIFIR, bit(56)) ? self_th_1;

    /** CHIFIR[57]
     *  WDF async error
     */
    (rCHIFIR, bit(57)) ? self_th_1;

    /** CHIFIR[58:59]
     *  reserved
     */
    (rCHIFIR, bit(58|59)) ? defaultMaskedError;

    /** CHIFIR[60]
     *  Debug/WAT register parity error
     */
    (rCHIFIR, bit(60)) ? defaultMaskedError;

    /** CHIFIR[61]
     *  DSFF channel timeout
     */
    (rCHIFIR, bit(61)) ? dsffChannelTimeout_UERE;

    /** CHIFIR[62]
     *  SCOM error
     */
    (rCHIFIR, bit(62)) ? defaultMaskedError;

    /** CHIFIR[63]
     *  SCOM error
     */
    (rCHIFIR, bit(63)) ? defaultMaskedError;

};

 ##############################################################################
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 ##############################################################################

# Include the actions defined for this target
.include "p9_common_actions.rule";
.include "cumulus_dmi_actions.rule";