# IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # # $Source: src/usr/diag/prdf/common/plat/axone/axone_pec.rule $ # # OpenPOWER HostBoot Project # # Contributors Listed Below - COPYRIGHT 2018 # [+] International Business Machines Corp. # # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or # implied. See the License for the specific language governing # permissions and limitations under the License. # # IBM_PROLOG_END_TAG chip axone_pec { name "AXONE PEC target"; targettype TYPE_PEC; sigoff 0x0000; dump DUMP_CONTENT_HW; scomlen 64; ############################################################################# # # # ###### # # # # ###### #### ### #### ##### ###### ##### #### # # # # # # # # # # # # # # # # ###### ##### # # #### # ##### # # #### # # # # # # ### # # # # ##### # # # # # # # # # # # # # # # # # # # # # ###### #### ### #### # ###### # # #### # # # ############################################################################# ############################################################################ # P9 PEC target PCI_LFIR ############################################################################ register PCI_LFIR { name "P9 PEC target PCI_LFIR"; scomaddr 0x0d04000a; reset (&, 0x0d04000b); mask (|, 0x0d04000f); capture group default; }; register PCI_LFIR_MASK { name "P9 PEC target PCI_LFIR MASK"; scomaddr 0x0d04000d; capture group default; }; register PCI_LFIR_ACT0 { name "P9 PEC target PCI_LFIR ACT0"; scomaddr 0x0d040010; capture group default; capture req nonzero("PCI_LFIR"); }; register PCI_LFIR_ACT1 { name "P9 PEC target PCI_LFIR ACT1"; scomaddr 0x0d040011; capture group default; capture req nonzero("PCI_LFIR"); }; ############################################################################ # P9 PEC target IOPCIFIR ############################################################################ register IOPCIFIR { name "P9 PEC target IOPCIFIR"; scomaddr 0x0d010c00; reset (&, 0x0d010c01); mask (|, 0x0d010c05); capture group default; }; register IOPCIFIR_MASK { name "P9 PEC target IOPCIFIR MASK"; scomaddr 0x0d010c03; capture group default; }; register IOPCIFIR_ACT0 { name "P9 PEC target IOPCIFIR ACT0"; scomaddr 0x0d010c06; capture group default; capture req nonzero("IOPCIFIR"); }; register IOPCIFIR_ACT1 { name "P9 PEC target IOPCIFIR ACT1"; scomaddr 0x0d010c07; capture group default; capture req nonzero("IOPCIFIR"); }; # Include registers not defined by the xml .include "p9_common_pec_regs.rule"; }; ############################################################################## # # # #### # # # # # # # # ##### ### # # # ## ##### ### ### # # ### # # # # # # # # # # # # # # # # # # ## # # # # #### # # # #### ### # ####### # # # # # # # # ### # # # # # # # # # # # # # # # # # # # ## # # # # # ### #### ##### ### # # # ## # ### ### # # ### # # # ############################################################################## ################################################################################ # Summary for PEC ################################################################################ rule rPEC { CHECK_STOP: summary( 0, rPCI_LFIR ) | summary( 1, rIOPCIFIR ); RECOVERABLE: summary( 0, rPCI_LFIR ) | summary( 1, rIOPCIFIR ); }; group gPEC attntype CHECK_STOP, RECOVERABLE filter singlebit { (rPEC, bit(0)) ? analyzePCI_LFIR; (rPEC, bit(1)) ? analyzeIOPCIFIR; }; ################################################################################ # P9 PEC target PCI_LFIR ################################################################################ rule rPCI_LFIR { CHECK_STOP: PCI_LFIR & ~PCI_LFIR_MASK & ~PCI_LFIR_ACT0 & ~PCI_LFIR_ACT1; RECOVERABLE: PCI_LFIR & ~PCI_LFIR_MASK & ~PCI_LFIR_ACT0 & PCI_LFIR_ACT1; }; group gPCI_LFIR filter singlebit, cs_root_cause { /** PCI_LFIR[0] * CFIR internal parity error */ (rPCI_LFIR, bit(0)) ? self_th_32perDay; /** PCI_LFIR[1] * Chiplet Control Reg: PCB Access Error */ (rPCI_LFIR, bit(1)) ? self_th_32perDay; /** PCI_LFIR[2] * Clock Controller: PCB Access Error */ (rPCI_LFIR, bit(2)) ? self_th_32perDay; /** PCI_LFIR[3] * Clock Controller: Summarized Error */ (rPCI_LFIR, bit(3)) ? self_th_32perDay; /** PCI_LFIR[4] * PSCOM Logic: PCB Access Error */ (rPCI_LFIR, bit(4)) ? defaultMaskedError; /** PCI_LFIR[5] * PSCOM Logic: Summarized internal errors */ (rPCI_LFIR, bit(5)) ? defaultMaskedError; /** PCI_LFIR[6] * Therm Logic: Summarized internal errors */ (rPCI_LFIR, bit(6)) ? defaultMaskedError; /** PCI_LFIR[7] * Therm Logic: PCB Access Error */ (rPCI_LFIR, bit(7)) ? defaultMaskedError; /** PCI_LFIR[8] * Therm Logic: Temperature critical trip */ (rPCI_LFIR, bit(8)) ? defaultMaskedError; /** PCI_LFIR[9] * Therm Logic: Temperature fatal trip */ (rPCI_LFIR, bit(9)) ? defaultMaskedError; /** PCI_LFIR[10] * UNUSED in P9 */ (rPCI_LFIR, bit(10)) ? defaultMaskedError; /** PCI_LFIR[11] * Debug Logic: Scom Satellite Error */ (rPCI_LFIR, bit(11)) ? defaultMaskedError; /** PCI_LFIR[12] * Scom Satellite Error - L3 Trace0 */ (rPCI_LFIR, bit(12)) ? defaultMaskedError; /** PCI_LFIR[13] * Scom Satellite Error - L3 Trace0 */ (rPCI_LFIR, bit(13)) ? defaultMaskedError; /** PCI_LFIR[14:40] * unused */ (rPCI_LFIR, bit(14|15|16|17|18|19|20|21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39|40)) ? defaultMaskedError; /** PCI_LFIR[41] * Malfunction Alert or Local Checkstop */ (rPCI_LFIR, bit(41)) ? defaultMaskedError; }; ################################################################################ # P9 PEC target IOPCIFIR ################################################################################ rule rIOPCIFIR { CHECK_STOP: IOPCIFIR & ~IOPCIFIR_MASK & ~IOPCIFIR_ACT0 & ~IOPCIFIR_ACT1; RECOVERABLE: IOPCIFIR & ~IOPCIFIR_MASK & ~IOPCIFIR_ACT0 & IOPCIFIR_ACT1; }; group gIOPCIFIR filter singlebit, cs_root_cause { /** IOPCIFIR[0] * HSS ZCAL Calibration Error */ (rIOPCIFIR, bit(0)) ? parent_proc_th_1; /** IOPCIFIR[1] * HSS CAL PLL A Calibration error */ (rIOPCIFIR, bit(1)) ? parent_proc_th_1; /** IOPCIFIR[2] * HSS CAL PLL B Calibration error */ (rIOPCIFIR, bit(2)) ? parent_proc_th_1; /** IOPCIFIR[3] * TX Lane A Calibration Error */ (rIOPCIFIR, bit(3)) ? defaultMaskedError; /** IOPCIFIR[4] * TX Lane B Calibration Error */ (rIOPCIFIR, bit(4)) ? defaultMaskedError; /** IOPCIFIR[5] * TX Lane C Calibration Error */ (rIOPCIFIR, bit(5)) ? defaultMaskedError; /** IOPCIFIR[6] * TX Lane D Calibration Error */ (rIOPCIFIR, bit(6)) ? defaultMaskedError; /** IOPCIFIR[7] * TX Lane E Calibration Error */ (rIOPCIFIR, bit(7)) ? defaultMaskedError; /** IOPCIFIR[8] * TX Lane F Calibration Error */ (rIOPCIFIR, bit(8)) ? defaultMaskedError; /** IOPCIFIR[9] * TX Lane G Calibration Error */ (rIOPCIFIR, bit(9)) ? defaultMaskedError; /** IOPCIFIR[10] * TX Lane H Calibration Error */ (rIOPCIFIR, bit(10)) ? defaultMaskedError; /** IOPCIFIR[11] * TX Lane I Calibration Error */ (rIOPCIFIR, bit(11)) ? defaultMaskedError; /** IOPCIFIR[12] * TX Lane J Calibration Error */ (rIOPCIFIR, bit(12)) ? defaultMaskedError; /** IOPCIFIR[13] * TX Lane K Calibration Error */ (rIOPCIFIR, bit(13)) ? defaultMaskedError; /** IOPCIFIR[14] * TX Lane L Calibration Error */ (rIOPCIFIR, bit(14)) ? defaultMaskedError; /** IOPCIFIR[15] * TX Lane M Calibration Error */ (rIOPCIFIR, bit(15)) ? defaultMaskedError; /** IOPCIFIR[16] * TX Lane N Calibration Error */ (rIOPCIFIR, bit(16)) ? defaultMaskedError; /** IOPCIFIR[17] * TX Lane O Calibration Error */ (rIOPCIFIR, bit(17)) ? defaultMaskedError; /** IOPCIFIR[18] * TX Lane P Calibration Error */ (rIOPCIFIR, bit(18)) ? defaultMaskedError; /** IOPCIFIR[19] * RX Lane A Calibration Error */ (rIOPCIFIR, bit(19)) ? defaultMaskedError; /** IOPCIFIR[20] * RX Lane B Calibration Error */ (rIOPCIFIR, bit(20)) ? defaultMaskedError; /** IOPCIFIR[21] * RX Lane C Calibration Error */ (rIOPCIFIR, bit(21)) ? defaultMaskedError; /** IOPCIFIR[22] * RX Lane D Calibration Error */ (rIOPCIFIR, bit(22)) ? defaultMaskedError; /** IOPCIFIR[23] * RX Lane E Calibration Error */ (rIOPCIFIR, bit(23)) ? defaultMaskedError; /** IOPCIFIR[24] * RX Lane F Calibration Error */ (rIOPCIFIR, bit(24)) ? defaultMaskedError; /** IOPCIFIR[25] * RX Lane G Calibration Error */ (rIOPCIFIR, bit(25)) ? defaultMaskedError; /** IOPCIFIR[26] * RX Lane H Calibration Error */ (rIOPCIFIR, bit(26)) ? defaultMaskedError; /** IOPCIFIR[27] * RX Lane I Calibration Error */ (rIOPCIFIR, bit(27)) ? defaultMaskedError; /** IOPCIFIR[28] * RX Lane J Calibration Error */ (rIOPCIFIR, bit(28)) ? defaultMaskedError; /** IOPCIFIR[29] * RX Lane K Calibration Error */ (rIOPCIFIR, bit(29)) ? defaultMaskedError; /** IOPCIFIR[30] * RX Lane L Calibration Error */ (rIOPCIFIR, bit(30)) ? defaultMaskedError; /** IOPCIFIR[31] * RX Lane M Calibration Error */ (rIOPCIFIR, bit(31)) ? defaultMaskedError; /** IOPCIFIR[32] * RX Lane N Calibration Error */ (rIOPCIFIR, bit(32)) ? defaultMaskedError; /** IOPCIFIR[33] * RX Lane O Calibration Error */ (rIOPCIFIR, bit(33)) ? defaultMaskedError; /** IOPCIFIR[34] * RX Lane P Calibration Error */ (rIOPCIFIR, bit(34)) ? defaultMaskedError; /** IOPCIFIR[35] * SCOM FIR Parity Error 0 */ (rIOPCIFIR, bit(35)) ? defaultMaskedError; /** IOPCIFIR[36] * SCOM FIR Parity Error 1 */ (rIOPCIFIR, bit(36)) ? defaultMaskedError; }; ############################################################################## # # # # ### # # # # ## ##### ### ### # # # # # # ### ### ### ### # # # # # # # # # # ## # # # # # # # # # # # ####### # # # # # # # # # # ##### ### ### ## ### # # # # # # # # # # # ## # # # # # # # # # # # # # ## # ### ### # # ### ### # # ### ### ### ### # # # ############################################################################## # Include the actions defined for this target .include "p9_common_actions.rule"; .include "p9_common_pec_actions.rule";