# IBM_PROLOG_BEGIN_TAG
# This is an automatically generated prolog.
#
# $Source: src/usr/diag/prdf/common/plat/axone/axone_omic.rule $
#
# OpenPOWER HostBoot Project
#
# Contributors Listed Below - COPYRIGHT 2018,2020
# [+] International Business Machines Corp.
#
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
# implied. See the License for the specific language governing
# permissions and limitations under the License.
#
# IBM_PROLOG_END_TAG

chip axone_omic
{
    name        "AXONE OMIC target";
    targettype  TYPE_OMIC;
    sigoff      0x0000;
    dump        DUMP_CONTENT_HW;
    scomlen     64;

 #############################################################################
 #                                                                           #
 #  ######                                                                   #
 #  #     #  ######   ####     ###    ####    #####  ######  #####    ####   #
 #  #     #  #       #    #     #    #          #    #       #    #  #       #
 #  ######   #####   #          #     ####      #    #####   #    #   ####   #
 #  #   #    #       #  ###     #         #     #    #       #####        #  #
 #  #    #   #       #    #     #    #    #     #    #       #   #   #    #  #
 #  #     #  ######   ####     ###    ####      #    ######  #    #   ####   #
 #                                                                           #
 #############################################################################

    ############################################################################
    # P9 OMIC target IOOMIFIR
    ############################################################################

    register IOOMIFIR
    {
        name        "P9 OMIC target IOOMIFIR";
        scomaddr    0x07011000;
        reset       (&, 0x07011001);
        mask        (|, 0x07011005);
        capture     group default;
    };

    register IOOMIFIR_MASK
    {
        name        "P9 OMIC target IOOMIFIR MASK";
        scomaddr    0x07011003;
        capture     group default;
    };

    register IOOMIFIR_ACT0
    {
        name        "P9 OMIC target IOOMIFIR ACT0";
        scomaddr    0x07011006;
        capture     group default;
        capture     req nonzero("IOOMIFIR");
    };

    register IOOMIFIR_ACT1
    {
        name        "P9 OMIC target IOOMIFIR ACT1";
        scomaddr    0x07011007;
        capture     group default;
        capture     req nonzero("IOOMIFIR");
    };

    ############################################################################
    # P9 OMIC target MCPPEFIR
    ############################################################################

    register MCPPEFIR
    {
        name        "P9 OMIC target MCPPEFIR";
        scomaddr    0x07012440;
        reset       (&, 0x07012441);
        mask        (|, 0x07012445);
        capture     group default;
    };

    register MCPPEFIR_MASK
    {
        name        "P9 OMIC target MCPPEFIR MASK";
        scomaddr    0x07012443;
        capture     group default;
    };

    register MCPPEFIR_ACT0
    {
        name        "P9 OMIC target MCPPEFIR ACT0";
        scomaddr    0x07012446;
        capture     group default;
        capture     req nonzero("MCPPEFIR");
    };

    register MCPPEFIR_ACT1
    {
        name        "P9 OMIC target MCPPEFIR ACT1";
        scomaddr    0x07012447;
        capture     group default;
        capture     req nonzero("MCPPEFIR");
    };

    ############################################################################
    # P9 OMIC target OMIDLFIR
    ############################################################################

    register OMIDLFIR
    {
        name        "P9 OMIC target OMIDLFIR";
        scomaddr    0x07013340;
        reset       (&, 0x07013341);
        mask        (|, 0x07013345);
        capture     group default;
    };

    register OMIDLFIR_MASK
    {
        name        "P9 OMIC target OMIDLFIR MASK";
        scomaddr    0x07013343;
        capture     group default;
    };

    register OMIDLFIR_ACT0
    {
        name        "P9 OMIC target OMIDLFIR ACT0";
        scomaddr    0x07013346;
        capture     group default;
        capture     req nonzero("OMIDLFIR");
    };

    register OMIDLFIR_ACT1
    {
        name        "P9 OMIC target OMIDLFIR ACT1";
        scomaddr    0x07013347;
        capture     group default;
        capture     req nonzero("OMIDLFIR");
    };

# Include registers not defined by the xml
.include "axone_omic_regs.rule";

};

 ##############################################################################
 #                                                                            #
 # ####                                 #                                     #
 # #   # #   # #    #####  ###      #  # #    ##  ##### ###  ###  #   #  ###  #
 # #   # #   # #    #     #        #  #   #  #  #   #    #  #   # ##  # #     #
 # ####  #   # #    ####   ###    #  ####### #      #    #  #   # # # #  ###  #
 # #  #  #   # #    #         #  #   #     # #  #   #    #  #   # #  ##     # #
 # #   #  ###  #### #####  ###  #    #     #  ##    #   ###  ###  #   #  ###  #
 #                                                                            #
 ##############################################################################

################################################################################
# Summary for OMIC
################################################################################

rule rOMIC
{
  CHECK_STOP:
    summary( 0, rIOOMIFIR ) |
    summary( 1, rMCPPEFIR ) |
    summary( 2, rOMIDLFIR );

  RECOVERABLE:
    summary( 0, rIOOMIFIR ) |
    summary( 1, rMCPPEFIR ) |
    summary( 2, rOMIDLFIR );

  UNIT_CS:
    summary( 0, rIOOMIFIR ) |
    summary( 1, rMCPPEFIR ) |
    summary( 2, rOMIDLFIR );

  HOST_ATTN:
    summary( 0, rIOOMIFIR ) |
    summary( 1, rMCPPEFIR ) |
    summary( 2, rOMIDLFIR );

};

group gOMIC attntype CHECK_STOP, RECOVERABLE, UNIT_CS, HOST_ATTN
    filter priority(2,0,1)
{
    # We need to prioritize analysis to the OMIDLFIR here because of potential
    # Channel Fail attentions in that FIR that will be reported as RECOVERABLE.
    (rOMIC, bit(0)) ? analyzeIOOMIFIR;
    (rOMIC, bit(1)) ? analyzeMCPPEFIR;
    (rOMIC, bit(2)) ? analyzeOMIDLFIR;
};

################################################################################
# P9 OMIC target IOOMIFIR
################################################################################

rule rIOOMIFIR
{
  CHECK_STOP:
    IOOMIFIR & ~IOOMIFIR_MASK & ~IOOMIFIR_ACT0 & ~IOOMIFIR_ACT1;
  RECOVERABLE:
    IOOMIFIR & ~IOOMIFIR_MASK & ~IOOMIFIR_ACT0 &  IOOMIFIR_ACT1;
  HOST_ATTN:
    IOOMIFIR & ~IOOMIFIR_MASK &  IOOMIFIR_ACT0 & ~IOOMIFIR_ACT1;
  UNIT_CS:
    IOOMIFIR & ~IOOMIFIR_MASK &  IOOMIFIR_ACT0 &  IOOMIFIR_ACT1;
};

group gIOOMIFIR
    filter singlebit,
           cs_root_cause
{
    /** IOOMIFIR[0]
     *  RX invalid state or parity error
     */
    (rIOOMIFIR, bit(0)) ? self_th_1;

    /** IOOMIFIR[1]
     *  TX invalid state or parity error
     */
    (rIOOMIFIR, bit(1)) ? self_th_1;

    /** IOOMIFIR[2]
     *  GCR hang error
     */
    (rIOOMIFIR, bit(2)) ? self_th_1;

    /** IOOMIFIR[3:47]
     *  Unused
     */
    (rIOOMIFIR, bit(3|4|5|6|7|8|9|10|11|12|13|14|15|16|17|18|19|20|21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39|40|41|42|43|44|45|46|47)) ? defaultMaskedError;

    /** IOOMIFIR[48]
     *  SCOM FSM or FIR register parity error
     */
    (rIOOMIFIR, bit(48)) ? defaultMaskedError;

    /** IOOMIFIR[49]
     *  SCOM FSM or FIR register parity error clone
     */
    (rIOOMIFIR, bit(49)) ? defaultMaskedError;

};

################################################################################
# P9 OMIC target MCPPEFIR
################################################################################

rule rMCPPEFIR
{
  CHECK_STOP:
    MCPPEFIR & ~MCPPEFIR_MASK & ~MCPPEFIR_ACT0 & ~MCPPEFIR_ACT1;
  RECOVERABLE:
    MCPPEFIR & ~MCPPEFIR_MASK & ~MCPPEFIR_ACT0 &  MCPPEFIR_ACT1;
  HOST_ATTN:
    MCPPEFIR & ~MCPPEFIR_MASK &  MCPPEFIR_ACT0 & ~MCPPEFIR_ACT1;
  UNIT_CS:
    MCPPEFIR & ~MCPPEFIR_MASK &  MCPPEFIR_ACT0 &  MCPPEFIR_ACT1;
};

group gMCPPEFIR
    filter singlebit,
           cs_root_cause
{
    /** MCPPEFIR[0]
     *  PPE general error.
     */
    (rMCPPEFIR, bit(0)) ? defaultMaskedError;

    /** MCPPEFIR[1]
     *  PPE general error.
     */
    (rMCPPEFIR, bit(1)) ? defaultMaskedError;

    /** MCPPEFIR[2]
     *  PPE general error.
     */
    (rMCPPEFIR, bit(2)) ? defaultMaskedError;

    /** MCPPEFIR[3]
     *  PPE general error.
     */
    (rMCPPEFIR, bit(3)) ? defaultMaskedError;

    /** MCPPEFIR[4]
     *  PPE halted.
     */
    (rMCPPEFIR, bit(4)) ? defaultMaskedError;

    /** MCPPEFIR[5]
     *  PPE watchdog timer timed out
     */
    (rMCPPEFIR, bit(5)) ? defaultMaskedError;

    /** MCPPEFIR[6]
     *  MMIO data in error.
     */
    (rMCPPEFIR, bit(6)) ? defaultMaskedError;

    /** MCPPEFIR[7]
     *  Arb missed scrub tick.
     */
    (rMCPPEFIR, bit(7)) ? defaultMaskedError;

    /** MCPPEFIR[8]
     *  Arb ary ue error.
     */
    (rMCPPEFIR, bit(8)) ? defaultMaskedError;

    /** MCPPEFIR[9]
     *  Arb ary ce error.
     */
    (rMCPPEFIR, bit(9)) ? defaultMaskedError;

    /** MCPPEFIR[10]
     *  spare
     */
    (rMCPPEFIR, bit(10)) ? defaultMaskedError;

    /** MCPPEFIR[11]
     *  FIR_SCOMFIR_ERROR
     */
    (rMCPPEFIR, bit(11)) ? defaultMaskedError;

    /** MCPPEFIR[12]
     *  FIR_SCOMFIR_ERROR
     */
    (rMCPPEFIR, bit(12)) ? defaultMaskedError;

};

################################################################################
# P9 OMIC target OMIDLFIR
################################################################################

rule rOMIDLFIR
{
  CHECK_STOP:
    OMIDLFIR & ~OMIDLFIR_MASK & ~OMIDLFIR_ACT0 & ~OMIDLFIR_ACT1;
  RECOVERABLE:
    OMIDLFIR & ~OMIDLFIR_MASK & ~OMIDLFIR_ACT0 &  OMIDLFIR_ACT1;
  HOST_ATTN:
    OMIDLFIR & ~OMIDLFIR_MASK &  OMIDLFIR_ACT0 & ~OMIDLFIR_ACT1;
  UNIT_CS:
    OMIDLFIR & ~OMIDLFIR_MASK &  OMIDLFIR_ACT0 &  OMIDLFIR_ACT1;
};

group gOMIDLFIR
    filter priority(0,20,40),
           cs_root_cause(0,20,40)
{
    /** OMIDLFIR[0]
     *  OMI-DL0 fatal error
     */
    (rOMIDLFIR, bit(0)) ? dl0_fatal_error;

    /** OMIDLFIR[1]
     *  OMI-DL0 UE on data flit
     */
    (rOMIDLFIR, bit(1)) ? dl0_omi_th_1;

    /** OMIDLFIR[2]
     *  OMI-DL0 CE on TL flit
     */
    (rOMIDLFIR, bit(2)) ? dl0_omi_th_32perDay;

    /** OMIDLFIR[3]
     *  OMI-DL0 detected a CRC error
     */
    (rOMIDLFIR, bit(3)) ? defaultMaskedError;

    /** OMIDLFIR[4]
     *  OMI-DL0 received a nack
     */
    (rOMIDLFIR, bit(4)) ? defaultMaskedError;

    /** OMIDLFIR[5]
     *  OMI-DL0 running in degraded mode
     */
    (rOMIDLFIR, bit(5)) ? dl0_omi_bus_th_1;

    /** OMIDLFIR[6]
     *  OMI-DL0 parity error detection on a lane
     */
    (rOMIDLFIR, bit(6)) ? defaultMaskedError;

    /** OMIDLFIR[7]
     *  OMI-DL0 retrained due to no forward progress
     */
    (rOMIDLFIR, bit(7)) ? dl0_omi_bus_th_32perDay;

    /** OMIDLFIR[8]
     *  OMI-DL0 remote side initiated a retrain
     */
    (rOMIDLFIR, bit(8)) ? defaultMaskedError;

    /** OMIDLFIR[9]
     *  OMI-DL0 retrain due to internal error or software initiated
     */
    (rOMIDLFIR, bit(9)) ? dl0_omi_bus_th_32perDay;

    /** OMIDLFIR[10]
     *  OMI-DL0 threshold reached
     */
    (rOMIDLFIR, bit(10)) ? dl0_omi_bus_th_32perDay;

    /** OMIDLFIR[11]
     *  OMI-DL0 trained
     */
    (rOMIDLFIR, bit(11)) ? defaultMaskedError;

    /** OMIDLFIR[12]
     *  OMI-DL0 endpoint error bit 0
     */
    (rOMIDLFIR, bit(12)) ? defaultMaskedError;

    /** OMIDLFIR[13]
     *  OMI-DL0 endpoint error bit 1
     */
    (rOMIDLFIR, bit(13)) ? defaultMaskedError;

    /** OMIDLFIR[14]
     *  OMI-DL0 endpoint error bit 2
     */
    (rOMIDLFIR, bit(14)) ? defaultMaskedError;

    /** OMIDLFIR[15]
     *  OMI-DL0 endpoint error bit 3
     */
    (rOMIDLFIR, bit(15)) ? defaultMaskedError;

    /** OMIDLFIR[16]
     *  OMI-DL0 endpoint error bit 4
     */
    (rOMIDLFIR, bit(16)) ? defaultMaskedError;

    /** OMIDLFIR[17]
     *  OMI-DL0 endpoint error bit 5
     */
    (rOMIDLFIR, bit(17)) ? defaultMaskedError;

    /** OMIDLFIR[18]
     *  OMI-DL0 endpoint error bit 6
     */
    (rOMIDLFIR, bit(18)) ? defaultMaskedError;

    /** OMIDLFIR[19]
     *  OMI-DL0 endpoint error bit 7
     */
    (rOMIDLFIR, bit(19)) ? defaultMaskedError;

    /** OMIDLFIR[20]
     *  OMI-DL1 fatal error
     */
    (rOMIDLFIR, bit(20)) ? dl1_fatal_error;

    /** OMIDLFIR[21]
     *  OMI-DL1 UE on data flit
     */
    (rOMIDLFIR, bit(21)) ? dl1_omi_th_1;

    /** OMIDLFIR[22]
     *  OMI-DL1 CE on TL flit
     */
    (rOMIDLFIR, bit(22)) ? dl1_omi_th_32perDay;

    /** OMIDLFIR[23]
     *  OMI-DL1 detected a CRC error
     */
    (rOMIDLFIR, bit(23)) ? defaultMaskedError;

    /** OMIDLFIR[24]
     *  OMI-DL1 received a nack
     */
    (rOMIDLFIR, bit(24)) ? defaultMaskedError;

    /** OMIDLFIR[25]
     *  OMI-DL1 running in degraded mode
     */
    (rOMIDLFIR, bit(25)) ? dl1_omi_bus_th_1;

    /** OMIDLFIR[26]
     *  OMI-DL1 parity error detection on a lane
     */
    (rOMIDLFIR, bit(26)) ? defaultMaskedError;

    /** OMIDLFIR[27]
     *  OMI-DL1 retrained due to no forward progress
     */
    (rOMIDLFIR, bit(27)) ? dl1_omi_bus_th_32perDay;

    /** OMIDLFIR[28]
     *  OMI-DL1 remote side initiated a retrain
     */
    (rOMIDLFIR, bit(28)) ? defaultMaskedError;

    /** OMIDLFIR[29]
     *  OMI-DL1 retrain due to internal error or software initiated
     */
    (rOMIDLFIR, bit(29)) ? dl1_omi_bus_th_32perDay;

    /** OMIDLFIR[30]
     *  OMI-DL1 threshold reached
     */
    (rOMIDLFIR, bit(30)) ? dl1_omi_bus_th_32perDay;

    /** OMIDLFIR[31]
     *  OMI-DL1 trained
     */
    (rOMIDLFIR, bit(31)) ? defaultMaskedError;

    /** OMIDLFIR[32]
     *  OMI-DL1 endpoint error bit 0
     */
    (rOMIDLFIR, bit(32)) ? defaultMaskedError;

    /** OMIDLFIR[33]
     *  OMI-DL1 endpoint error bit 1
     */
    (rOMIDLFIR, bit(33)) ? defaultMaskedError;

    /** OMIDLFIR[34]
     *  OMI-DL1 endpoint error bit 2
     */
    (rOMIDLFIR, bit(34)) ? defaultMaskedError;

    /** OMIDLFIR[35]
     *  OMI-DL1 endpoint error bit 3
     */
    (rOMIDLFIR, bit(35)) ? defaultMaskedError;

    /** OMIDLFIR[36]
     *  OMI-DL1 endpoint error bit 4
     */
    (rOMIDLFIR, bit(36)) ? defaultMaskedError;

    /** OMIDLFIR[37]
     *  OMI-DL1 endpoint error bit 5
     */
    (rOMIDLFIR, bit(37)) ? defaultMaskedError;

    /** OMIDLFIR[38]
     *  OMI-DL1 endpoint error bit 6
     */
    (rOMIDLFIR, bit(38)) ? defaultMaskedError;

    /** OMIDLFIR[39]
     *  OMI-DL1 endpoint error bit 7
     */
    (rOMIDLFIR, bit(39)) ? defaultMaskedError;

    /** OMIDLFIR[40]
     *  OMI-DL2 fatal error
     */
    (rOMIDLFIR, bit(40)) ? dl2_fatal_error;

    /** OMIDLFIR[41]
     *  OMI-DL2 UE on data flit
     */
    (rOMIDLFIR, bit(41)) ? dl2_omi_th_1;

    /** OMIDLFIR[42]
     *  OMI-DL2 CE on TL flit
     */
    (rOMIDLFIR, bit(42)) ? dl2_omi_th_32perDay;

    /** OMIDLFIR[43]
     *  OMI-DL2 detected a CRC error
     */
    (rOMIDLFIR, bit(43)) ? defaultMaskedError;

    /** OMIDLFIR[44]
     *  OMI-DL2 received a nack
     */
    (rOMIDLFIR, bit(44)) ? defaultMaskedError;

    /** OMIDLFIR[45]
     *  OMI-DL2 running in degraded mode
     */
    (rOMIDLFIR, bit(45)) ? dl2_omi_bus_th_1;

    /** OMIDLFIR[46]
     *  OMI-DL2 parity error detection on a lane
     */
    (rOMIDLFIR, bit(46)) ? defaultMaskedError;

    /** OMIDLFIR[47]
     *  OMI-DL2 retrained due to no forward progress
     */
    (rOMIDLFIR, bit(47)) ? dl2_omi_bus_th_32perDay;

    /** OMIDLFIR[48]
     *  OMI-DL2 remote side initiated a retrain
     */
    (rOMIDLFIR, bit(48)) ? defaultMaskedError;

    /** OMIDLFIR[49]
     *  OMI-DL2 retrain due to internal error or software initiated
     */
    (rOMIDLFIR, bit(49)) ? dl2_omi_bus_th_32perDay;

    /** OMIDLFIR[50]
     *  OMI-DL2 threshold reached
     */
    (rOMIDLFIR, bit(50)) ? dl2_omi_bus_th_32perDay;

    /** OMIDLFIR[51]
     *  OMI-DL2 trained
     */
    (rOMIDLFIR, bit(51)) ? defaultMaskedError;

    /** OMIDLFIR[52]
     *  OMI-DL2 endpoint error bit 0
     */
    (rOMIDLFIR, bit(52)) ? defaultMaskedError;

    /** OMIDLFIR[53]
     *  OMI-DL2 endpoint error bit 1
     */
    (rOMIDLFIR, bit(53)) ? defaultMaskedError;

    /** OMIDLFIR[54]
     *  OMI-DL2 endpoint error bit 2
     */
    (rOMIDLFIR, bit(54)) ? defaultMaskedError;

    /** OMIDLFIR[55]
     *  OMI-DL2 endpoint error bit 3
     */
    (rOMIDLFIR, bit(55)) ? defaultMaskedError;

    /** OMIDLFIR[56]
     *  OMI-DL2 endpoint error bit 4
     */
    (rOMIDLFIR, bit(56)) ? defaultMaskedError;

    /** OMIDLFIR[57]
     *  OMI-DL2 endpoint error bit 5
     */
    (rOMIDLFIR, bit(57)) ? defaultMaskedError;

    /** OMIDLFIR[58]
     *  OMI-DL2 endpoint error bit 6
     */
    (rOMIDLFIR, bit(58)) ? defaultMaskedError;

    /** OMIDLFIR[59]
     *  OMI-DL2 endpoint error bit 7
     */
    (rOMIDLFIR, bit(59)) ? defaultMaskedError;

    /** OMIDLFIR[60]
     *  Performance monitor wrapped
     */
    (rOMIDLFIR, bit(60)) ? defaultMaskedError;

    /** OMIDLFIR[61]
     *  reserved
     */
    (rOMIDLFIR, bit(61)) ? defaultMaskedError;

    /** OMIDLFIR[62]
     *  LFIR internal parity error
     */
    (rOMIDLFIR, bit(62)) ? defaultMaskedError;

    /** OMIDLFIR[63]
     *  SCOM Satellite Error
     */
    (rOMIDLFIR, bit(63)) ? defaultMaskedError;

};

 ##############################################################################
 #                                                                            #
 #    #                                  ###                                  #
 #   # #    ##  ##### ###  ###  #   #   #   # #     #    ###   ###  ###  ###  #
 #  #   #  #  #   #    #  #   # ##  #   #     #    # #  #     #     #   #     #
 # ####### #      #    #  #   # # # #   #     #   #####  ###   ###  ##   ###  #
 # #     # #  #   #    #  #   # #  ##   #   # #   #   #     #     # #       # #
 # #     #  ##    #   ###  ###  #   #    ###  ### #   #  ###   ###  ###  ###  #
 #                                                                            #
 ##############################################################################

# Include the actions defined for this target
.include "p9_common_actions.rule";
.include "axone_omic_actions.rule";