# IBM_PROLOG_BEGIN_TAG
# This is an automatically generated prolog.
#
# $Source: src/usr/diag/prdf/common/plat/axone/axone_mi.rule $
#
# OpenPOWER HostBoot Project
#
# Contributors Listed Below - COPYRIGHT 2018,2019
# [+] International Business Machines Corp.
#
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
# implied. See the License for the specific language governing
# permissions and limitations under the License.
#
# IBM_PROLOG_END_TAG

chip axone_mi
{
    name        "AXONE MI target";
    targettype  TYPE_MI;
    sigoff      0x0000;
    dump        DUMP_CONTENT_HW;
    scomlen     64;

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    ############################################################################
    # P9 MI target MCFIR
    ############################################################################

    register MCFIR
    {
        name        "P9 MI target MCFIR";
        scomaddr    0x05010800;
        reset       (&, 0x05010801);
        mask        (|, 0x05010805);
        capture     group default;
        capture     group MirrorConfig;
    };

    register MCFIR_MASK
    {
        name        "P9 MI target MCFIR MASK";
        scomaddr    0x05010803;
        capture     group default;
        capture     group MirrorConfig;
    };

    register MCFIR_ACT0
    {
        name        "P9 MI target MCFIR ACT0";
        scomaddr    0x05010806;
        capture     group default;
        capture     req nonzero("MCFIR");
        capture     group MirrorConfig;
    };

    register MCFIR_ACT1
    {
        name        "P9 MI target MCFIR ACT1";
        scomaddr    0x05010807;
        capture     group default;
        capture     req nonzero("MCFIR");
        capture     group MirrorConfig;
    };

# Include registers not defined by the xml
.include "axone_mi_regs.rule";

};

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 ##############################################################################

################################################################################
# Summary for MI
################################################################################

rule rMI
{
  CHECK_STOP:
    summary( 0, rMCFIR );

  RECOVERABLE:
    summary( 0, rMCFIR );

  UNIT_CS:
    summary( 0, rMCFIR );

  HOST_ATTN:
    summary( 0, rMCFIR );

};

group gMI attntype CHECK_STOP, RECOVERABLE, UNIT_CS, HOST_ATTN
    filter singlebit
{
    (rMI, bit(0)) ? analyzeMCFIR;
};

################################################################################
# P9 MI target MCFIR
################################################################################

rule rMCFIR
{
  CHECK_STOP:
    MCFIR & ~MCFIR_MASK & ~MCFIR_ACT0 & ~MCFIR_ACT1;
  RECOVERABLE:
    MCFIR & ~MCFIR_MASK & ~MCFIR_ACT0 &  MCFIR_ACT1;
  HOST_ATTN:
    MCFIR & ~MCFIR_MASK &  MCFIR_ACT0 & ~MCFIR_ACT1;
  UNIT_CS:
    MCFIR & ~MCFIR_MASK &  MCFIR_ACT0 &  MCFIR_ACT1;
};

group gMCFIR
    filter singlebit,
           cs_root_cause
{
    /** MCFIR[0]
     *  MC internal recoverable error
     */
    (rMCFIR, bit(0)) ? self_th_1;

    /** MCFIR[1]
     *  MC internal non recoverable error
     */
    (rMCFIR, bit(1)) ? parent_proc_th_1;

    /** MCFIR[2]
     *  Powerbus protocol error
     */
    (rMCFIR, bit(2)) ? level2_th_1;

    /** MCFIR[3]
     *  Inband bar hit with incorrect ttype
     */
    (rMCFIR, bit(3)) ? level2_M_self_L_th_1;

    /** MCFIR[4]
     *  Multiple bar
     */
    (rMCFIR, bit(4)) ? self_th_1;

    /** MCFIR[5]
     *  PB write ECC syndrome NE0
     */
    (rMCFIR, bit(5)) ? defaultMaskedError;

    /** MCFIR[6:7]
     *  reserved
     */
    (rMCFIR, bit(6|7)) ? defaultMaskedError;

    /** MCFIR[8]
     *  Command list timeout
     */
    (rMCFIR, bit(8)) ? threshold_and_mask_level2;

    /** MCFIR[9:10]
     *  reserved
     */
    (rMCFIR, bit(9|10)) ? defaultMaskedError;

    /** MCFIR[11]
     *  MCS wat0 event
     */
    (rMCFIR, bit(11)) ? defaultMaskedError;

    /** MCFIR[12]
     *  MCS wat1 event
     */
    (rMCFIR, bit(12)) ? defaultMaskedError;

    /** MCFIR[13]
     *  MCS wat2 event
     */
    (rMCFIR, bit(13)) ? defaultMaskedError;

    /** MCFIR[14]
     *  MCS wat3 event
     */
    (rMCFIR, bit(14)) ? defaultMaskedError;

    /** MCFIR[15:16]
     *  reserved
     */
    (rMCFIR, bit(15|16)) ? defaultMaskedError;

    /** MCFIR[17]
     *  WAT debug config reg error
     */
    (rMCFIR, bit(17)) ? defaultMaskedError;

    /** MCFIR[18:21]
     *  reserved
     */
    (rMCFIR, bit(18|19|20|21)) ? defaultMaskedError;

    /** MCFIR[22]
     *  Invalid SMF access
     */
    (rMCFIR, bit(22)) ? defaultMaskedError;

    /** MCFIR[23]
     *  reserved
     */
    (rMCFIR, bit(23)) ? defaultMaskedError;

    /** MCFIR[24]
     *  Internal SCOM error
     */
    (rMCFIR, bit(24)) ? defaultMaskedError;

    /** MCFIR[25]
     *  Internal SCOM error clone
     */
    (rMCFIR, bit(25)) ? defaultMaskedError;

};

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 ##############################################################################

# Include the actions defined for this target
.include "p9_common_actions.rule";
.include "axone_mi_actions.rule";