# IBM_PROLOG_BEGIN_TAG
# This is an automatically generated prolog.
#
# $Source: src/usr/diag/prdf/common/plat/axone/axone_eq.rule $
#
# OpenPOWER HostBoot Project
#
# Contributors Listed Below - COPYRIGHT 2018
# [+] International Business Machines Corp.
#
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
# implied. See the License for the specific language governing
# permissions and limitations under the License.
#
# IBM_PROLOG_END_TAG

chip axone_eq
{
    name        "AXONE EQ target";
    targettype  TYPE_EQ;
    sigoff      0x0000;
    dump        DUMP_CONTENT_HW;
    scomlen     64;

 #############################################################################
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 #############################################################################

    ############################################################################
    # EQ Chiplet FIR
    ############################################################################

    register EQ_CHIPLET_CS_FIR
    {
        name        "EQ Chiplet Checkstop FIR";
        scomaddr    0x10040000;
        capture     group default;
    };

    register EQ_CHIPLET_RE_FIR
    {
        name        "EQ Chiplet Recoverable FIR";
        scomaddr    0x10040001;
        capture     group default;
    };

    register EQ_CHIPLET_FIR_MASK
    {
        name        "EQ Chiplet FIR MASK";
        scomaddr    0x10040002;
        capture     group default;
    };

    ############################################################################
    # P9 EQ target EQ_LFIR
    ############################################################################

    register EQ_LFIR
    {
        name        "P9 EQ target EQ_LFIR";
        scomaddr    0x1004000a;
        reset       (&, 0x1004000b);
        mask        (|, 0x1004000f);
        capture     group default;
    };

    register EQ_LFIR_MASK
    {
        name        "P9 EQ target EQ_LFIR MASK";
        scomaddr    0x1004000d;
        capture     group default;
    };

    register EQ_LFIR_ACT0
    {
        name        "P9 EQ target EQ_LFIR ACT0";
        scomaddr    0x10040010;
        capture     group default;
        capture     req nonzero("EQ_LFIR");
    };

    register EQ_LFIR_ACT1
    {
        name        "P9 EQ target EQ_LFIR ACT1";
        scomaddr    0x10040011;
        capture     group default;
        capture     req nonzero("EQ_LFIR");
    };

# Include registers not defined by the xml
.include "p9_common_eq_regs.rule";

};

 ##############################################################################
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 # #   #  ###  #### #####  ###  #    #     #  ##    #   ###  ###  #   #  ###  #
 #                                                                            #
 ##############################################################################

################################################################################
# EQ Chiplet FIR
################################################################################

rule rEQ_CHIPLET_FIR
{
  CHECK_STOP:
     EQ_CHIPLET_CS_FIR       & ~EQ_CHIPLET_FIR_MASK & `1fffffffffffffff`;
  RECOVERABLE:
    (EQ_CHIPLET_RE_FIR >> 2) & ~EQ_CHIPLET_FIR_MASK & `1fffffffffffffff`;
};

group gEQ_CHIPLET_FIR attntype CHECK_STOP, RECOVERABLE
    filter singlebit
{
    /** EQ_CHIPLET_FIR[3]
     *  Attention from EQ_LFIR
     */
    (rEQ_CHIPLET_FIR, bit(3)) ? analyzeEQ_LFIR;

    /** EQ_CHIPLET_FIR[4]
     *  Attention from L3FIR 0
     */
    (rEQ_CHIPLET_FIR, bit(4)) ? analyzeConnectedEX0;

    /** EQ_CHIPLET_FIR[5]
     *  Attention from L3FIR 1
     */
    (rEQ_CHIPLET_FIR, bit(5)) ? analyzeConnectedEX1;

    /** EQ_CHIPLET_FIR[6]
     *  Attention from L2FIR 0
     */
    (rEQ_CHIPLET_FIR, bit(6)) ? analyzeConnectedEX0;

    /** EQ_CHIPLET_FIR[7]
     *  Attention from L2FIR 1
     */
    (rEQ_CHIPLET_FIR, bit(7)) ? analyzeConnectedEX1;

    /** EQ_CHIPLET_FIR[8]
     *  Attention from NCUFIR 0
     */
    (rEQ_CHIPLET_FIR, bit(8)) ? analyzeConnectedEX0;

    /** EQ_CHIPLET_FIR[9]
     *  Attention from NCUFIR 1
     */
    (rEQ_CHIPLET_FIR, bit(9)) ? analyzeConnectedEX1;

    /** EQ_CHIPLET_FIR[11]
     *  Attention from CMEFIR 0
     */
    (rEQ_CHIPLET_FIR, bit(11)) ? analyzeConnectedEX0;

    /** EQ_CHIPLET_FIR[12]
     *  Attention from CMEFIR 1
     */
    (rEQ_CHIPLET_FIR, bit(12)) ? analyzeConnectedEX1;

};

################################################################################
# P9 EQ target EQ_LFIR
################################################################################

rule rEQ_LFIR
{
  CHECK_STOP:
    EQ_LFIR & ~EQ_LFIR_MASK & ~EQ_LFIR_ACT0 & ~EQ_LFIR_ACT1;
  RECOVERABLE:
    EQ_LFIR & ~EQ_LFIR_MASK & ~EQ_LFIR_ACT0 &  EQ_LFIR_ACT1;
};

group gEQ_LFIR
    filter singlebit,
           cs_root_cause
{
    /** EQ_LFIR[0]
     *  CFIR internal parity error
     */
    (rEQ_LFIR, bit(0)) ? self_th_32perDay;

    /** EQ_LFIR[1]
     *  Chiplet Control Reg: PCB Access Error
     */
    (rEQ_LFIR, bit(1)) ? self_th_32perDay;

    /** EQ_LFIR[2]
     *  Clock Controller: PCB Access Error
     */
    (rEQ_LFIR, bit(2)) ? self_th_32perDay;

    /** EQ_LFIR[3]
     *  Clock Controller: Summarized Error
     */
    (rEQ_LFIR, bit(3)) ? self_th_32perDay;

    /** EQ_LFIR[4]
     *  PSCOM Logic: PCB Access Error
     */
    (rEQ_LFIR, bit(4)) ? defaultMaskedError;

    /** EQ_LFIR[5]
     *  PSCOM Logic: Summarized internal errors
     */
    (rEQ_LFIR, bit(5)) ? defaultMaskedError;

    /** EQ_LFIR[6]
     *  Therm Logic: Summarized internal errors
     */
    (rEQ_LFIR, bit(6)) ? defaultMaskedError;

    /** EQ_LFIR[7]
     *  Therm Logic: PCB Access Error
     */
    (rEQ_LFIR, bit(7)) ? defaultMaskedError;

    /** EQ_LFIR[8]
     *  Therm Logic: Temperature critical trip
     */
    (rEQ_LFIR, bit(8)) ? defaultMaskedError;

    /** EQ_LFIR[9]
     *  Therm Logic: Temperature fatal trip
     */
    (rEQ_LFIR, bit(9)) ? defaultMaskedError;

    /** EQ_LFIR[10]
     *  UNUSED in P9
     */
    (rEQ_LFIR, bit(10)) ? defaultMaskedError;

    /** EQ_LFIR[11]
     *  Debug Logic: Scom Satellite Error
     */
    (rEQ_LFIR, bit(11)) ? defaultMaskedError;

    /** EQ_LFIR[12]
     *  Scom Satellite Error - L3 Trace0
     */
    (rEQ_LFIR, bit(12)) ? defaultMaskedError;

    /** EQ_LFIR[13]
     *  Scom Satellite Error - L3 Trace0
     */
    (rEQ_LFIR, bit(13)) ? defaultMaskedError;

    /** EQ_LFIR[14]
     *  Scom Satellite Error - L3 Trace1
     */
    (rEQ_LFIR, bit(14)) ? defaultMaskedError;

    /** EQ_LFIR[15]
     *  Scom Satellite Error - L3 Trace1
     */
    (rEQ_LFIR, bit(15)) ? defaultMaskedError;

    /** EQ_LFIR[16]
     *  Scom Satellite Error - L20 Trace0
     */
    (rEQ_LFIR, bit(16)) ? defaultMaskedError;

    /** EQ_LFIR[17]
     *  Scom Satellite Error - L20 Trace0
     */
    (rEQ_LFIR, bit(17)) ? defaultMaskedError;

    /** EQ_LFIR[18]
     *  Scom Satellite Error - L20 Trace1
     */
    (rEQ_LFIR, bit(18)) ? defaultMaskedError;

    /** EQ_LFIR[19]
     *  Scom Satellite Error - L20 Trace1
     */
    (rEQ_LFIR, bit(19)) ? defaultMaskedError;

    /** EQ_LFIR[20]
     *  Duty Cycle Adjust Logic error: cache clk
     */
    (rEQ_LFIR, bit(20)) ? self_th_32perDay;

    /** EQ_LFIR[21]
     *  Duty Cycle Adjust Logic error: ex00_c0
     */
    (rEQ_LFIR, bit(21)) ? self_th_32perDay;

    /** EQ_LFIR[22]
     *  Duty Cycle Adjust error :  ex00_c1
     */
    (rEQ_LFIR, bit(22)) ? self_th_32perDay;

    /** EQ_LFIR[23]
     *  Duty Cycle Adjust error : ex00_l2
     */
    (rEQ_LFIR, bit(23)) ? self_th_32perDay;

    /** EQ_LFIR[24]
     *  Duty Cycle Adjust Logic error :  ex01_c0
     */
    (rEQ_LFIR, bit(24)) ? self_th_32perDay;

    /** EQ_LFIR[25]
     *  Duty Cycle Adjust Logic error : ex01_c1
     */
    (rEQ_LFIR, bit(25)) ? self_th_32perDay;

    /** EQ_LFIR[26]
     *  Duty Cycle Adjust Logic error : ex01_l2
     */
    (rEQ_LFIR, bit(26)) ? self_th_32perDay;

    /** EQ_LFIR[27]
     *  Skew Adjust Logic Data or deskew error
     */
    (rEQ_LFIR, bit(27)) ? self_th_32perDay;

    /** EQ_LFIR[28:40]
     *  spare
     */
    (rEQ_LFIR, bit(28|29|30|31|32|33|34|35|36|37|38|39|40)) ? defaultMaskedError;

    /** EQ_LFIR[41]
     *  Malfunction Alert or Local Checkstop
     */
    (rEQ_LFIR, bit(41)) ? defaultMaskedError;

};

 ##############################################################################
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 # #     #  ##    #   ###  ###  #   #    ###  ### #   #  ###   ###  ###  ###  #
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 ##############################################################################

# Include the actions defined for this target
.include "p9_common_actions.rule";
.include "p9_common_eq_actions.rule";