ATTR_MEM_SI_SIGNATURE_HASH TARGET_TYPE_MEM_PORT Hash Signature for SI settings from SPD. The hash signature is 32bits for 256 bytes of data. uint32 si_signature_hash ATTR_MEM_SI_DIMM_RCD_IBT_CA TARGET_TYPE_MEM_PORT Array[DIMM] Register Clock Driver, Input Bus Termination for Command/Address in tens of Ohms. uint8 IBT_OFF = 0, IBT_100 = 10, IBT_150 = 15, IBT_300 = 30 ohm si_dimm_rcd_ibt_ca 2 ATTR_MEM_SI_DIMM_RCD_IBT_CKE TARGET_TYPE_MEM_PORT Array[DIMM] Register Clock Driver, Input Bus Termination for Clock Enable in tens of Ohms. uint8 IBT_OFF = 0, IBT_100 = 10, IBT_150 = 15, IBT_300 = 30 ohm si_dimm_rcd_ibt_cke 2 ATTR_MEM_SI_DIMM_RCD_IBT_CS TARGET_TYPE_MEM_PORT Array[DIMM] Register Clock Driver, Input Bus Termination for Chip Select in tens of Ohms. uint8 IBT_OFF = 0, IBT_100 = 10, IBT_150 = 15, IBT_300 = 30 ohm si_dimm_rcd_ibt_cs 2 ATTR_MEM_SI_DIMM_RCD_IBT_ODT TARGET_TYPE_MEM_PORT Array[DIMM] Register Clock Driver, Input Bus Termination for On Die Termination in tens of Ohms. uint8 IBT_OFF = 0, IBT_100 = 10, IBT_150 = 15, IBT_300 = 30 ohm si_dimm_rcd_ibt_odt 2 ATTR_MEM_SI_DRAM_DRV_IMP_DQ_DQS TARGET_TYPE_MEM_PORT Array[DIMM][RANK] DQ and DQS Drive Impedance. uint8 DISABLE = 0, OHM34 = 34, OHM48 = 48 ohm si_dram_drv_imp_dq_dqs 2 4 ATTR_MEM_SI_DRAM_PREAMBLE TARGET_TYPE_MEM_PORT Array[DIMM][RANK] Number of clocks used for read/write preamble. Calibration only uses 1 nCK preamble (DEFAULT). Mainline has both 1 nCK and 2 nCK preamble option. The value of "0" means 1 nCK preamble, the value of "1" means 2 nCK preamble. Bit 3 for READ preamble, and Bit 7 for WRITE preamble. E.g. 0b00010001 means 2 nCK preamble for both READ and WRITE uint8 READ_PREAMBLE_BIT = 3, WRITE_PREAMBLE_BIT = 7 nCK si_dram_preamble 2 4 ATTR_MEM_SI_DRAM_RTT_NOM TARGET_TYPE_MEM_PORT Array[DIMM][RANK] DRAM side Nominal Termination Resistance in Ohms. uint8 DISABLE = 0, OHM34 = 34, OHM40 = 40, OHM60 = 60, OHM80 = 80, OHM120 = 120, OHM240 = 240 ohm si_dram_rtt_nom 2 4 ATTR_MEM_SI_DRAM_RTT_PARK TARGET_TYPE_MEM_PORT Array[DIMM][RANK] DRAM side Park Termination Resistance in Ohms. uint8 DISABLE = 0, OHM34 = 34, OHM40 = 40, OHM48 = 48, OHM60 = 60, OHM80 = 80, OHM120 = 120, OHM240 = 240 ohm si_dram_rtt_park 2 4 ATTR_MEM_SI_DRAM_RTT_WR TARGET_TYPE_MEM_PORT Array[DIMM][RANK] DRAM side Write Termination Resistance in Ohms. uint8 DISABLE = 0, OHM80 = 80, OHM120 = 120, OHM240 = 240 ohm si_dram_rtt_wr 2 4 ATTR_MEM_SI_GEARDOWN_MODE TARGET_TYPE_MEM_PORT ARRAY[DIMM][RANK] Gear Down Mode. This is for DDR4 MRS3. Each memory channel will have a value. uint8 HALF=0, QUARTER=1 2 4 si_geardown_mode ATTR_MEM_SI_MC_DRV_DQ_DQS TARGET_TYPE_MEM_PORT Array[DIMM][RANK] Tx drive impedance for DQ/DQS of all ranks in ohms uint8 si_mc_drv_dq_dqs 2 4 ATTR_MEM_SI_MC_RCV_EQ_DQ_DQS TARGET_TYPE_MEM_PORT Array[DIMM][RANK] Memory Controller side Receiver Equalization for Data and Data Strobe Lines. uint8 DISABLE = 0, ENABLE = 1 si_mc_rcv_eq_dq_dqs 2 4 ATTR_MEM_SI_MC_DRV_EQ_DQ_DQS TARGET_TYPE_MEM_PORT Array[DIMM][RANK] Memory Controller side Drive Equalization for Data and Data Strobe Lines. uint8 DISABLE = 0, FFE = 1 si_mc_drv_eq_dq_dqs 2 4 ATTR_MEM_SI_MC_DRV_IMP_CLK TARGET_TYPE_MEM_PORT Array[DIMM][RANK] Memory Controller side Drive Impedance for Clock in Ohms. uint8 DISABLE = 0, OHM_20 = 20, OHM_24 = 24, OHM_30 = 30, OHM_40 = 40, OHM_60 = 60, OHM_120 = 120 ohm si_mc_drv_imp_clk 2 4 ATTR_MEM_SI_MC_DRV_IMP_CMD_ADDR TARGET_TYPE_MEM_PORT Array[DIMM][RANK] Memory Controller side Drive Impedance for Address, Bank Address, Bank Group and Activate Lines in Ohms. uint8 DISABLE = 0, OHM_20 = 20, OHM_24 = 24, OHM_30 = 30, OHM_40 = 40, OHM_60 = 60, OHM_120 = 120 ohm si_mc_drv_imp_cmd_addr 2 4 ATTR_MEM_SI_MC_DRV_IMP_CNTL TARGET_TYPE_MEM_PORT Array[DIMM][RANK] Memory Controller side Drive Impedance for Clock Enable, ODT, Parity, and Reset Lines in Ohms. uint8 DISABLE = 0 ohm si_mc_drv_imp_cntl 2 4 ATTR_MEM_SI_MC_DRV_IMP_CSCID TARGET_TYPE_MEM_PORT Array[DIMM][RANK] Memory Controller side Drive Impedance for Chip Select and Chip ID Lines in Ohms. uint8 DISABLE = 0 ohm si_mc_drv_imp_cscid 2 4 ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN TARGET_TYPE_MEM_PORT Array[DIMM][RANK] Memory Controller side Drive Impedance Pull Down for Data and Data Strobe Lines in Ohms. uint16 DISABLE = 0, OHM_28 = 28, OHM_30 = 30, OHM_32 = 32, OHM_34 = 34, OHM_36 = 36, OHM_40 = 40, OHM_43 = 43, OHM_48 = 48, OHM_53 = 53, OHM_60 = 60, OHM_68 = 68, OHM_80 = 80, OHM_96 = 96, OHM_120 = 120, OHM_160 = 160, OHM_240 = 240, OHM_480 = 480 ohm si_mc_drv_imp_dq_dqs_pull_down 2 4 ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_UP TARGET_TYPE_MEM_PORT Array[DIMM][RANK] Memory Controller side Drive Impedance Pull Up for Data and Data Strobe Lines in Ohms. uint16 DISABLE = 0, OHM_28 = 28, OHM_30 = 30, OHM_32 = 32, OHM_34 = 34, OHM_36 = 36, OHM_40 = 40, OHM_43 = 43, OHM_48 = 48, OHM_53 = 53, OHM_60 = 60, OHM_68 = 68, OHM_80 = 80, OHM_96 = 96, OHM_120 = 120, OHM_160 = 160, OHM_240 = 240, OHM_480 = 480 ohm si_mc_drv_imp_dq_dqs_pull_up 2 4 ATTR_MEM_SI_MC_DRV_SLEW_RATE_CLK TARGET_TYPE_MEM_PORT Array[DIMM][RANK] Memory Controller side Drive Slew Rate for Clock in Ohms. uint8 DISABLE = 0 ohm si_mc_drv_slew_rate_clk 2 4 ATTR_MEM_SI_MC_DRV_SLEW_RATE_CMD_ADDR TARGET_TYPE_MEM_PORT Array[DIMM][RANK] Memory Controller side Drive Slew Rate for Address, Bank Address, Bank Group and Activate Lines in Ohms. uint8 DISABLE = 0 ohm si_mc_drv_slew_rate_cmd_addr 2 4 ATTR_MEM_SI_MC_DRV_SLEW_RATE_CNTL TARGET_TYPE_MEM_PORT Array[DIMM][RANK] Memory Controller side Drive Slew Rate for Clock Enable, ODT, Parity, and Reset Lines in Ohms. uint8 DISABLE = 0 ohm si_mc_drv_slew_rate_cntl 2 4 ATTR_MEM_SI_MC_DRV_SLEW_RATE_CSCID TARGET_TYPE_MEM_PORT Array[DIMM][RANK] Memory Controller side Drive Slew Rate for Chip Select and Chip ID Lines in Ohms. uint8 DISABLE = 0 ohm si_mc_drv_slew_rate_cscid 2 4 ATTR_MEM_SI_MC_DRV_SLEW_RATE_DQ_DQS TARGET_TYPE_MEM_PORT Array[DIMM][RANK] Memory Controller side Drive Slew Rate for Data and Data Strobe Lines in Ohms. uint8 DISABLE = 0 ohm si_mc_drv_slew_rate_dq_dqs 2 4 ATTR_MEM_SI_MC_RCV_IMP_ALERT_N TARGET_TYPE_MEM_PORT Memory Controller side Receiver Impedance. Alert_N line in Ohms. uint8 DISABLE = 0, OHM_40 = 40, OHM_48 = 48, OHM_60 = 60, OHM_80 = 80, OHM_120 = 120, OHM_240 = 240 ohm si_mc_rcv_imp_alert_n 2 4 ATTR_MEM_SI_MC_RCV_IMP_DQ_DQS TARGET_TYPE_MEM_PORT Array[DIMM][RANK] Memory Controller side Receiver Impedance. Data and Data Strobe Lines in Ohms. uint8 DISABLE = 0, OHM_40 = 40, OHM_60 = 60, OHM_80 = 80, OHM_120 = 120, OHM_240 = 240 ohm si_mc_rcv_imp_dq_dqs 2 4 ATTR_MEM_SI_ODT_RD TARGET_TYPE_MEM_PORT Array[DIMM][RANK] READ, On Die Termination triggering bitmap. Use bitmap to determine which ODT to fire for the designated rank. The bits in 8 bit field are [DIMM0 ODT0][DIMM0 ODT1][DIMM0 ODT2][DIMM0 ODT3][DIMM1 ODT0][DIMM1 ODT1][DIMM1 ODT2][DIMM1 ODT3] uint8 si_odt_rd 2 4 ATTR_MEM_SI_ODT_WR TARGET_TYPE_MEM_PORT Array[DIMM][RANK] WRITE, On Die Termination triggering bitmap. Use bitmap to determine which ODT to fire for the designated rank. The bits in 8 bit field are [DIMM0 ODT0][DIMM0 ODT1][DIMM0 ODT2][DIMM0 ODT3][DIMM1 ODT0][DIMM1 ODT1][DIMM1 ODT2][DIMM1 ODT3] uint8 si_odt_wr 2 4 ATTR_MEM_SI_VREF_DRAM_WR TARGET_TYPE_MEM_PORT DRAM side Write Vref setting for DDR4. Bit encode is 01234567. Bit 0 is unused. Bit 1 is the Range. Bits 2-7 is the Value. Refer to the VrefDQ Training Table in JEDEC. uint8 si_vref_dram_wr ATTR_MEM_SI_VREF_MC_RD TARGET_TYPE_MEM_PORT Memory Controller side Read Vref setting. Dividing by 1000 gives you percentage of Vdd. Disable = 0, defined as no HW adjustment or Vdd/2 if possible. uint32 DISABLE = 0 percent of Vdd si_vref_mc_rd ATTR_MEM_SI_WINDAGE_RD_CTR TARGET_TYPE_MEM_PORT Derived from calibration/characterization of read centering. Number of windage offset in units of pico-seconds[ps]. Default is 0 for no windage adjustment. Specification of the value in this file is 2's compliment hex int16 signed si_windage_rd_ctr