ATTR_MEM_EFF_DRAM_GEN TARGET_TYPE_MEM_PORT ARRAY[DIMM] DRAM Device Type. Decodes SPD byte 2. Generation of memory: DDR3, DDR4. uint8 EMPTY = 0, DDR3 = 1, DDR4 = 2 2 dram_gen ATTR_MEM_EFF_DIMM_TYPE TARGET_TYPE_MEM_PORT ARRAY[DIMM] Base Module Type. Decodes SPD Byte 3 (bits 3~0). Type of DIMM: RDIMM, UDIMM, LRDIMM as specified by the JEDEC standard. uint8 EMPTY = 0, RDIMM = 1, UDIMM = 2, LRDIMM = 3, DDIMM = 4, MDS_LRDIMM = 5, MDS = 6 2 dimm_type ATTR_MEM_EFF_HYBRID_MEMORY_TYPE TARGET_TYPE_MEM_PORT ARRAY[DIMM] Hybrid Media. Decodes SPD Byte 3 (bits 6~4) uint8 NONE = 0, NVDIMM = 1 2 hybrid_memory_type ATTR_MEM_EFF_HYBRID TARGET_TYPE_MEM_PORT ARRAY[DIMM] Hybrid. Decodes SPD Byte 3 (bit 7) uint8 NOT_HYBRID = 0, IS_HYBRID= 1 2 hybrid ATTR_MEM_EFF_HOST_TO_DDR_SPEED_RATIO TARGET_TYPE_MEM_PORT ARRAY[DIMM] OMI to DDR frequency ratio uint8 1_TO_1 = 1, 2_TO_1 = 2, 4_TO_1 = 4, 8_TO_1 = 8, 16_TO_1 = 16, 32_TO_1 = 32, 64_TO_1 = 64, 128_TO_1 = 128 8 2 ratio host_to_ddr_speed_ratio ATTR_MEM_EFF_DRAM_DENSITY TARGET_TYPE_MEM_PORT ARRAY[DIMM] DRAM Density. Decodes SPD Byte 4 (bits 3~0). Total SDRAM capacity per die. For multi-die stacks (DDP, QDP, or 3DS), this represents the capacity of each DRAM die in the stack. uint8 4G = 4, 8G = 8, 16G = 16 2 Gb dram_density ATTR_MEM_EFF_DRAM_BANK_BITS TARGET_TYPE_MEM_PORT ARRAY[DIMM] Number of DRAM bank address bits. Actual number of banks is 2^N, where N is the number of bank address bits. Decodes SPD Byte 4 (bits 5~4). uint8 2 dram_bank_bits ATTR_MEM_EFF_DRAM_BANK_GROUP_BITS TARGET_TYPE_MEM_PORT ARRAY[DIMM] Bank Groups Bits. Decoded SPD Byte 4 (bits 7~6). Actual number of bank groups is 2^N, where N is the number of bank address bits. This value represents the number of bank groups into which the memory array is divided. uint8 2 dram_bank_group_bits ATTR_MEM_EFF_DRAM_COLUMN_BITS TARGET_TYPE_MEM_PORT ARRAY[DIMM] Column Address Bits. Decoded SPD Byte 5 (bits 2~0). Actual number of DRAM columns is 2^N, where N is the number of column address bits uint8 NUM10 = 10 2 dram_column_bits ATTR_MEM_EFF_DRAM_ROW_BITS TARGET_TYPE_MEM_PORT ARRAY[DIMM] Row Address Bits. Decodes Byte 5 (bits 5~3). Number of DRAM column address bits. Actual number of DRAM rows is 2^N, where N is the number of row address bits uint8 NUM14 = 14, NUM15 = 15, NUM16 = 16, NUM17 = 17, NUM18 = 18 2 dram_row_bits ATTR_MEM_EFF_PRIM_DIE_COUNT TARGET_TYPE_MEM_PORT ARRAY[DIMM] Primary SDRAM Die Count. Decodes Byte 6 (bits 6~4). uint8 D1 = 1, D2 = 2, D3 = 3, D4 = 4, D5 = 5, D6 = 6, D7 = 7, D8 = 8 2 prim_die_count ATTR_MEM_EFF_PRIM_STACK_TYPE TARGET_TYPE_MEM_PORT ARRAY[DIMM] Primary SDRAM Package Type (bits 1~0). Decodes Byte 6. This byte defines the primary set of SDRAMs. Monolithic = SPD, Multi-load stack = DDP/QDP, Single-load stack = 3DS uint8 SDP = 0, DDP_QDP = 1, 3DS = 2 2 prim_stack_type ATTR_MEM_EFF_PRIM_BUS_WIDTH TARGET_TYPE_MEM_PORT ARRAY[DIMM] Primary bus with (bits 1~0). Decodes Byte 13. uint8 8_BITS = 8, 16_BITS = 16, 32_BITS = 32, 64_BITS = 64 2 prim_bus_width ATTR_MEM_EFF_DRAM_PPR TARGET_TYPE_MEM_PORT ARRAY[DIMM] Post Package Repair. Used in various locations and is evaluated in mss_eff_cnfg. uint8 NOT_SUPPORTED = 0, SUPPORTED = 1 2 dram_ppr ATTR_MEM_EFF_DRAM_SOFT_PPR TARGET_TYPE_MEM_PORT ARRAY[DIMM] Soft Post Package Repair. Used in various locations and is evaluated in mss_eff_cnfg. uint8 NOT_SUPPORTED = 0, SUPPORTED = 1 2 dram_soft_ppr ATTR_MEM_EFF_DRAM_TRCD TARGET_TYPE_MEM_PORT Minimum RAS to CAS Delay Time in nck (number of clock cyles). Decodes SPD byte 25 (7~0) and byte 112 (7~0). Each memory channel will have a value. uint8 nck dram_trcd ATTR_MEM_EFF_DRAM_TRP TARGET_TYPE_MEM_PORT SDRAM Row Precharge Delay Time in nck (number of clock cycles). Decodes SPD byte 26 (bits 7~0) and byte 121 (bits 7~0). Each memory channel will have a value. uint8 nck dram_trp ATTR_MEM_EFF_DRAM_TRAS TARGET_TYPE_MEM_PORT Minimum Active to Precharge Delay Time in nck (number of clock cycles). Decodes SPD byte 27 (bits 3~0) and byte 28 (7~0). Each memory channel will have a value. creator: mss_eff_cnfg_timing uint8 nck dram_tras ATTR_MEM_EFF_DRAM_TRC TARGET_TYPE_MEM_PORT Minimum Active to Active/Refresh Delay in nck (number of clock cyles). Decodes SPD byte 27 (bits 7~4), byte 29 (bits 7~0), and byte 120. Each memory channel will have a value. uint8 nck dram_trc ATTR_MEM_EFF_DRAM_TRFC TARGET_TYPE_MEM_PORT DDR4 Spec defined as Refresh Cycle Time (tRFC). SPD Spec refers it to the Minimum Refresh Recovery Delay Time. In nck (number of clock cyles). Decodes SPD byte 31 (bits 15~8) and byte 30 (bits 7~0) for tRFC1. Decodes SPD byte 33 (bits 15~8) and byte 32 (bits 7~0) for tRFC2. Decodes SPD byte 35 (bits 15~8) and byte 34 (bits 7~0) for tRFC4. Selected tRFC value depends on MRW attribute that selects refresh mode. For 3DS, The tRFC time to the same logical rank is defined as tRFC_slr and is specificed as the value as for a monolithic DDR4 SDRAM of equivalent density. uint16 nck dram_trfc ATTR_MEM_EFF_DRAM_TFAW TARGET_TYPE_MEM_PORT Minimum Four Activate Window Delay Time in nck (number of clock cycles). Decodes SPD byte 36 (bits 3~0) and byte 37 (bits 7~0). For 3DS, tFAW time to the same logical rank is defined as tFAW_slr_x4 or tFAW_slr_x8 (for x4 and x8 devices only) and specificed as the value as for a monolithic DDR4 SDRAM equivalent density. Each memory channel will have a value. uint8 nck dram_tfaw ATTR_MEM_EFF_DRAM_TRRD_S TARGET_TYPE_MEM_PORT Minimum Activate to Activate Delay Time, different bank group in nck (number of clock cycles). Decodes SPD byte 38 (bits 7~0). For 3DS, The tRRD_S time to a different bank group in the same logical rank is defined as tRRD_slr and is specificed as the value as for a monolithic DDR4 SDRAM of equivalent density. Each memory channel will have a value. uint8 nck dram_trrd_s ATTR_MEM_EFF_DRAM_TRRD_L TARGET_TYPE_MEM_PORT Minimum Activate to Activate Delay Time, same bank group in nck (number of clock cycles). Decodes SPD byte 39 (bits 7~0). For 3DS, The tRRD_L time to the same bank group in the same logical rank is defined as tRRD_L_slr and is specificed as the value as for a monolithic DDR4 SDRAM of equivalent density. Each memory channel will have a value. uint8 nck dram_trrd_l ATTR_MEM_EFF_DRAM_TRRD_DLR TARGET_TYPE_MEM_PORT Minimum Activate to Activate Delay Time (different logical ranks) in nck (number of clock cycles). For 3DS, The tRRD_S time to a different logical rank is defined as tRRD_dlr. Each memory channel will have a value. uint8 nck dram_trrd_dlr ATTR_MEM_EFF_DRAM_TCCD_L TARGET_TYPE_MEM_PORT Minimum CAS to CAS Delay Time, same bank group in nck (number of clock cycles). Decodes SPD byte 40 (bits 7~0) and byte 117 (bits 7~0). This is for DDR4 MRS6. Each memory channel will have a value. uint8 4NCK = 4, 5NCK = 5, 6NCK = 6, 7NCK = 7, 8NCK = 8 nck dram_tccd_l ATTR_MEM_EFF_DRAM_TWR TARGET_TYPE_MEM_PORT Minimum Write Recovery Time. Decodes SPD byte 41 (bits 3~0) and byte 42 (bits 7~0). Each memory channel will have a value. uint8 nck dram_twr ATTR_MEM_EFF_DRAM_TWTR_S TARGET_TYPE_MEM_PORT Minimum Write to Read Time, different bank group in nck (number of clock cycles). Decodes SPD byte 43 (3~0) and byte 44 (bits 7~0). Each memory channel will have a value. uint8 nck dram_twtr_s ATTR_MEM_EFF_DRAM_TWTR_L TARGET_TYPE_MEM_PORT Minimum Write to Read Time, same bank group in nck (number of clock cycles). Decodes byte 43 (7~4) and byte 45 (bits 7~0). Each memory channel will have a value. uint8 nck dram_twtr_l ATTR_MEM_EFF_DRAM_TMAW TARGET_TYPE_MEM_PORT Maximum Activate Window in nck (number of clock cycles). Decodes SPD byte 7 (bits 5~4). Depends on tREFI multiplier. Each memory channel will have a value. uint16 nck dram_tmaw ATTR_MEM_EFF_DRAM_WIDTH TARGET_TYPE_MEM_PORT ARRAY[DIMM] SDRAM Device Width Decodes SPD Byte 12 (bits 2~0). Options: X4 (4 bits), X8 (8 bits), X16 (16 bits), X32 (32 bits). uint8 X4 = 4, X8 = 8, X16 = 16, X32 = 32 bits 2 dram_width ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM TARGET_TYPE_MEM_PORT ARRAY[DIMM] Total number of ranks in each DIMM. For monolithic and multi-load stack modules (SDP/DDP) this is the same as the number of package ranks per DIMM (SPD Byte 12 bits 5~3). For single load stack (3DS) modules this value represents the number of logical ranks per DIMM. Logical rank refers the individually addressable die in a 3DS stack and has no meaning for monolithic or multi-load stacked SDRAMs. uint8 1R = 1, 2R = 2, 4R = 4, 8R = 8, 16R = 16 2 logical_ranks_per_dimm ATTR_MEM_3DS_HEIGHT TARGET_TYPE_MEM_PORT Setting for 3DS stack. Calculated from logical_ranks / master_ranks uint16 PLANAR = 0, H2 = 2, H4 = 4, H8 = 8 2 3ds_height ATTR_MEM_EFF_REGISTER_TYPE TARGET_TYPE_MEM_PORT ARRAY[DIMM] Register Type Decodes SPD Byte 131 RCD01 = 0x0, RCD02 = 0x1 uint8 2 register_type ATTR_MEM_EFF_DRAM_MFG_ID TARGET_TYPE_MEM_PORT ARRAY[DIMM] DRAM Manufacturer ID Code Decodes SPD Byte 350 and 351 for ISDIMMs Decodes SPD Byte 552 and 553 for DDIMMs MICRON = 0x802C, SAMSUNG = 0x80CE, HYNIX = 0x80AD uint16 2 dram_mfg_id ATTR_MEM_EFF_DRAM_MODULE_HEIGHT TARGET_TYPE_MEM_PORT ARRAY[DIMM] DRAM Modlue Height Decodes SPD Byte 193 1U = 0, 2U = 1, 4U = 2 uint8 2 dram_module_height ATTR_MEM_EFF_RCD_MFG_ID TARGET_TYPE_MEM_PORT ARRAY[DIMM] Register Manufacturer ID Code Decodes SPD Byte 133 and 134 INPHI = 0xB304, MONTAGE = 0x3286, IDT = 0xB380 uint16 2 rcd_mfg_id ATTR_MEM_EFF_REGISTER_REV TARGET_TYPE_MEM_PORT ARRAY[DIMM] Register Revision Number Decodes SPD Byte 135 uint8 2 register_rev ATTR_MEM_EFF_PACKAGE_RANK_MAP TARGET_TYPE_MEM_PORT ARRAY[DIMM][DQ_NIBBLES] Package Rank Map Decodes SPD Byte 60 - 77 (Bits 7~6) uint8 2 20 package_rank_map ATTR_MEM_EFF_NIBBLE_MAP TARGET_TYPE_MEM_PORT ARRAY[DIMM][DQ_NIBBLES] Nibble Map Decodes SPD Byte 60 - 77 (Bits 5~0) for DDR4 uint8 2 20 nibble_map ATTR_MEM_EFF_DIMM_SIZE TARGET_TYPE_MEM_PORT ARRAY[DIMM] DIMM Size, in GB Used in various locations uint32 4GB = 4, 8GB = 8, 16GB = 16, 32GB = 32, 64GB = 64, 128GB = 128, 256GB = 256, 512GB = 512 2 GB dimm_size ATTR_MEM_EFF_DIMM_SPARE TARGET_TYPE_MEM_PORT Spare DRAM availability. Used in various locations and is computed in mss_eff_cnfg. Array indexes are [DIMM][RANK] uint8 NO_SPARE = 0, LOW_NIBBLE = 1, HIGH_NIBBLE = 2, FULL_BYTE = 3 2 4 dimm_spare ATTR_MEM_EFF_DRAM_CL TARGET_TYPE_MEM_PORT CAS Latency. Each memory channel will have a value. uint8 nck dram_cl ATTR_MEM_EFF_DRAM_MDS TARGET_TYPE_MEM_PORT Controls if the given target has an MDS (managed DRAM solution) uint8 dram_mds ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM TARGET_TYPE_MEM_PORT ARRAY[DIMM] Specifies the number of master ranks per DIMM. Represents the number of physical ranks on a DIMM. From SPD spec JEDEC Standard No. 21-C: Page 4.1.2.L-4. Byte 12 (Bits 5~3) Number of package ranks per DIMM. Package ranks per DIMM refers to the collections of devices on the module sharing common chip select signals. uint8 1R = 1, 2R = 2, 4R = 4, 8R = 8 2 num_master_ranks_per_dimm ATTR_MEM_EFF_DIMM_RANKS_CONFIGED TARGET_TYPE_MEM_PORT Bit wise representation of master ranks in each DIMM that are used for reads and writes. Used by PRD. uint8 2 dimm_ranks_configed ATTR_MEM_EFF_DRAM_TREFI TARGET_TYPE_MEM_PORT Average Refresh Interval (tREFI) in nck (number of clock cycles). This depends on MRW attribute that selects fine refresh mode (x1, x2, x4). From DDR4 spec (79-4A). For 3DS, the tREFI time to the same logical rank is defined as tRFC_slr1, tRFC_slr2, or tRFC_slr4. uint16 nck dram_trefi ATTR_MEM_EFF_DRAM_TRTP TARGET_TYPE_MEM_PORT Internal Read to Precharge Delay. From the DDR4 spec (79-4A). Each memory channel will have a value. uint8 nck dram_trtp ATTR_MEM_EFF_DRAM_TRFC_DLR TARGET_TYPE_MEM_PORT Minimum Refresh Recovery Delay Time (different logical ranks) in nck (number of clock cyles). Selected tRFC value (tRFC_dlr1, tRFC_dlr2, or tRFC_dlr4) depends on MRW attribute that selects fine refresh mode (x1, x2, x4). For 3DS, The tRFC time to different logical ranks are defined as tRFC_dlr uint8 nck dram_trfc_dlr ATTR_MEM_EFF_FREQ TARGET_TYPE_MEM_PORT Frequency of this memory channel in MT/s (Mega Transfers per second) uint64 MT/s freq ATTR_MEM_EFF_VOLT_VDDR TARGET_TYPE_OCMB_CHIP DRAM Voltage, each voltage rail would need to have a value. uint32 mV volt_vddr ATTR_MEM_EFF_VOLT_VPP TARGET_TYPE_OCMB_CHIP DRAM VPP Voltage, each voltage rail would need to have a value. uint32 mV volt_vpp