ATTR_MEM_DRAM_CWL TARGET_TYPE_MEM_PORT CAS Write Latency. nck uint8 dram_cwl ATTR_MEM_RDIMM_BUFFER_DELAY TARGET_TYPE_MEM_PORT Delay due to the presence of a buffer, in number of clocks nck uint8 dimm_buffer_delay ATTR_MEM_REORDER_QUEUE_SETTING TARGET_TYPE_OCMB_CHIP Contains the settings for write/read reorder queue REORDER = 0, FIFO = 1 uint8 reorder_queue_setting ATTR_MEM_2N_MODE TARGET_TYPE_OCMB_CHIP Default value for 2N Mode from Signal Integrity. 0x0 = Invalid Mode, 0x01 = 1N Mode , 0x02 = 2N Mode If value is set to 0x0 this indicate value was never initialized correctly. uint8 mem_2n_mode ATTR_MEM_VPD_DQ_MAP TARGET_TYPE_MEM_PORT ARRAY[Dimm DQ PIN] The map from the Dual Inline Memory Module (DIMM) Data (DQ) Pin to the Module Package Data (DQ) Pinout uint8 0 72 mem_vpd_dq_map 72 ATTR_MEM_DIMM_DDR4_F0RC0F TARGET_TYPE_MEM_PORT ARRAY[DIMM] F0RC0F - Command Latency Adder Control Word; Default value - 04. Values Range from 00 to 04. No need to calculate; User can override with desired experimental value. uint8 2 dimm_ddr4_f0rc0f ATTR_MEM_CS_CMD_LATENCY TARGET_TYPE_MEM_PORT ARRAY[DIMM] CS to CMD/ADDR Latency. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value. uint8 DISABLE = 0, 3CYC = 3, 4CYC = 4, 5CYC = 5, 6CYC = 6, 8CYC = 8 2 cs_cmd_latency ATTR_MEM_CA_PARITY_LATENCY TARGET_TYPE_MEM_PORT ARRAY[DIMM] C/A Parity Latency Mode. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value. uint8 DISABLE = 0, PL4 = 4, PL5 = 5, PL6 = 6, PL8 = 8 2 ca_parity_latency ATTR_MEM_DIMM_DDR4_F0RC02 TARGET_TYPE_MEM_PORT ARRAY[DIMM] F0RC02: Timing and IBT Control Word; Default value - 0x00. Values Range from 0-8. No need to calculate; User can override with desired experimental value. uint8 2 dimm_ddr4_f0rc02 ATTR_MEM_DIMM_DDR4_F0RC03 TARGET_TYPE_MEM_PORT ARRAY[DIMM] F0RC03 - CA and CS Signals Driver Characteristics Control Word; Default value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD byte 137, 1st Nibble for CS and CA. uint8 2 dimm_ddr4_f0rc03 ATTR_MEM_DIMM_DDR4_F0RC04 TARGET_TYPE_MEM_PORT ARRAY[DIMM] F0RC04 - ODT and CKE Signals Driver Characteristics Control Word; Default value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD byte 137, 2nd Nibble for ODT and CKE. uint8 2 dimm_ddr4_f0rc04 ATTR_MEM_DIMM_DDR4_F0RC05 TARGET_TYPE_MEM_PORT ARRAY[DIMM] F0RC05 - Clock Driver Characteristics Control Word; Default value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD byte 138, 2nd Nibble for CK. uint8 2 dimm_ddr4_f0rc05 ATTR_MEM_DIMM_DDR4_F0RC0B TARGET_TYPE_MEM_PORT ARRAY[DIMM] Operating Voltage VDD and VrefCA Source Control Word; Read from ATTR_MSS_VOLT_VDDR. Default value - 14. Values Range from 00 to 15 decimal. No need to calculate; User can override with desired experimental value. uint8 2 dimm_ddr4_f0rc0b ATTR_MEM_DIMM_DDR4_F0RC1X TARGET_TYPE_MEM_PORT ARRAY[DIMM] F0RC1x - Internal VrefCA Control Word; Default value - 00. Values Range from 00 to 3F. No need to calculate; User can override with desired experimental value. uint8 2 dimm_ddr4_f0rc1x ATTR_MEM_DIMM_DDR4_F0RC7X TARGET_TYPE_MEM_PORT ARRAY[DIMM] F0RC7x: IBT Control Word; Default value - 00. Values Range from 00 to FF.No need to calculate. User can override with desired experimental value. uint8 2 dimm_ddr4_f0rc7x ATTR_MEM_DIMM_DDR4_F1RC00 TARGET_TYPE_MEM_PORT ARRAY[DIMM] F1RC00: Data Buffer Interface Driver Characteristics Control Word; Default value - 00. Values Range from 00 to 0F. No need to calculate. User can override with desired experimental value. uint8 2 dimm_ddr4_f1rc00 ATTR_MEM_DIMM_DDR4_F1RC02 TARGET_TYPE_MEM_PORT ARRAY[DIMM] F1RC00: Data Buffer Interface Driver Characteristics Control Word; Default value - 00. Values Range from 00 to 0F. No need to calculate; User can override with desired experimental value. uint8 2 dimm_ddr4_f1rc02 ATTR_MEM_DIMM_DDR4_F1RC03 TARGET_TYPE_MEM_PORT ARRAY[DIMM] F1RC00: Data Buffer Interface Driver Characteristics Control Word. Default value - 00. Values Range from 00 to 0F. No need to calculate. User can override with desired experimental value. uint8 2 dimm_ddr4_f1rc03 ATTR_MEM_DIMM_DDR4_F1RC04 TARGET_TYPE_MEM_PORT ARRAY[DIMM] F1RC00: Data Buffer Interface Driver Characteristics Control Word; Default value - 00. Values Range from 00 to 0F. No need to calculate. User can override with desired experimental value. uint8 2 dimm_ddr4_f1rc04 ATTR_MEM_DIMM_DDR4_F1RC05 TARGET_TYPE_MEM_PORT ARRAY[DIMM] F1RC00: Data Buffer Interface Driver Characteristics Control Word. Default value - 00. Values Range from 00 to 0F. No need to calculate. User can override with desired experimental value. uint8 2 dimm_ddr4_f1rc05 ATTR_MEM_DIMM_POS_METADATA TARGET_TYPE_DIMM To get the FAPI_POS to the equivilent of ATTR_POS, we need to normalize the fapi_pos value to the processor (stride across which ever processor we're on) and then add in the delta per processor as ATTR_POS isn't processor relative (delta is the total dimm on a processor) uint32 dimm_pos_metadata ATTR_MEM_DRAM_GEN_METADATA TARGET_TYPE_DIMM DRAM Device Type. Decodes SPD byte 2. Created for use by attributes that need this data earlier than eff_config, such as c_str and the hypervisor. Not meant for direct HWP use. This is just an abstraction of any chip specific EFF_DRAM_GEN attribute. uint8 EMPTY = 0, DDR3 = 1, DDR4 = 2 dram_gen_metadata ATTR_MEM_DIMM_TYPE_METADATA TARGET_TYPE_DIMM Base Module Type. Decodes SPD Byte 3 (bits 3~0). Created for use by attributes that need this data earlier than eff_config, such as c_str and the hypervisor. Not meant for direct HWP use. This is just an abstraction of any chip specific EFF_DIMM_TYPE attribute. uint8 EMPTY = 0, RDIMM = 1, UDIMM = 2, LRDIMM = 3, DDIMM = 4 dimm_type_metadata ATTR_MSS_OMI_EDPL_DISABLE TARGET_TYPE_SYSTEM EDPL (Error Detection Per Lane) is a feature in the DL that adds some additional checks to the traffic going across the OpenCAPI link in order to better track which lanes are having issues. Note: EDPL must be set the same on both sides of the link. This attribute affects both the proc/mc side and the OCMB side. uint8 FALSE = 0, TRUE = 1 mss_omi_edpl_disable ATTR_OMI_DL_PREIPL_PRBS_TIME TARGET_TYPE_OMI The time to send pre-ipl PRBS in ms. uint32 0x400 omi_dl_preipl_prbs_time