ATTR_MEM_FREQ
TARGET_TYPE_MEM_PORT
Frequency of this memory channel in MT/s (Mega Transfers per second)
uint64
freq
ATTR_MEM_EFF_DIMM_TYPE
TARGET_TYPE_MEM_PORT
Base Module Type.
Decodes SPD Byte 3 (bits 3~0).
Type of DIMM: RDIMM, UDIMM, LRDIMM as specified by the JEDEC standard.
uint8
eff_dimm_type
2
EMPTY = 0, RDIMM = 1, UDIMM = 2, LRDIMM = 3
ATTR_MEM_EFF_DRAM_CL
TARGET_TYPE_MEM_PORT
CAS Latency.
nck
uint8
eff_dram_cl
ATTR_MEM_EFF_DRAM_CWL
TARGET_TYPE_MEM_PORT
CAS Write Latency.
nck
uint8
eff_dram_cwl
ATTR_MEM_EFF_DRAM_TCCD_L
TARGET_TYPE_MEM_PORT
Minimum CAS to CAS Delay Time, same bank group
in nck (number of clock cycles).
Decodes SPD byte 40 (bits 7~0) and byte 117 (bits 7~0).
This is for DDR4 MRS6.
nck
uint8
eff_dram_tccd_l
ATTR_MEM_EFF_DRAM_TFAW
TARGET_TYPE_MEM_PORT
Minimum Four Activate Window Delay Time
in nck (number of clock cycles).
Decodes SPD byte 36 (bits 3~0) and byte 37 (bits 7~0).
For 3DS, tFAW time to the same logical rank is defined as
tFAW_slr_x4 or tFAW_slr_x8 (for x4 and x8 devices only) and
specificed as the value as for a monolithic DDR4 SDRAM
equivalent density.
nck
uint8
eff_dram_tfaw
ATTR_MEM_EFF_DRAM_TRAS
TARGET_TYPE_MEM_PORT
Minimum Active to Precharge Delay Time
in nck (number of clock cycles).
Decodes SPD byte 27 (bits 3~0) and byte 28 (7~0).
nck
uint8
eff_dram_tras
ATTR_MEM_EFF_DRAM_TRCD
TARGET_TYPE_MEM_PORT
Minimum RAS to CAS Delay Time
in nck (number of clock cyles).
Decodes SPD byte 25 (7~0) and byte 112 (7~0).
nck
uint8
eff_dram_trcd
ATTR_MEM_EFF_DRAM_TREFI
TARGET_TYPE_MEM_PORT
Average Refresh Interval (tREFI)
in nck (number of clock cycles).
This depends on MRW attribute that selects fine refresh mode (x1, x2, x4).
From DDR4 spec (79-4A).
For 3DS, the tREFI time to the same logical rank is defined as
tREFI_slr1, tREFI_slr2, or tREFI_slr4.
nck
uint16
eff_dram_trefi
ATTR_MEM_EFF_DRAM_TRFC
TARGET_TYPE_MEM_PORT
DDR4 Spec defined as Refresh Cycle Time (tRFC).
SPD Spec refers it to the Minimum Refresh Recovery Delay Time.
In nck (number of clock cyles).
Decodes SPD byte 31 (bits 15~8) and byte 30 (bits 7~0) for tRFC1.
Decodes SPD byte 33 (bits 15~8) and byte 32 (bits 7~0) for tRFC2.
Decodes SPD byte 35 (bits 15~8) and byte 34 (bits 7~0) for tRFC4.
Selected tRFC value depends on MRW attribute that selects refresh mode.
For 3DS, The tRFC time to the same logical rank is defined as tRFC_slr and is
specificed as the value as for a monolithic DDR4 SDRAM of equivalent density.
nck
uint16
eff_dram_trfc
ATTR_MEM_EFF_DRAM_TRFC_DLR
TARGET_TYPE_MEM_PORT
Minimum Refresh Recovery Delay Time (different logical ranks)
in nck (number of clock cyles).
Selected tRFC value (tRFC_dlr1, tRFC_dlr2, or tRFC_dlr4)
depends on MRW attribute that selects fine refresh mode (x1, x2, x4).
For 3DS, The tRFC time to different logical ranks are defined as tRFC_dlr
nck
uint16
eff_dram_trfc_dlr
ATTR_MEM_EFF_DRAM_TRP
TARGET_TYPE_MEM_PORT
SDRAM Row Precharge Delay Time
in nck (number of clock cycles).
Decodes SPD byte 26 (bits 7~0) and byte 121 (bits 7~0).
nck
uint8
eff_dram_trp
ATTR_MEM_EFF_DRAM_TRRD_L
TARGET_TYPE_MEM_PORT
Minimum Activate to Activate Delay Time, same bank group
in nck (number of clock cycles).
Decodes SPD byte 39 (bits 7~0).
For 3DS, The tRRD_L time to the same bank group in the
same logical rank is defined as tRRD_L_slr and is
specificed as the value as for a monolithic
DDR4 SDRAM of equivalent density.
nck
uint8
eff_dram_trrd_l
ATTR_MEM_EFF_DRAM_TRRD_S
TARGET_TYPE_MEM_PORT
Minimum Activate to Activate Delay Time, different bank group
in nck (number of clock cycles).
Decodes SPD byte 38 (bits 7~0).
For 3DS, The tRRD_S time to a different bank group in the
same logical rank is defined as tRRD_slr and is
specificed as the value as for a monolithic
DDR4 SDRAM of equivalent density.
nck
uint8
eff_dram_trrd_s
ATTR_MEM_EFF_DRAM_TRTP
TARGET_TYPE_MEM_PORT
Internal Read to Precharge Delay.
From the DDR4 spec (79-4A).
nck
uint8
eff_dram_trtp
ATTR_MEM_EFF_DRAM_TWR
TARGET_TYPE_MEM_PORT
Minimum Write Recovery Time.
Decodes SPD byte 41 (bits 3~0) and byte 42 (bits 7~0).
nck
uint8
eff_dram_twr
ATTR_MEM_EFF_DRAM_TWTR_L
TARGET_TYPE_MEM_PORT
Minimum Write to Read Time, same bank group
in nck (number of clock cycles).
Decodes byte 43 (7~4) and byte 45 (bits 7~0).
nck
uint8
eff_dram_twtr_l
ATTR_MEM_EFF_DRAM_TWTR_S
TARGET_TYPE_MEM_PORT
Minimum Write to Read Time, different bank group
in nck (number of clock cycles).
Decodes SPD byte 43 (3~0) and byte 44 (bits 7~0).
nck
uint8
eff_dram_twtr_s
ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM
TARGET_TYPE_MEM_PORT
Specifies the number of master ranks per DIMM.
Represents the number of physical ranks on a DIMM.
From SPD spec JEDEC Standard No. 21-C: Page 4.1.2.L-4.
Byte 12 (Bits 5~3) Number of package ranks per DIMM.
Package ranks per DIMM refers to the collections of devices
on the module sharing common chip select signals.
uint8
eff_num_master_ranks_per_dimm
2
ATTR_MEM_EFF_NUM_RANKS_PER_DIMM
TARGET_TYPE_MEM_PORT
Total number of ranks in each DIMM.
For monolithic and multi-load stack modules (SDP/DDP) this is the same as
the number of package ranks per DIMM (SPD Byte 12 bits 5~3).
For single load stack (3DS) modules this value represents the number
of logical ranks per DIMM.
Logical rank refers the individually addressable die in a 3DS stack
and has no meaning for monolithic or multi-load stacked SDRAMs.
uint8
eff_num_ranks_per_dimm
2
ATTR_MEM_RDIMM_BUFFER_DELAY
TARGET_TYPE_MEM_PORT
Delay due to the presence of a buffer, in number of clocks
nck
uint8
dimm_buffer_delay
ATTR_MEM_REORDER_QUEUE_SETTING
TARGET_TYPE_OCMB_CHIP
Contains the settings for write/read reorder queue
REORDER = 0, FIFO = 1
uint8
reorder_queue_setting
ATTR_MEM_2N_MODE
TARGET_TYPE_OCMB_CHIP
Default value for 2N Mode from Signal Integrity.
0x0 = Invalid Mode, 0x01 = 1N Mode , 0x02 = 2N Mode
If value is set to 0x0 this indicate value was never
initialized correctly.
uint8
mem_2n_mode