/* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ /* $Source: src/import/chips/p9a/procedures/hwp/memory/lib/mc/omi_traits.H $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ /* Contributors Listed Below - COPYRIGHT 2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ /* You may obtain a copy of the License at */ /* */ /* http://www.apache.org/licenses/LICENSE-2.0 */ /* */ /* Unless required by applicable law or agreed to in writing, software */ /* distributed under the License is distributed on an "AS IS" BASIS, */ /* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ /* implied. See the License for the specific language governing */ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ /// /// @file omi_traits.H /// @brief Traits class for the MC ECC syndrome registers /// // *HWP HWP Owner: Louis Stermole // *HWP HWP Backup: Stephen Glancy // *HWP Team: Memory // *HWP Level: 3 // *HWP Consumed by: FSP:HB #ifndef _P9A_OMI_TRAITS_H_ #define _P9A_OMI_TRAITS_H_ #include #include #include #include #include namespace mss { /// /// @class omiTraits /// @brief a collection of traits associated with the mc omi interface /// @tparam T fapi2::TargetType representing the mc/omi /// @tparam PROC mss::proc_typ representing the processor /// template< fapi2::TargetType T, mss::proc_type PROC = DEFAULT_PROC_TYPE> class omiTraits; /// /// @class omiTraits /// @brief a collection of traits associated with the axone mc omi interface /// template<> class omiTraits< fapi2::TARGET_TYPE_MC > { public: //MC OMI registers - must be 64 bits. static constexpr uint64_t MC_REG0_CMN_CONFIG = P9A_MC_REG0_CMN_CONFIG; static constexpr uint64_t MC_REG1_CMN_CONFIG = P9A_MC_REG1_CMN_CONFIG; static constexpr uint64_t MC_REG2_CMN_CONFIG = P9A_MC_REG2_CMN_CONFIG; // Fields, can be any size. enum { // MC_REGx_CMN_CONFIG MC_REG0_CMN_CONFIG_SPARE = P9A_MC_REG0_CMN_CONFIG_SPARE, MC_REG0_CMN_CONFIG_SPARE_LEN = P9A_MC_REG0_CMN_CONFIG_SPARE_LEN, MC_REG0_CMN_CONFIG_PM_CDR_TIMER = P9A_MC_REG0_CMN_CONFIG_PM_CDR_TIMER, MC_REG0_CMN_CONFIG_PM_CDR_TIMER_LEN = P9A_MC_REG0_CMN_CONFIG_PM_CDR_TIMER_LEN, MC_REG0_CMN_CONFIG_PM_DIDT_TIMER = P9A_MC_REG0_CMN_CONFIG_PM_DIDT_TIMER, MC_REG0_CMN_CONFIG_PM_DIDT_TIMER_LEN = P9A_MC_REG0_CMN_CONFIG_PM_DIDT_TIMER_LEN, MC_REG0_CMN_CONFIG_PSAV_STS_ENABLE = P9A_MC_REG0_CMN_CONFIG_PSAV_STS_ENABLE, MC_REG0_CMN_CONFIG_RECAL_TIMER = P9A_MC_REG0_CMN_CONFIG_RECAL_TIMER, MC_REG0_CMN_CONFIG_RECAL_TIMER_LEN = P9A_MC_REG0_CMN_CONFIG_RECAL_TIMER_LEN, MC_REG0_CMN_CONFIG_CFG_CMN_1US_TMR = P9A_MC_REG0_CMN_CONFIG_CFG_CMN_1US_TMR, MC_REG0_CMN_CONFIG_CFG_CMN_1US_TMR_LEN = P9A_MC_REG0_CMN_CONFIG_CFG_CMN_1US_TMR_LEN, MC_REG0_CMN_CONFIG_CFG_CMN_DBG_EN = P9A_MC_REG0_CMN_CONFIG_CFG_CMN_DBG_EN, MC_REG0_CMN_CONFIG_DBG_SEL = P9A_MC_REG0_CMN_CONFIG_DBG_SEL, MC_REG0_CMN_CONFIG_DBG_SEL_LEN = P9A_MC_REG0_CMN_CONFIG_DBG_SEL_LEN, MC_REG0_CMN_CONFIG_RD_RST = P9A_MC_REG0_CMN_CONFIG_RD_RST, MC_REG0_CMN_CONFIG_PRE_SCALAR = P9A_MC_REG0_CMN_CONFIG_PRE_SCALAR, MC_REG0_CMN_CONFIG_PRE_SCALAR_LEN = P9A_MC_REG0_CMN_CONFIG_PRE_SCALAR_LEN, MC_REG0_CMN_CONFIG_CFG_CMN_FREEZE = P9A_MC_REG0_CMN_CONFIG_CFG_CMN_FREEZE, MC_REG0_CMN_CONFIG_PORT_SEL = P9A_MC_REG0_CMN_CONFIG_PORT_SEL, MC_REG0_CMN_CONFIG_PORT_SEL_LEN = P9A_MC_REG0_CMN_CONFIG_PORT_SEL_LEN, MC_REG0_CMN_CONFIG_CNTR3_PS = P9A_MC_REG0_CMN_CONFIG_CNTR3_PS, MC_REG0_CMN_CONFIG_CNTR3_PS_LEN = P9A_MC_REG0_CMN_CONFIG_CNTR3_PS_LEN, MC_REG0_CMN_CONFIG_CNTR3_ES = P9A_MC_REG0_CMN_CONFIG_CNTR3_ES, MC_REG0_CMN_CONFIG_CNTR3_ES_LEN = P9A_MC_REG0_CMN_CONFIG_CNTR3_ES_LEN, MC_REG0_CMN_CONFIG_CNTR2_PS = P9A_MC_REG0_CMN_CONFIG_CNTR2_PS, MC_REG0_CMN_CONFIG_CNTR2_PS_LEN = P9A_MC_REG0_CMN_CONFIG_CNTR2_PS_LEN, MC_REG0_CMN_CONFIG_CNTR2_ES = P9A_MC_REG0_CMN_CONFIG_CNTR2_ES, MC_REG0_CMN_CONFIG_CNTR2_ES_LEN = P9A_MC_REG0_CMN_CONFIG_CNTR2_ES_LEN, MC_REG0_CMN_CONFIG_CNTR1_PS = P9A_MC_REG0_CMN_CONFIG_CNTR1_PS, MC_REG0_CMN_CONFIG_CNTR1_PS_LEN = P9A_MC_REG0_CMN_CONFIG_CNTR1_PS_LEN, MC_REG0_CMN_CONFIG_CNTR1_ES = P9A_MC_REG0_CMN_CONFIG_CNTR1_ES, MC_REG0_CMN_CONFIG_CNTR1_ES_LEN = P9A_MC_REG0_CMN_CONFIG_CNTR1_ES_LEN, MC_REG0_CMN_CONFIG_CNTR0_PS = P9A_MC_REG0_CMN_CONFIG_CNTR0_PS, MC_REG0_CMN_CONFIG_CNTR0_PS_LEN = P9A_MC_REG0_CMN_CONFIG_CNTR0_PS_LEN, MC_REG0_CMN_CONFIG_CNTR0_ES = P9A_MC_REG0_CMN_CONFIG_CNTR0_ES, MC_REG0_CMN_CONFIG_CNTR0_ES_LEN = P9A_MC_REG0_CMN_CONFIG_CNTR0_ES_LEN, MC_REG0_CMN_CONFIG_CNTR3_PE = P9A_MC_REG0_CMN_CONFIG_CNTR3_PE, MC_REG0_CMN_CONFIG_CNTR2_PE = P9A_MC_REG0_CMN_CONFIG_CNTR2_PE, MC_REG0_CMN_CONFIG_CNTR1_PE = P9A_MC_REG0_CMN_CONFIG_CNTR1_PE, MC_REG0_CMN_CONFIG_CNTR0_PE = P9A_MC_REG0_CMN_CONFIG_CNTR0_PE, MC_REG0_CMN_CONFIG_CNTR3_EN = P9A_MC_REG0_CMN_CONFIG_CNTR3_EN, MC_REG0_CMN_CONFIG_CNTR2_EN = P9A_MC_REG0_CMN_CONFIG_CNTR2_EN, MC_REG0_CMN_CONFIG_CNTR1_EN = P9A_MC_REG0_CMN_CONFIG_CNTR1_EN, MC_REG0_CMN_CONFIG_CNTR0_EN = P9A_MC_REG0_CMN_CONFIG_CNTR0_EN, }; }; /// /// @class omiTraits /// @brief a collection of traits associated with the axone mc omi interface /// template<> class omiTraits< fapi2::TARGET_TYPE_OMI, DEFAULT_PROC_TYPE > { public: //MC OMI registers - must be 64 bits. static constexpr uint64_t MC_REG2_DL0_CONFIG0 = P9A_MC_REG2_DL0_CONFIG0; static constexpr uint64_t MC_REG2_DL0_CONFIG1 = P9A_MC_REG2_DL0_CONFIG1; static constexpr uint64_t MC_REG2_DL0_STATUS = P9A_MC_REG2_DL0_STATUS; static constexpr uint64_t MC_REG2_DL0_CYA_BITS = P9A_MC_REG2_DL0_CYA_BITS; static constexpr uint64_t MC_REG2_DL0_ERROR_ACTION = P9A_MC_REG2_DL0_ERROR_ACTION; static constexpr uint64_t MC_REG2_DL0_RMT_CONFIG = P9A_MC_REG2_DL0_RMT_CONFIG; // Fields, can be any size. enum { // MC_REG2_DL0_CONFIG0 MC_REG2_DL0_CONFIG0_CFG_ENABLE = P9A_MC_REG2_DL0_CONFIG0_CFG_ENABLE, MC_REG2_DL0_CONFIG0_CFG_CFG_SPARE = P9A_MC_REG2_DL0_CONFIG0_CFG_CFG_SPARE, MC_REG2_DL0_CONFIG0_CFG_CFG_SPARE_LEN = P9A_MC_REG2_DL0_CONFIG0_CFG_CFG_SPARE_LEN, MC_REG2_DL0_CONFIG0_CFG_CFG_TL_CREDITS = P9A_MC_REG2_DL0_CONFIG0_CFG_CFG_TL_CREDITS, MC_REG2_DL0_CONFIG0_CFG_CFG_TL_CREDITS_LEN = P9A_MC_REG2_DL0_CONFIG0_CFG_CFG_TL_CREDITS_LEN, MC_REG2_DL0_CONFIG0_CFG_TL_EVENT_ACTIONS = P9A_MC_REG2_DL0_CONFIG0_CFG_TL_EVENT_ACTIONS, MC_REG2_DL0_CONFIG0_CFG_TL_EVENT_ACTIONS_LEN = P9A_MC_REG2_DL0_CONFIG0_CFG_TL_EVENT_ACTIONS_LEN, MC_REG2_DL0_CONFIG0_CFG_TL_ERROR_ACTIONS = P9A_MC_REG2_DL0_CONFIG0_CFG_TL_ERROR_ACTIONS, MC_REG2_DL0_CONFIG0_CFG_TL_ERROR_ACTIONS_LEN = P9A_MC_REG2_DL0_CONFIG0_CFG_TL_ERROR_ACTIONS_LEN, MC_REG2_DL0_CONFIG0_CFG_FWD_PROGRESS_TIMER = P9A_MC_REG2_DL0_CONFIG0_CFG_FWD_PROGRESS_TIMER, MC_REG2_DL0_CONFIG0_CFG_FWD_PROGRESS_TIMER_LEN = P9A_MC_REG2_DL0_CONFIG0_CFG_FWD_PROGRESS_TIMER_LEN, MC_REG2_DL0_CONFIG0_CFG_REPLAY_RSVD_ENTRIES = P9A_MC_REG2_DL0_CONFIG0_CFG_REPLAY_RSVD_ENTRIES, MC_REG2_DL0_CONFIG0_CFG_REPLAY_RSVD_ENTRIES_LEN = P9A_MC_REG2_DL0_CONFIG0_CFG_REPLAY_RSVD_ENTRIES_LEN, MC_REG2_DL0_CONFIG0_CFG_DEBUG_SELECT = P9A_MC_REG2_DL0_CONFIG0_CFG_DEBUG_SELECT, MC_REG2_DL0_CONFIG0_CFG_DEBUG_SELECT_LEN = P9A_MC_REG2_DL0_CONFIG0_CFG_DEBUG_SELECT_LEN, MC_REG2_DL0_CONFIG0_CFG_DEBUG_ENABLE = P9A_MC_REG2_DL0_CONFIG0_CFG_DEBUG_ENABLE, MC_REG2_DL0_CONFIG0_CFG_DL2TL_DATA_PARITY_INJECT = P9A_MC_REG2_DL0_CONFIG0_CFG_DL2TL_DATA_PARITY_INJECT, MC_REG2_DL0_CONFIG0_CFG_DL2TL_CONTROL_PARITY_INJECT = P9A_MC_REG2_DL0_CONFIG0_CFG_DL2TL_CONTROL_PARITY_INJECT, MC_REG2_DL0_CONFIG0_CFG_ECC_UE_INJECTION = P9A_MC_REG2_DL0_CONFIG0_CFG_ECC_UE_INJECTION, MC_REG2_DL0_CONFIG0_CFG_ECC_CE_INJECTION = P9A_MC_REG2_DL0_CONFIG0_CFG_ECC_CE_INJECTION, MC_REG2_DL0_CONFIG0_CFG_FP_DISABLE = P9A_MC_REG2_DL0_CONFIG0_CFG_FP_DISABLE, MC_REG2_DL0_CONFIG0_CFG_UNUSED2 = P9A_MC_REG2_DL0_CONFIG0_CFG_UNUSED2, MC_REG2_DL0_CONFIG0_CFG_TX_LN_REV_ENA = P9A_MC_REG2_DL0_CONFIG0_CFG_TX_LN_REV_ENA, MC_REG2_DL0_CONFIG0_CFG_128_130_ENCODING_ENABLED = P9A_MC_REG2_DL0_CONFIG0_CFG_128_130_ENCODING_ENABLED, MC_REG2_DL0_CONFIG0_CFG_PHY_CNTR_LIMIT = P9A_MC_REG2_DL0_CONFIG0_CFG_PHY_CNTR_LIMIT, MC_REG2_DL0_CONFIG0_CFG_PHY_CNTR_LIMIT_LEN = P9A_MC_REG2_DL0_CONFIG0_CFG_PHY_CNTR_LIMIT_LEN, MC_REG2_DL0_CONFIG0_CFG_TX_EP_MODE = P9A_MC_REG2_DL0_CONFIG0_CFG_TX_EP_MODE, MC_REG2_DL0_CONFIG0_CFG_PWRMGT_ENABLE = P9A_MC_REG2_DL0_CONFIG0_CFG_PWRMGT_ENABLE, MC_REG2_DL0_CONFIG0_CFG_X1_BACKOFF_ENABLE = P9A_MC_REG2_DL0_CONFIG0_CFG_X1_BACKOFF_ENABLE, MC_REG2_DL0_CONFIG0_CFG_X4_BACKOFF_ENABLE = P9A_MC_REG2_DL0_CONFIG0_CFG_X4_BACKOFF_ENABLE, MC_REG2_DL0_CONFIG0_CFG_SUPPORTED_MODES = P9A_MC_REG2_DL0_CONFIG0_CFG_SUPPORTED_MODES, MC_REG2_DL0_CONFIG0_CFG_SUPPORTED_MODES_LEN = P9A_MC_REG2_DL0_CONFIG0_CFG_SUPPORTED_MODES_LEN, MC_REG2_DL0_CONFIG0_CFG_TRAIN_MODE = P9A_MC_REG2_DL0_CONFIG0_CFG_TRAIN_MODE, MC_REG2_DL0_CONFIG0_CFG_TRAIN_MODE_LEN = P9A_MC_REG2_DL0_CONFIG0_CFG_TRAIN_MODE_LEN, MC_REG2_DL0_CONFIG0_CFG_VERSION = P9A_MC_REG2_DL0_CONFIG0_CFG_VERSION, MC_REG2_DL0_CONFIG0_CFG_VERSION_LEN = P9A_MC_REG2_DL0_CONFIG0_CFG_VERSION_LEN, MC_REG2_DL0_CONFIG0_CFG_RETRAIN = P9A_MC_REG2_DL0_CONFIG0_CFG_RETRAIN, MC_REG2_DL0_CONFIG0_CFG_RESET = P9A_MC_REG2_DL0_CONFIG0_CFG_RESET, // MC_REG2_DL0_CONFIG1 MC_REG2_DL0_CONFIG1_CFG_CFG1_SPARE = P9A_MC_REG2_DL0_CONFIG1_CFG_CFG1_SPARE, MC_REG2_DL0_CONFIG1_CFG_CFG1_SPARE_LEN = P9A_MC_REG2_DL0_CONFIG1_CFG_CFG1_SPARE_LEN, MC_REG2_DL0_CONFIG1_CFG_LANE_WIDTH = P9A_MC_REG2_DL0_CONFIG1_CFG_LANE_WIDTH, MC_REG2_DL0_CONFIG1_CFG_LANE_WIDTH_LEN = P9A_MC_REG2_DL0_CONFIG1_CFG_LANE_WIDTH_LEN, MC_REG2_DL0_CONFIG1_CFG_PREIPL_PRBS_ENA = P9A_MC_REG2_DL0_CONFIG1_CFG_PREIPL_PRBS_ENA, MC_REG2_DL0_CONFIG1_CFG_PREIPL_PRBS_TIME = P9A_MC_REG2_DL0_CONFIG1_CFG_PREIPL_PRBS_TIME, MC_REG2_DL0_CONFIG1_CFG_PREIPL_PRBS_TIME_LEN = P9A_MC_REG2_DL0_CONFIG1_CFG_PREIPL_PRBS_TIME_LEN, MC_REG2_DL0_CONFIG1_CFG_B_HYSTERESIS = P9A_MC_REG2_DL0_CONFIG1_CFG_B_HYSTERESIS, MC_REG2_DL0_CONFIG1_CFG_B_HYSTERESIS_LEN = P9A_MC_REG2_DL0_CONFIG1_CFG_B_HYSTERESIS_LEN, MC_REG2_DL0_CONFIG1_CFG_A_HYSTERESIS = P9A_MC_REG2_DL0_CONFIG1_CFG_A_HYSTERESIS, MC_REG2_DL0_CONFIG1_CFG_A_HYSTERESIS_LEN = P9A_MC_REG2_DL0_CONFIG1_CFG_A_HYSTERESIS_LEN, MC_REG2_DL0_CONFIG1_CFG_B_PATTERN_LENGTH = P9A_MC_REG2_DL0_CONFIG1_CFG_B_PATTERN_LENGTH, MC_REG2_DL0_CONFIG1_CFG_B_PATTERN_LENGTH_LEN = P9A_MC_REG2_DL0_CONFIG1_CFG_B_PATTERN_LENGTH_LEN, MC_REG2_DL0_CONFIG1_CFG_A_PATTERN_LENGTH = P9A_MC_REG2_DL0_CONFIG1_CFG_A_PATTERN_LENGTH, MC_REG2_DL0_CONFIG1_CFG_A_PATTERN_LENGTH_LEN = P9A_MC_REG2_DL0_CONFIG1_CFG_A_PATTERN_LENGTH_LEN, MC_REG2_DL0_CONFIG1_CFG_TX_PERF_DEGRADED = P9A_MC_REG2_DL0_CONFIG1_CFG_TX_PERF_DEGRADED, MC_REG2_DL0_CONFIG1_CFG_TX_PERF_DEGRADED_LEN = P9A_MC_REG2_DL0_CONFIG1_CFG_TX_PERF_DEGRADED_LEN, MC_REG2_DL0_CONFIG1_CFG_RX_PERF_DEGRADED = P9A_MC_REG2_DL0_CONFIG1_CFG_RX_PERF_DEGRADED, MC_REG2_DL0_CONFIG1_CFG_RX_PERF_DEGRADED_LEN = P9A_MC_REG2_DL0_CONFIG1_CFG_RX_PERF_DEGRADED_LEN, MC_REG2_DL0_CONFIG1_CFG_TX_LANES_DISABLE = P9A_MC_REG2_DL0_CONFIG1_CFG_TX_LANES_DISABLE, MC_REG2_DL0_CONFIG1_CFG_TX_LANES_DISABLE_LEN = P9A_MC_REG2_DL0_CONFIG1_CFG_TX_LANES_DISABLE_LEN, MC_REG2_DL0_CONFIG1_CFG_RX_LANES_DISABLE = P9A_MC_REG2_DL0_CONFIG1_CFG_RX_LANES_DISABLE, MC_REG2_DL0_CONFIG1_CFG_RX_LANES_DISABLE_LEN = P9A_MC_REG2_DL0_CONFIG1_CFG_RX_LANES_DISABLE_LEN, MC_REG2_DL0_CONFIG1_CFG_RESET_ERR_HLD = P9A_MC_REG2_DL0_CONFIG1_CFG_RESET_ERR_HLD, MC_REG2_DL0_CONFIG1_CFG_RESET_ERR_CAP = P9A_MC_REG2_DL0_CONFIG1_CFG_RESET_ERR_CAP, MC_REG2_DL0_CONFIG1_CFG_RESET_TSHD_REG = P9A_MC_REG2_DL0_CONFIG1_CFG_RESET_TSHD_REG, MC_REG2_DL0_CONFIG1_CFG_RESET_RMT_MSG = P9A_MC_REG2_DL0_CONFIG1_CFG_RESET_RMT_MSG, MC_REG2_DL0_CONFIG1_CFG_INJECT_CRC_DIRECTION = P9A_MC_REG2_DL0_CONFIG1_CFG_INJECT_CRC_DIRECTION, MC_REG2_DL0_CONFIG1_CFG_INJECT_CRC_RATE = P9A_MC_REG2_DL0_CONFIG1_CFG_INJECT_CRC_RATE, MC_REG2_DL0_CONFIG1_CFG_INJECT_CRC_RATE_LEN = P9A_MC_REG2_DL0_CONFIG1_CFG_INJECT_CRC_RATE_LEN, MC_REG2_DL0_CONFIG1_CFG_INJECT_CRC_LANE = P9A_MC_REG2_DL0_CONFIG1_CFG_INJECT_CRC_LANE, MC_REG2_DL0_CONFIG1_CFG_INJECT_CRC_LANE_LEN = P9A_MC_REG2_DL0_CONFIG1_CFG_INJECT_CRC_LANE_LEN, MC_REG2_DL0_CONFIG1_CFG_INJECT_CRC_ERROR = P9A_MC_REG2_DL0_CONFIG1_CFG_INJECT_CRC_ERROR, MC_REG2_DL0_CONFIG1_CFG_EDPL_TIME = P9A_MC_REG2_DL0_CONFIG1_CFG_EDPL_TIME, MC_REG2_DL0_CONFIG1_CFG_EDPL_TIME_LEN = P9A_MC_REG2_DL0_CONFIG1_CFG_EDPL_TIME_LEN, MC_REG2_DL0_CONFIG1_CFG_EDPL_THRESHOLD = P9A_MC_REG2_DL0_CONFIG1_CFG_EDPL_THRESHOLD, MC_REG2_DL0_CONFIG1_CFG_EDPL_THRESHOLD_LEN = P9A_MC_REG2_DL0_CONFIG1_CFG_EDPL_THRESHOLD_LEN, MC_REG2_DL0_CONFIG1_CFG_EDPL_ENA = P9A_MC_REG2_DL0_CONFIG1_CFG_EDPL_ENA, // MC_REG2_DL0_CYA_BITS MC_REG2_DL0_CYA_BITS_CFG_BITS0 = P9A_MC_REG2_DL0_CYA_BITS_CFG_BITS0, MC_REG2_DL0_CYA_BITS_CFG_BITS0_LEN = P9A_MC_REG2_DL0_CYA_BITS_CFG_BITS0_LEN, // MC_REG2_DL0_ERROR_ACTION MC_REG2_DL0_ERROR_ACTION_FIR11_ACTION = P9A_MC_REG2_DL0_ERROR_ACTION_FIR11_ACTION, MC_REG2_DL0_ERROR_ACTION_FIR11_ACTION_LEN = P9A_MC_REG2_DL0_ERROR_ACTION_FIR11_ACTION_LEN, MC_REG2_DL0_ERROR_ACTION_FIR10_ACTION = P9A_MC_REG2_DL0_ERROR_ACTION_FIR10_ACTION, MC_REG2_DL0_ERROR_ACTION_FIR10_ACTION_LEN = P9A_MC_REG2_DL0_ERROR_ACTION_FIR10_ACTION_LEN, MC_REG2_DL0_ERROR_ACTION_FIR9_ACTION = P9A_MC_REG2_DL0_ERROR_ACTION_FIR9_ACTION, MC_REG2_DL0_ERROR_ACTION_FIR9_ACTION_LEN = P9A_MC_REG2_DL0_ERROR_ACTION_FIR9_ACTION_LEN, MC_REG2_DL0_ERROR_ACTION_FIR8_ACTION = P9A_MC_REG2_DL0_ERROR_ACTION_FIR8_ACTION, MC_REG2_DL0_ERROR_ACTION_FIR8_ACTION_LEN = P9A_MC_REG2_DL0_ERROR_ACTION_FIR8_ACTION_LEN, MC_REG2_DL0_ERROR_ACTION_FIR7_ACTION = P9A_MC_REG2_DL0_ERROR_ACTION_FIR7_ACTION, MC_REG2_DL0_ERROR_ACTION_FIR7_ACTION_LEN = P9A_MC_REG2_DL0_ERROR_ACTION_FIR7_ACTION_LEN, MC_REG2_DL0_ERROR_ACTION_FIR6_ACTION = P9A_MC_REG2_DL0_ERROR_ACTION_FIR6_ACTION, MC_REG2_DL0_ERROR_ACTION_FIR6_ACTION_LEN = P9A_MC_REG2_DL0_ERROR_ACTION_FIR6_ACTION_LEN, MC_REG2_DL0_ERROR_ACTION_FIR5_ACTION = P9A_MC_REG2_DL0_ERROR_ACTION_FIR5_ACTION, MC_REG2_DL0_ERROR_ACTION_FIR5_ACTION_LEN = P9A_MC_REG2_DL0_ERROR_ACTION_FIR5_ACTION_LEN, MC_REG2_DL0_ERROR_ACTION_FIR4_ACTION = P9A_MC_REG2_DL0_ERROR_ACTION_FIR4_ACTION, MC_REG2_DL0_ERROR_ACTION_FIR4_ACTION_LEN = P9A_MC_REG2_DL0_ERROR_ACTION_FIR4_ACTION_LEN, MC_REG2_DL0_ERROR_ACTION_FIR3_ACTION = P9A_MC_REG2_DL0_ERROR_ACTION_FIR3_ACTION, MC_REG2_DL0_ERROR_ACTION_FIR3_ACTION_LEN = P9A_MC_REG2_DL0_ERROR_ACTION_FIR3_ACTION_LEN, MC_REG2_DL0_ERROR_ACTION_FIR2_ACTION = P9A_MC_REG2_DL0_ERROR_ACTION_FIR2_ACTION, MC_REG2_DL0_ERROR_ACTION_FIR2_ACTION_LEN = P9A_MC_REG2_DL0_ERROR_ACTION_FIR2_ACTION_LEN, MC_REG2_DL0_ERROR_ACTION_FIR1_ACTION = P9A_MC_REG2_DL0_ERROR_ACTION_FIR1_ACTION, MC_REG2_DL0_ERROR_ACTION_FIR1_ACTION_LEN = P9A_MC_REG2_DL0_ERROR_ACTION_FIR1_ACTION_LEN, MC_REG2_DL0_ERROR_ACTION_FIR0_ACTION = P9A_MC_REG2_DL0_ERROR_ACTION_FIR0_ACTION, MC_REG2_DL0_ERROR_ACTION_FIR0_ACTION_LEN = P9A_MC_REG2_DL0_ERROR_ACTION_FIR0_ACTION_LEN, // MC_REG2_DL0_RMT_CONFIG MC_REG2_DL0_RMT_CONFIG_CFG_DLX2 = P9A_MC_REG2_DL0_RMT_CONFIG_CFG_DLX2, MC_REG2_DL0_RMT_CONFIG_CFG_DLX2_LEN = P9A_MC_REG2_DL0_RMT_CONFIG_CFG_DLX2_LEN, // MC_REG2_DL0_STATUS MC_REG2_DL0_STATUS_STS_TRAINING_STATE_MACHINE = P9A_MC_REG2_DL0_STATUS_STS_TRAINING_STATE_MACHINE, MC_REG2_DL0_STATUS_STS_TRAINING_STATE_MACHINE_LEN = P9A_MC_REG2_DL0_STATUS_STS_TRAINING_STATE_MACHINE_LEN, }; }; } // namespace mss #endif