RC_PM_PSS_ADC_ERROR SPIADC error bit asserted waiting for operation to complete. CHIP POLLCOUNT PSS_FFDC_REGISTERS CHIP TARGET_TYPE_PROC_CHIP CHIP HIGH CODE LOW RC_PM_PSS_ADC_WRITE_WHILE_BUSY SPI ADC was written while the bridge was busy. Cleared with coming reset. CHIP POLLCOUNT PSS_FFDC_REGISTERS CHIP TARGET_TYPE_PROC_CHIP CODE HIGH RC_PM_PSS_ADC_TIMEOUT SPIADC timed waiting to be quiesced. The SPIADC will be reset anyway so as to attempt to recover the interface. CHIP POLLCOUNT MAXPOLLS TIMEOUTUS PSS_FFDC_REGISTERS CHIP TARGET_TYPE_PROC_CHIP CHIP HIGH RC_PM_PSS_P2S_ERROR SPIP2S error bit asserted waiting for operation to complete. CHIP POLLCOUNT PSS_FFDC_REGISTERS CHIP TARGET_TYPE_PROC_CHIP CHIP HIGH CODE LOW