REG_FFDC_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_0 MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_1 MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_2 MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_3 MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_4 MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_0 MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_1 MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_2 MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_3 MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_4 MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_0 MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_1 MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_2 MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_3 MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_4 MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_0 MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_1 MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_2 MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_3 MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_4 REG_FFDC_MSS_DRAMINIT_TRAINING_ERROR_STATUS MCA_DDRPHY_PC_INIT_CAL_ERROR_P0 MCA_DDRPHY_DP16_RD_STATUS0_P0_0 MCA_DDRPHY_DP16_RD_STATUS0_P0_1 MCA_DDRPHY_DP16_RD_STATUS0_P0_2 MCA_DDRPHY_DP16_RD_STATUS0_P0_3 MCA_DDRPHY_DP16_RD_STATUS0_P0_4 MCA_DDRPHY_DP16_WR_ERROR0_P0_0 MCA_DDRPHY_DP16_WR_ERROR0_P0_1 MCA_DDRPHY_DP16_WR_ERROR0_P0_2 MCA_DDRPHY_DP16_WR_ERROR0_P0_3 MCA_DDRPHY_DP16_WR_ERROR0_P0_4 MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0 MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1 MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2 MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3 MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4 MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0 MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1 MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2 MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3 MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4 REG_FFDC_MSS_DRAMINIT_TRAINING_ERROR_INFO MCA_DDRPHY_APB_ERROR_STATUS0_P0 MCA_DDRPHY_APB_FIR_ERR0_P0 MCA_DDRPHY_APB_FIR_ERR1_P0 MCA_DDRPHY_APB_FIR_ERR2_P0 MCA_DDRPHY_APB_FIR_ERR3_P0 MCA_IOM_PHY0_DDRPHY_FIR_REG RC_MSS_DRAMINIT_TRAINING_PORT_FIR A PHY fir was lit up due to draminit training. There could be a problem with the training engine Checking fir bits 1-7 PHY_FIR DIMM_TARGET REG_FFDC_MSS_DRAMINIT_TRAINING_ERROR_INFO MCA_TARGET TARGET_TYPE_MCA REG_FFDC_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS MCA_TARGET TARGET_TYPE_MCA REG_FFDC_MSS_DRAMINIT_TRAINING_ERROR_STATUS MCA_TARGET TARGET_TYPE_MCA DIMM_TARGET HIGH DIMM_TARGET DIMM_TARGET CODE MEDIUM RC_MSS_DRAMINIT_TRAINING_MULTIPLE_ERRORS Multiple training steps failed for a given position within this calibration. FAILED_STEPS PORT_POSITION RANKGROUP_POSITION REG_FFDC_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS MCA_TARGET TARGET_TYPE_MCA REG_FFDC_MSS_DRAMINIT_TRAINING_ERROR_STATUS MCA_TARGET TARGET_TYPE_MCA DIMM_TARGET HIGH DIMM_TARGET DIMM_TARGET CODE MEDIUM RC_MSS_DRAMINIT_TRAINING_WR_LVL_ERROR Write Leveling has returned a fail for a given position within this calibration. PORT_POSITION RANKGROUP_POSITION REG_FFDC_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS MCA_TARGET TARGET_TYPE_MCA REG_FFDC_MSS_DRAMINIT_TRAINING_ERROR_STATUS MCA_TARGET TARGET_TYPE_MCA DIMM_TARGET HIGH DIMM_TARGET DIMM_TARGET CODE MEDIUM RC_MSS_DRAMINIT_TRAINING_INITIAL_PAT_WRITE_ERROR Initial pattern write has returned a fail for a given position within this calibration. PORT_POSITION RANKGROUP_POSITION REG_FFDC_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS MCA_TARGET TARGET_TYPE_MCA REG_FFDC_MSS_DRAMINIT_TRAINING_ERROR_STATUS MCA_TARGET TARGET_TYPE_MCA DIMM_TARGET HIGH DIMM_TARGET DIMM_TARGET CODE MEDIUM RC_MSS_DRAMINIT_TRAINING_DQS_ALIGNMENT_ERROR DQS Alignment has returned a fail for a given position within this calibration. PORT_POSITION RANKGROUP_POSITION REG_FFDC_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS MCA_TARGET TARGET_TYPE_MCA REG_FFDC_MSS_DRAMINIT_TRAINING_ERROR_STATUS MCA_TARGET TARGET_TYPE_MCA DIMM_TARGET HIGH DIMM_TARGET DIMM_TARGET CODE MEDIUM RC_MSS_DRAMINIT_TRAINING_DQS_ALIGNMENT_WORKAROUND_FAILED DQS Alignment has returned a fail for a given position within this calibration. Looping did not seem to fix the problem NUM_LOOPS RP ABORT_ON_ERROR REG_FFDC_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS MCA_TARGET TARGET_TYPE_MCA REG_FFDC_MSS_DRAMINIT_TRAINING_ERROR_STATUS MCA_TARGET TARGET_TYPE_MCA MCA_TARGET HIGH MCA_TARGET MCA_TARGET CODE MEDIUM RC_MSS_DRAMINIT_TRAINING_RD_CLK_SYS_CLK_ALIGNMENT_ERROR Read CLK to SYS CLK Alignment has returned a fail for a given position within this calibration. PORT_POSITION RANKGROUP_POSITION REG_FFDC_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS MCA_TARGET TARGET_TYPE_MCA REG_FFDC_MSS_DRAMINIT_TRAINING_ERROR_STATUS MCA_TARGET TARGET_TYPE_MCA DIMM_TARGET HIGH DIMM_TARGET DIMM_TARGET CODE MEDIUM RC_MSS_DRAMINIT_TRAINING_RD_CENTERING_ERROR Read Centering has returned a fail for a given position within this calibration. PORT_POSITION RANKGROUP_POSITION REG_FFDC_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS MCA_TARGET TARGET_TYPE_MCA REG_FFDC_MSS_DRAMINIT_TRAINING_ERROR_STATUS MCA_TARGET TARGET_TYPE_MCA DIMM_TARGET HIGH DIMM_TARGET DIMM_TARGET CODE MEDIUM RC_MSS_DRAMINIT_TRAINING_WR_CENTERING_ERROR Write centering has returned a fail for a given position within this calibration. PORT_POSITION RANKGROUP_POSITION REG_FFDC_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS MCA_TARGET TARGET_TYPE_MCA REG_FFDC_MSS_DRAMINIT_TRAINING_ERROR_STATUS MCA_TARGET TARGET_TYPE_MCA DIMM_TARGET HIGH DIMM_TARGET DIMM_TARGET CODE MEDIUM RC_MSS_DRAMINIT_TRAINING_INITIAL_COARSE_WR_ERROR Initial coarse write has returned a fail for a given position within this calibration. PORT_POSITION RANKGROUP_POSITION REG_FFDC_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS MCA_TARGET TARGET_TYPE_MCA REG_FFDC_MSS_DRAMINIT_TRAINING_ERROR_STATUS MCA_TARGET TARGET_TYPE_MCA DIMM_TARGET HIGH DIMM_TARGET DIMM_TARGET CODE MEDIUM RC_MSS_DRAMINIT_TRAINING_COARSE_RD_ERROR Coarse read has returned a fail for a given position within this calibration. PORT_POSITION RANKGROUP_POSITION REG_FFDC_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS MCA_TARGET TARGET_TYPE_MCA REG_FFDC_MSS_DRAMINIT_TRAINING_ERROR_STATUS MCA_TARGET TARGET_TYPE_MCA DIMM_TARGET HIGH DIMM_TARGET DIMM_TARGET CODE MEDIUM RC_MSS_DRAMINIT_TRAINING_CUSTOM_PATTERN_RD_ERROR Custom Pattern Read has returned a fail for a given position within this calibration. PORT_POSITION RANKGROUP_POSITION REG_FFDC_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS MCA_TARGET TARGET_TYPE_MCA REG_FFDC_MSS_DRAMINIT_TRAINING_ERROR_STATUS MCA_TARGET TARGET_TYPE_MCA DIMM_TARGET HIGH DIMM_TARGET CODE LOW RC_MSS_DRAMINIT_TRAINING_CUSTOM_PATTERN_WR_ERROR Custom Pattern Write has returned a fail for a given position within this calibration. PORT_POSITION RANKGROUP_POSITION REG_FFDC_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS MCA_TARGET TARGET_TYPE_MCA REG_FFDC_MSS_DRAMINIT_TRAINING_ERROR_STATUS MCA_TARGET TARGET_TYPE_MCA DIMM_TARGET HIGH DIMM_TARGET DIMM_TARGET CODE LOW RC_MSS_DRAMINIT_TRAINING_DIGITAL_EYE_ERROR Digital Eye has returned a fail for a given position within this calibration. PORT_POSITION RANKGROUP_POSITION REG_FFDC_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS MCA_TARGET TARGET_TYPE_MCA REG_FFDC_MSS_DRAMINIT_TRAINING_ERROR_STATUS MCA_TARGET TARGET_TYPE_MCA DIMM_TARGET HIGH DIMM_TARGET DIMM_TARGET CODE LOW RC_MSS_DRAMINIT_TRAINING_VREF_ERROR WR or RD VREF has returned a fail for a given position within this calibration. PORT_POSITION RANKGROUP_POSITION REG_FFDC_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS MCA_TARGET TARGET_TYPE_MCA REG_FFDC_MSS_DRAMINIT_TRAINING_ERROR_STATUS MCA_TARGET TARGET_TYPE_MCA DIMM_TARGET HIGH DIMM_TARGET DIMM_TARGET CODE LOW RC_MSS_DISABLED_BITS The PHY has disabled too many bits to continue (6 bits) DP REG_FFDC_MSS_DRAMINIT_TRAINING_ERROR_INFO MCA_TARGET TARGET_TYPE_MCA REG_FFDC_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS MCA_TARGET TARGET_TYPE_MCA MCA_TARGET HIGH DIMM_TARGET MEDIUM DIMM_TARGET DIMM_TARGET RC_MSS_FAILED_RDVREF_CAL A DP16 has failed read vREF calibration. If this fails, RDCNTR cal will also catch the fail REGISTER VALUE DIMM_TARGET REG_FFDC_MSS_DRAMINIT_TRAINING_ERROR_INFO MCA_TARGET TARGET_TYPE_MCA REG_FFDC_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS MCA_TARGET TARGET_TYPE_MCA MCA_TARGET HIGH RC_MSS_NO_DIMM_FOR_MAPPING Tried to map rank pairs on a port without any DIMMS FUNCTION MCA_TARGET CODE HIGH RC_MSS_INVALID_RANK_VECTOR_PASSED_IN Invalid vector of ranks passed in FUNCTION RANK_SIZE MCA_TARGET CODE HIGH RC_MSS_INVALID_RANK_PAIR Invalid rank pair passed into function RANK_PAIR FUNCTION MCA_TARGET CODE HIGH RC_MSS_NO_PRIMARY_RANK_FOUND_RP No primary rank in rank pair RANK_PAIR MCA_TARGET CODE HIGH RC_MSS_FAILED_WRVREF_CAL A DP16 has failed write VREF calibration REGISTER VALUE MASK DIMM_TARGET REG_FFDC_MSS_DRAMINIT_TRAINING_ERROR_INFO MCA_TARGET TARGET_TYPE_MCA REG_FFDC_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS MCA_TARGET TARGET_TYPE_MCA MCA_TARGET MCA_TARGET RC_MSS_RD_CTR_WORKAROUND_EMPTY_VECTOR An empty vector was passed into the find_median_and_sort function CODE HIGH RC_MSS_RDCLK_ALIGN_VECTOR_MISMATCH Size of disable bit vector is not the same as rd clk vector size BITVECTOR_SIZE RDCLK_SIZE CODE HIGH RC_MSS_WR_VREF_WORKAROUND_BIG_STEPS_OUTOFBOUNDS Makes sure that the values passed in were not out of range MAX_BIG_STEP ACTUAL_BIG_STEP CODE HIGH RC_MSS_WR_VREF_TRAIN_WORKAROUND_BIG_STEPS_OUTOFBOUNDS Makes sure that the values passed in were not out of range MAX_BIG_STEP ACTUAL_BIG_STEP CODE HIGH RC_MSS_WR_VREF_WORKAROUND_SMALL_STEPS_OUTOFBOUNDS Makes sure that the values passed in were not out of range MAX_SMALL_STEP ACTUAL_SMALL_STEP CODE HIGH RC_MSS_EXCEED_NUMBER_OF_DP There is an error iterating over the bad bits and assigning them to DP16 BAD_DP_NUM MAX_DP CODE HIGH TARGET MEDIUM RC_MSS_WR_VREF_DRAM_RECOVERY An informational callout for the WR VREF bad DRAM recovery workaround TARGET RP DRAM IS_BAD TARGET HIGH RC_MSS_RP_OUT_OF_RANGE An informational callout for rank-pair value out of range RP