ATTR_EXTERNAL_VRM_STEPSIZE
TARGET_TYPE_SYSTEM
Step size (binary in microvolts) to take upon external VRM voltage
transitions. The value set here must take into account where internal
VRMs are enabled or not as, when they are enabled, the step size must
account for the tracking (eg PFET strength recalculation) for the step.
Firmware provides a default value of 50mV if this attribute is zero.
Consumer: p9_pstate_parameter_block ->
p9_setup_evid
Pstate Parameter Block (PSPB) for PGPE
Provided by the Machine Readable Workbook after system characterization.
uint32
ATTR_EXTERNAL_VRM_TRANSITION_START_NS
TARGET_TYPE_SYSTEM
Delay (binary in nanoseconds) from the time the VRM receives the write
voltage command until the voltage actually moves. This value is used for
both increasing and decreasing transitions as part of the overall voltage
transition time calculation.
Firmware provides a default value of 8000ns (eg 8us)) if this attribute is
zero. Note: the smallest possible delay is limited to 1ns.
Consumer: p9_pstate_parameter_block ->
Pstate Parameter Block (PSPB) for PGPE
Provided by the Machine Readable Workbook after system characterization.
uint32
ATTR_EXTERNAL_VRM_TRANSITION_RATE_INC_UV_PER_US
TARGET_TYPE_SYSTEM
Transition rate (binary in microVolts per microsecond) of the VRM for an
increasing voltage transition. This is used as part of the overall voltage
transition time calculation
Firmware provides a default value of 10000 uV/us (eg 10mV/us) if this
attribute is zero. Note: the fastest possible rate is limited to 1uV/us.
Consumer: p9_pstate_parameter_block ->
Pstate Parameter Block (PSPB) for PGPE
Provided by the Machine Readable Workbook after system characterization.
uint32
ATTR_EXTERNAL_VRM_TRANSITION_RATE_DEC_UV_PER_US
TARGET_TYPE_SYSTEM
Transition rate (binary in microVolts per microsecond) of the VRM for an
decreasing voltage transition. This is used as part of the overall voltage
transition time calculation
Firmware provides a default value of 10000 uV/us (eg 10mV/us) if this
attribute is zero. Note: the fastest possible rate is limited to 1uV/us.
Consumer: p9_pstate_parameter_block ->
Pstate Parameter Block (PSPB) for PGPE
Provided by the Machine Readable Workbook after system characterization.
uint32
ATTR_EXTERNAL_VRM_TRANSITION_STABILIZATION_TIME_NS
TARGET_TYPE_SYSTEM
Time (binary in nanoseconds) to allow the voltage rail to stabilize before
considering the transition to be fully complete. This value is used for
both increasing and decreasing transitions as part of the overall voltage
transition time calculation.
Firmware provides a default value of 5000ns (5us) if this attribute is zero.
Note: the smallest delay is limited to 1ns.
Consumer: p9_pstate_parameter_block ->
Pstate Parameter Block (PSPB) for PGPE
Provided by the Machine Readable Workbook after system characterization.
uint32
ATTR_SAFE_MODE_NOVDM_UPLIFT_MV
TARGET_TYPE_PROC_CHIP
Attribute in place to allow override for boot mode voltage
Consumer: p9_setup_evid.C
uint32
ATTR_SAFE_MODE_VOLTAGE_MV
TARGET_TYPE_PROC_CHIP
Safe mode voltage in mv
This attribute is used within the hwp to update the
VDM config register.
Consumer: p9_setup_evid.C
Modified in p9_pstate_parameter_block
uint32
ATTR_SAFE_MODE_FREQUENCY_MHZ
TARGET_TYPE_PROC_CHIP
Safe mode frequency in MHZ
This attribute is used within the hwp to update QPPM DPLL
frequency register
Consumer: p9_setup_evid.C
Modified by p9_pstate_parameter_block
uint32
ATTR_AVSBUS_FREQUENCY
TARGET_TYPE_SYSTEM
AVSBus Clock Frequency (binary in KHz)
Consumer: p9_ocb_init.C
Overridden by the Machine Readable Workbook.
If default of 0 is read, HWP will set AVSBus frequency to 1MHz.
uint32
ATTR_VDD_AVSBUS_BUSNUM
TARGET_TYPE_PROC_CHIP
Defines the AVSBus (0 or 1) which has the core VDD rail VRM
Producer: Machine Readable Workbook
Consumers: p9_set_evid;
p9_set_voltage (tool);
p9_build_pstate_datablock ->
Pstate Parameter Block (PSPB) for PGPE
*MOST* systems use Bus 0 for VDD. If this is not the case, the value
must be appropriately set by the platform (eg MRWB or equivalent)
uint8
0
ATTR_VDN_AVSBUS_BUSNUM
TARGET_TYPE_PROC_CHIP
Defines the AVSBus (0 or 1) which has the chip VDN rail VRM
Producer: Machine Readable Workbook
Consumers: p9_set_evid;
p9_set_voltage (tool);
p9_build_pstate_datablock ->
Pstate Parameter Block (PSPB) for PGPE
*MOST* systems use Bus 1 for VDD. If this is not the case, the value
must be appropriately set by the platform (eg MRWB or equivalent)
uint8
1
ATTR_VCS_AVSBUS_BUSNUM
TARGET_TYPE_PROC_CHIP
Defines the AVSBus (0 or 1) which has the chip VCS rail VRM
Producer: Machine Readable Workbook
Consumers: p9_set_evid;
p9_set_voltage (tool);
p9_build_pstate_datablock ->
Pstate Parameter Block (PSPB) for PGPE
For systems where VCS is not connected via AVSBus, set to 0xFF.
uint8
0xFF
ATTR_VDD_AVSBUS_RAIL
TARGET_TYPE_PROC_CHIP
Defines the AVSBus rail selector number (0 - 15) for the VDD VRM on the bus
defined by ATTR_AVSBUS_VDD_BUSNUM.
Producer: Machine Readable Workbook
Consumers: p9_set_evid;
p9_set_voltage (tool);
p9_build_pstate_datablock ->
Pstate Parameter Block (PSPB) for PGPE
*MOST* systems use Rail 0 for VDD for the bus on which they are connected.
If this is not the case, the value must be appropriately set by the platform
(eg MRWB or equivalent)
uint8
0
ATTR_VDN_AVSBUS_RAIL
TARGET_TYPE_PROC_CHIP
Defines the AVSBus rail selector number (0 - 15) for the VDN VRM on the bus
defined by ATTR_AVSBUS_VDN_BUSNUM.
Producer: Machine Readable Workbook
Consumers:
p9_set_avsbus_voltage (tool);
p9_build_pstate_datablock ->
Pstate Parameter Block (PSPB) for PGPE
*MOST* systems use Rail 0 for VDN for the bus on which they are connected.
If this is not the case, the value must be appropriately set by the platform
(eg MRWB or equivalent)
uint8
0
ATTR_VCS_AVSBUS_RAIL
TARGET_TYPE_PROC_CHIP
Defines the AVSBus rail selector number (0 - 15) for the VCS VRM on the bus
defined by ATTR_AVSBUS_VCS_BUSNUM.
Producer: Machine Readable Workbook
Consumers:
p9_set_avsbus_voltage (tool);
p9_build_pstate_datablock ->
Pstate Parameter Block (PSPB) for PGPE
uint8
0xFF
ATTR_VCS_I2C_BUSNUM
TARGET_TYPE_PROC_CHIP
Defines the I2C bus number (0 - 15) that has the VCS VRM.
Producer: Machine Readable Workbook
Consumers: p9_set_evid;
p9_set_voltage (tool)
uint8
0xFF
ATTR_VDD_BOOT_VOLTAGE
TARGET_TYPE_PROC_CHIP
Voltage (binary in 1mV units) to apply to the VDD VRM for booting. Value
chosen is system dependent and is a combination of the part's Vital Product
Data (VPD) (typically the PowerSave value) and the minimum allowed for
correct operation of the fabric bus.
Producer: p9_setup_evid (first pass)
Consumer: p9_setup_evid (second pass)
uint32
ATTR_VDN_BOOT_VOLTAGE
TARGET_TYPE_PROC_CHIP
Voltage (binary in 1mV units) to apply to the VDN VRM for booting. Value
chosen is system dependent and is a combination of the part's Vital Product
Data (VPD) (typically the PowerSave value) and the minimum allowed for
correct operation of the fabric bus.
Producer: p9_setup_evid (first pass)
Consumer: p9_setup_evid (second pass)
uint32
ATTR_VCS_BOOT_VOLTAGE
TARGET_TYPE_PROC_CHIP
Voltage (binary in 1mV units) to apply to the VCS VRM for booting. Value
chosen is system dependent and is a combination of the part's Vital Product
Data (VPD) (typically the PowerSave value) and the minimum allowed for
correct operation of the fabric bus.
Producer: p9_setup_evid (first pass)
Consumer: p9_setup_evid (second pass)
uint32
ATTR_SPIPSS_FREQUENCY
TARGET_TYPE_SYSTEM
SPIPSS Clock Frequency (binary in KHz)
Valid range: 500KHz to 2500KHz
Consumer: p9_pss_init
Overridden by the Machine Readable Workbook.
If default of 0 is read, HWP will set SPIPSS frequency to 10MHz.
uint32
ATTR_PM_APSS_CHIP_SELECT
TARGET_TYPE_PROC_CHIP
Defines which of the PSS chip selects (0 or 1) that the APSS is connected
Provided by the Machine Readable Workbook.
Consumer: p9_pm_pss_init
uint8
NONE = 0xFF, CS0 = 0x00, CS1 = 0x01
ATTR_PROC_R_LOADLINE_VDD_UOHM
TARGET_TYPE_PROC_CHIP
Impedance (binary microOhms) of the load line from a processor VDD VRM to the
Processor Module pins. This value is applied to each processor instance.
Producer: Machine Readable Workbook (per the power subsystem design)
Consumers: p9_pstate_parameter_block
uint32
ATTR_PROC_R_DISTLOSS_VDD_UOHM
TARGET_TYPE_PROC_CHIP
Impedance (binary in microOhms) of the VDD distribution loss sense point
to the circuit. This value is applied to each processor instance.
Producer: Machine Readable Workbook (per the power subsystem design)
Consumers: p9_pstate_parameter_block
uint32
ATTR_PROC_VRM_VOFFSET_VDD_UV
TARGET_TYPE_PROC_CHIP
Offset voltage (binary in microvolts) to apply to the VDD VRM distribution
to the processor module. This value is applied to each processor instance.
Note: no loadline may be present in the system; thus, a value of 0 is
legal.
Producer: Machine Readable Workbook (per the power subsystem design)
Consumers: p9_pstate_parameter_block
uint32
ATTR_PROC_R_LOADLINE_VDN_UOHM
TARGET_TYPE_PROC_CHIP
Impedance (binary microOhms) of the load line from a processor VDN VRM to
the Processor Module pins. This value is applied to each processor
instance.
Note: no loadline may be present in the system; thus, a value of 0 is
legal.
Producer: Machine Readable Workbook (per the power subsystem design)
Consumers: p9_pstate_parameter_block
uint32
ATTR_PROC_R_DISTLOSS_VDN_UOHM
TARGET_TYPE_PROC_CHIP
Impedance (binary in microOhms) of the VDN distribution loss sense point
to the circuit. This value is applied to each processor instance.
Producer: Machine Readable Workbook (per the power subsystem design)
Consumers: p9_pstate_parameter_block
uint32
ATTR_PROC_VRM_VOFFSET_VDN_UV
TARGET_TYPE_PROC_CHIP
Offset voltage (binary in microvolts) to apply to the VDN VRM distribution
to the processor module. This value is applied to each processor instance.
Producer: Machine Readable Workbook (per the power subsystem design)
Consumers: p9_pstate_parameter_block
uint32
ATTR_PROC_R_LOADLINE_VCS_UOHM
TARGET_TYPE_PROC_CHIP
Impedance (binary microOhms) of the load line from a processor VCS VRM to
the Processor Module pins. This value is applied to each processor
instance.
Note: no loadline may be present in the system; thus, a value of 0 is
legal.
Producer: Machine Readable Workbook (per the power subsystem design)
Consumers: p9_pstate_parameter_block
uint32
ATTR_PROC_R_DISTLOSS_VCS_UOHM
TARGET_TYPE_PROC_CHIP
Impedance (binary in microOhms) of the VCS distribution loss sense point
to the circuit. This value is applied to each processor instance.
Producer: Machine Readable Workbook (via the power subsystem design per
system)
Consumer: p9_pstate_parameter_block
uint32
ATTR_PROC_VRM_VOFFSET_VCS_UV
TARGET_TYPE_PROC_CHIP
Offset voltage (binary in microvolts) to apply to the VCS VRM distribution
to the processor module. This value is applied to each processor instance.
Producer: Machine Readable Workbook (via the power subsystem design per
system)
Consumer: FSP
uint32
ATTR_FREQ_BIAS_ULTRATURBO
TARGET_TYPE_PROC_CHIP
UltraTurbo Frequency Bias - % of bias (signed twos complement in 0.5
percent steps) used in calculating the frequency associated with a Pstate
- both Global and Local.
Producer: Attribute Overrides by Lab/Mfg Characterization Team
Consumer: p9_pstate_parameter_block
int8
ATTR_FREQ_BIAS_TURBO
TARGET_TYPE_PROC_CHIP
Turbo Frequency Bias - % of bias (signed twos complement in 0.5 percent
steps) used in calculating the frequency associated with a Pstate - both
Global and Local.
Producer: Attribute Overrides by Lab/Mfg Characterization Team
Consumer: p9_pstate_parameter_block
int8
ATTR_FREQ_BIAS_NOMINAL
TARGET_TYPE_PROC_CHIP
Nominal Frequency Bias - % of bias (signed twos complement in 0.5 percent
steps) used in calculating the frequency associated with a Pstate - both
Global and Local.
Producer: Attribute Overrides by Lab/Mfg Characterization Team
Consumer: p9_pstate_parameter_block
int8
ATTR_FREQ_BIAS_POWERSAVE
TARGET_TYPE_PROC_CHIP
PowerSave Frequency Bias - % of bias (signed twos complement in 0.5 percent
steps) used in calculating the frequency associated with a Pstate - both
Global and Local.
Producer: Attribute Overrides by Lab/Mfg Characterization Team
Consumer: p9_pstate_parameter_block
int8
ATTR_VOLTAGE_EXT_VDD_BIAS_ULTRATURBO
TARGET_TYPE_PROC_CHIP
UltraTurbo VDD Voltage Bias - % of bias (signed twos complement in 0.5
percent steps) that is applied to the UltraTurbo VPD point used in
calculating the Global Pstate values.
Producer: Attribute Overrides by Lab/Mfg Characterization Team
Consumer: p9_pstate_parameter_block
int8
ATTR_VOLTAGE_EXT_VDD_BIAS_TURBO
TARGET_TYPE_PROC_CHIP
Turbo VDD Voltage Bias - % of bias (signed twos complement in 0.5 percent
steps) that is applied to the UltraTurbo VPD point used in calculating the
Global Pstate values.
Producer: Attribute Overrides by Lab/Mfg Characterization Team
Consumer: p9_pstate_parameter_block
int8
ATTR_VOLTAGE_EXT_VDD_BIAS_NOMINAL
TARGET_TYPE_PROC_CHIP
Nominal VDD Voltage Bias - % of bias (signed twos complement in 0.5 percent
steps) that is applied to the UltraTurbo VPD point used in calculating the
Global Pstate values.
Producer: Attribute Overrides by Lab/Mfg Characterization Team
Consumer: p9_pstate_parameter_block
int8
ATTR_VOLTAGE_EXT_VDD_BIAS_POWERSAVE
TARGET_TYPE_PROC_CHIP
PowerSave VDD Voltage Bias - % of bias (signed twos complement in 0.5
percent steps) that is applied to the UltraTurbo VPD point used in
calculating the Global Pstate values.
Producer: Attribute Overrides by Lab/Mfg Characterization Team
Consumer: p9_pstate_parameter_block
int8
ATTR_VOLTAGE_EXT_VCS_BIAS
TARGET_TYPE_PROC_CHIP
VCS Voltage Bias - % of bias (signed twos complement in 0.5 percent
steps) that is applied to the VCS value stored in the UltraTurbo VPD
point for setting the VCS rail.
Producer: Attribute Overrides by Lab/Mfg Characterization Team
Consumer: p9_pstate_parameter_block
Platform default: 0
int8
ATTR_VOLTAGE_EXT_VDN_BIAS
TARGET_TYPE_PROC_CHIP
VDN Voltage Bias - % of bias (signed twos complement in 0.5 percent
steps) that is applied to the VDN value stored in the VPD for setting the
VDN rail.
Producer: Attribute Overrides by Lab/Mfg Characterization Team
Consumer: p9_pstate_parameter_block
Platform default: 0
int8
ATTR_VOLTAGE_INT_VDD_BIAS_ULTRATURBO
TARGET_TYPE_PROC_CHIP
TODO (RTC 136996) NEED TO LOOK AT PERCENTAGE IMPLEMENTATION IN CME CODE AS
WELL AS THE IVRM VOLTAGE CALCULATION PROCESS
UltraTurbo Internal VDD Voltage Bias - % of bias (signed twos complement in
0.5 percent steps) that is applied to the voltage computed (Vout) as part
of the Local Pstate. Note: the Vin Effective that models the Vin to the
PFETs (i.e accounting for system parameter losses) may include biassing
based on ATTR_VOLTAGE_VDD_BIAS_ULTRATURBO.
Producer: Attribute Overrides by Lab/Mfg Characterization Team
Consumer: p9_pstate_parameter_block
Platform default: 0
int8
ATTR_VOLTAGE_INT_VDD_BIAS_TURBO
TARGET_TYPE_PROC_CHIP
TODO (RTC 136996) NEED TO LOOK AT PERCENTAGE IMPLEMENTATION IN CME CODE AS
WELL AS THE IVRM VOLTAGE CALCULATION PROCESS
TURBO Internal VDD Voltage Bias - % of bias (signed twos complement in 0.5
percent steps) that is applied to the voltage computed (Vout) as part of
the Local Pstate. Note: the Vin Effective that models the Vin to the PFETs
(i.e accounting for system parameter losses) may include biassing based on
ATTR_VOLTAGE_VDD_BIAS_TURBO.
Producer: Attribute Overrides by Lab/Mfg Characterization Team
Consumer: p9_pstate_parameter_block
Platform default: 0
int8
ATTR_VOLTAGE_INT_VDD_BIAS_NOMINAL
TARGET_TYPE_PROC_CHIP
TODO (RTC 136996) NEED TO LOOK AT PERCENTAGE IMPLEMENTATION IN CME CODE AS
WELL AS THE IVRM VOLTAGE CALCULATION PROCESS
Nominal Internal VDD Voltage Bias - % of bias (signed twos complement in
0.5 percent steps) that is applied to the voltage computed (Vout) as part
of the Local Pstate. Note: the Vin Effective that models the Vin to the
PFETs (i.e accounting for system parameter losses) may include biassing
based on ATTR_VOLTAGE_VDD_BIAS_NOMINAL.
Producer: Attribute Overrides by Lab/Mfg Characterization Team
Consumer: p9_pstate_parameter_block
Platform default: 0
int8
ATTR_VOLTAGE_INT_VDD_BIAS_POWERSAVE
TARGET_TYPE_PROC_CHIP
TODO (RTC 136996) NEED TO LOOK AT PERCENTAGE IMPLEMENTATION IN CME CODE AS
WELL AS THE IVRM VOLTAGE CALCULATION PROCESS
PowerSave Internal VDD Voltage Bias - % of bias (signed twos complement in
0.5 percent steps) that is applied to the voltage computed (Vout) as part of
the Local Pstate. Note: the Vin Effective that models the Vin to the PFETs
(i.e accounting for system parameter losses) may include biassing based on
ATTR_VOLTAGE_VDD_BIAS_POWERSAVE.
Producer: Attribute Overrides by Lab/Mfg Characterization Team
Consumer: p9_pstate_parameter_block
Platform default: 0
int8
ATTR_STOP4_DISABLE
TARGET_TYPE_SYSTEM
Control CME response to execution of PowerPC STOP instruction
if OFF, treat STOP4 as STOP4
if ON, treat STOP4 as STOP2
Producer: Work-around tools
Consumer: p9_hcode_image_build.C
Platform default: OFF
uint8
OFF=0, ON=1
ATTR_STOP5_DISABLE
TARGET_TYPE_SYSTEM
Control CME response to execution of PowerPC STOP instruction
if OFF, treat STOP5 as STOP5
if ON, treat STOP5 as STOP4
Producer: ???
Consumer: p9_hcode_image_build.C
Platform default: ON
uint8
OFF=0, ON=1
ATTR_STOP8_DISABLE
TARGET_TYPE_SYSTEM
Control CME response to execution of PowerPC STOP instruction
if OFF, treat STOP8 as STOP8
if ON, treat STOP8 as STOP4
Producer: Work-around tools
Consumer: p9_hcode_image_build.C
Platform default: OFF
uint8
OFF=0, ON=1
ATTR_STOP11_DISABLE
TARGET_TYPE_SYSTEM
Control CME response to execution of PowerPC STOP instruction
if OFF, treat STOP11 as STOP11
if ON, treat STOP11 as STOP8
Producer: Work-around tools
Consumer: p9_hcode_image_build.C
Platform default: OFF
uint8
OFF=0, ON=1
ATTR_SYSTEM_CORE_PERIODIC_QUIESCE_DISABLE
TARGET_TYPE_SYSTEM
Disable the Core Periodic Quiesce Hang Buster function
Producer: Lab tools
Consumer: p9_hcode_image_build.C -> SGPE Hcode -> CME Hcode
Platform default: OFF
uint8
OFF=0, ON=1
ON
ATTR_SYSTEM_POUNDV_VALIDITY_HALT_DISABLE
TARGET_TYPE_SYSTEM
Disables the validity checking of #V VPD content from causing
IPL failures.
OFF: Will enable PStates given all validity checks pass. If
validity checks fail, the a failure is log and error reaction
will occur (eg IPL failure)
ON: Will disable #V validity checking of #V from causing IPL
to halt. Validity check failures will cause error logs and
Pstates (including other dependent functions) will be
disabled.
Producer: Override
Consumers: p9_pstate_parameter_block
uint8
OFF=0, ON=1
ATTR_SYSTEM_WOF_DISABLE
TARGET_TYPE_SYSTEM
Disables Work Load Optimized Frequency (WOF) algorithms to
modify frequency based on active core count and other inputs.
OFF: Will enable WOF given all validity check pass. If
validity checks fail, WOF will be disabled for the
present IPL.
ON: Will disable WOF
OFF_SKIP_DD: Same as OFF but skips any validity checking of the chip
design level (lab use only).
Producer: Override
Consumers: p9_build_pstate_datablock ->
Pstate Parameter Block (PSPB) for PGPE/OCC
uint8
OFF=0, ON=1, OFF_SKIP_DD=2
ATTR_SYSTEM_WOV_UNDERV_DISABLE
TARGET_TYPE_SYSTEM
Enables Workload Optimized Voltage (WOV) undervolting algorithms which
dynamically modify voltage below the value calculated from VPD.
OFF: Will enable WOV undervolting given all validity check pass. If
validity checks fail, WOV undervolting will be disabled for the
present IPL.
ON: Will disable WOV undervolting
Producer: Override
Consumers: p9_build_pstate_datablock ->
Pstate Parameter Block (PSPB) for PGPE/OCC
uint8
OFF=0, ON=1
ATTR_WOV_UNDERV_FORCE
TARGET_TYPE_PROC_CHIP
Overrides VPD_UNDERVOLT_TEST value to 1. The VPD_UNDERVOLT_TEST is
set to 1 by mSLT or MFT, and means that undervolting test was run and passed on the
part. However, for older parts, the field will be set to 0, so to force enablement of
undervolting on older parts, this attribute can be set to override the VPD_UNDERVOLT_TEST.
ON: Will override VPD_UNDERVOLT_TEST value to 1.
OFF: Will not override VPD_UNDERVOLT_TEST
Producer: Override
Consumers: p9_build_pstate_datablock ->
Pstate Parameter Block (PSPB) for PGPE/OCC
uint8
OFF=0, ON=1
ATTR_SYSTEM_WOV_OVERV_DISABLE
TARGET_TYPE_SYSTEM
Enables Workload Optimized Voltage (WOV) undervolting algorithms which
dynamically modify voltage below the value calculated from VPD.
OFF: Will enable WOV overvolting given all validity check pass. If
validity checks fail, WOV overvolting will be disabled for the
present IPL.
ON: Will disable WOV overvolting
Producer: Override
Consumers: p9_build_pstate_datablock ->
Pstate Parameter Block (PSPB) for PGPE/OCC
uint8
OFF=0, ON=1
ATTR_SYSTEM_IVRM_DISABLE
TARGET_TYPE_SYSTEM
Disables IVRM enablement in the system
Producer: MRW
Consumers: p9_build_pstate_datablock ->
Pstate Parameter Block (PSPB) for PGPE/OCC
CME Quad Pstate Region (CQPR) for CM Quad Manager
uint8
OFF=0, ON=1
ATTR_WOF_ENABLE_FRATIO
TARGET_TYPE_SYSTEM
If wof_enabled, defines the Frequency Ratio calculation performed.
(THIS IS NOT SUPPORTED IN P9 GA1!).
uint8
FIXED=0, STEPPED=1
ATTR_WOF_ENABLE_VRATIO
TARGET_TYPE_SYSTEM
If wof_enabled, defines the Voltage Ratio calculation performed.
THIS IS NOT SUPPORTED AT PRESENT. GA1 SUPPORT IS TBD).
uint8
FIXED=0, CALCULATED=1
ATTR_WOF_VRATIO_SELECT
TARGET_TYPE_SYSTEM
If wof_enabled AND ATTR_WOF_ENABLE_VRATIO = CALCULATED, this attribute
selects the Vratio calculation type.
ACTIVE_CORES: Vratio is the number of active cores to the
number of good cores
FULL: Vratio is Vaverage to Vclip(Fclip) where Vclip(Fclip) is
the normal interpolated regulator voltage (including load line uplife @ RDP
current) derated with presently measured Idd current (from the AVSBus) and
the loadline.
uint8
ACTIVE_CORES=0, FULL=1
ATTR_WOV_SAMPLE_125US
TARGET_TYPE_PROC_CHIP
If WOV undervolting and/or WOF overvolting is enabled, then this overrides default
period at which the undervolting and/or overvolting is run.
If 0, then will interally default to 2(~250us), and is also the minimum value
uint32
ATTR_WOV_MAX_DROOP_10THPCT
TARGET_TYPE_PROC_CHIP
If WOV undervolting and/or WOF overvolting is enabled, then this is used to
used as a check for maximum frequency loss. If frequency in tenths of percentage
is below this value, then an error is logged and WOV is disabled.
uint32
ATTR_WOV_UNDERV_VMIN_MV
TARGET_TYPE_PROC_CHIP
Minimum voltage(floor) that regulator voltage is set to whether undervolting or not.
If 0, the Psafe computed voltage uplifted by the loadline*PowerSave RDP current is used.
This implies that no undervolting can happen at Psafe, and very little undervolting
slightly above Psafe frequency (slightly lower Pstate).
Otherwise, setting this parameter higher than the (default) Psafe voltage effectively
changes the Pstate table, raising any Pstate voltage to this value.
uint16
ATTR_WOV_UNDERV_LIMIT_ALGORITHM
TARGET_TYPE_PROC_CHIP
Defines the algorithm used to set the voltage to quit undervolting.
If 0, then value specified by ATTR_WOV_UNDERV_VMIN_MV attribute is used.
UNDERV_VMIN(default): Stops undervolting below the value specified by
ATTR_WOV_UNDERV_VMIN_MV.
UNDERV_LIMIT: Learns the value of the undervolting limit based on part VPD
TURBO: Stops undervolting below the TURBO VPD voltage.
NOMINAL: Stops undervolting below the NOMINIAL VPD voltage.
uint8
UNDERV_VMIN=0, UNDERV_LIMIT=1, TURBO=2, NOMINAL=3
ATTR_WOV_UNDERV_LIMIT_MV
TARGET_TYPE_PROC_CHIP
The lowest voltage below at which undervolting stops.
If 0, then this is calculated using the value provided by the attribute
ATTR_WOV_UNDERV_LIMIT_10THPCT.
uint16
ATTR_WOV_UNDERV_LIMIT_10THPCT
TARGET_TYPE_PROC_CHIP
Used to calculate the value for ATTR_WOV_UNDERV_LIMIT_MV, if
ATTR_WOV_UNDERV_LIMIT_MV is set to 0. The value is specified in tenths of
percent
If 0, then default value of 50(5%)
Value can range from 1(0.1%) to 250(25%).
uint8
ATTR_WOV_OVERV_VMAX_SETPOINT_MV
TARGET_TYPE_PROC_CHIP
Maximum regulator voltage allowed without exceeding the technology Vmax
at the chip pins.
If, 0, then default value of 1150(1.15V)
uint16
ATTR_WOV_UNDERV_STEP_INCR_10THPCT
TARGET_TYPE_PROC_CHIP
If WOV undervolting is enabled, then this specifies the amount by which to
increment percentage of undervolt amount. The value is specified in tenths
of percentage(0.1%).
If 0, then default value of 0.5%(5) is used.
Value can range from 1(0.1%) to 20(2%). Values greater than 20 are
clipped to 20(2%)
uint8
ATTR_WOV_UNDERV_STEP_DECR_10THPCT
TARGET_TYPE_PROC_CHIP
If WOV undervolting is enabled, then this specifies the amount by which to
decrement percentage of undervolt amount. The value is specified in tenths
of percentage(0.1%).
If 0, then default value of 0.5%(5) is used.
Value can range from 1(0.1%) to 20(2%). Values greater than 20 are
clipped to 20(2%)
uint8
ATTR_WOV_UNDERV_MAX_10THPCT
TARGET_TYPE_PROC_CHIP
If WOV undervolting is enabled, then this specifies the maximum amount
of undervolt percentage. The value is specified in tenths
of percentage(0.1%).
If, 0, then default value of 10%(100) is used.
Value can range from 10(1%) to 255(25.5%). For values between 1(0.1%) and 9(0.9%)
,value of 10(1%) will be used.
uint8
ATTR_WOV_UNDERV_PERF_LOSS_THRESH_10THPCT
TARGET_TYPE_PROC_CHIP
If WOV undervolting is enabled, then this specifies the maximum amount
of performance loss at which undervolting increments are stopped(and may be reduced).
The value is specified in tenths of percentage(0.1%).
If, 0, then default value of 0.5%(5) is used.
Value can range from 1(0.1%) to 20(2%). All other values will be
clipped to 20(2%).
uint8
ATTR_WOV_OVERV_STEP_INCR_10THPCT
TARGET_TYPE_PROC_CHIP
If WOV overvolting is enabled, then this specifies the amount by which to
increment percentage of overvolt amount. The value is specified in tenths
of percentage(0.1%).
If 0, then default value of 0.5%(5) is used.
Value can range from 1(0.1%) to 20(2%). Values greater than 20 are
clipped to 20(2%)
uint8
ATTR_WOV_OVERV_STEP_DECR_10THPCT
TARGET_TYPE_PROC_CHIP
If WOV overvolting is enabled, then this specifies the amount by which to
decrement percentage of overvolt amount. The value is specified in tenths
of percentage(0.1%).
If 0, then default value of 0.5%(5) is used.
Value can range from 1(0.1%) to 20(2%). Values greater than 20 are
clipped to 20(2%)
uint8
ATTR_WOV_OVERV_MAX_10THPCT
TARGET_TYPE_PROC_CHIP
If WOV overvolting is enabled, then this specifies the maximum amount
of overvolt percentange. The value is specified in tenths
of percentage(0.1%).
If, 0, then default value of 0(0%) is used.
Value can range from 1(0.1%) to 100(10%). Values greater than 100 are
clipped to 100(10%)
uint8
ATTR_PBAX_GROUPID
TARGET_TYPE_PROC_CHIP
Receive PBAX Groupid. Value that indicates this PBA's PBAX Group affinity.
This is matched to pbax_groupid of the PMISC Address phase.
Provided by the Machine Readable Workbook.
Platform default: Nimbus systems = 0
uint8
ATTR_PBAX_CHIPID
TARGET_TYPE_PROC_CHIP
Receive PBAX Chipid. Value that indicates this PBA's PBAX Chipid within
the PBAX node. Is matched to pbax_chipid of the Address phase if
pbax_type=unicast.
Provided by the Machine Readable Workbook.
Platform default: Nimbus systems - set so value in ATTR_FABRIC_GROUP_ID
uint8
ATTR_PBAX_BRDCST_ID_VECTOR
TARGET_TYPE_PROC_CHIP
Receive PBAX Broadcast Group. Vector that is indexed when decoded PMISC
pbax_type=broadcast with the decoded PMISC pbax_chipid value. If the
bit in this vector at the decoded bit location is a 1, then this receive
engine will participate in the broadcast operation.
Override attribute. Platform value of 0 indiates the OCC firmware will
perform this function.
uint8
ATTR_POUNDV_BUCKET_NUM_OVERRIDE
TARGET_TYPE_EQ
1 if override of poundv bucket num is available.
0 if override is unavailable.
uint8
ATTR_POUNDV_BUCKET_NUM
TARGET_TYPE_EQ
Attribute in place to allow override of which POUNDV
bucket to use to set power management data.
1 = Bucket A
2 = Bucket B
3 = Bucket C
4 = Bucket D
5 = Bucket E
6 = Bucket F
uint8
ATTR_POUNDV_BUCKET_DATA
TARGET_TYPE_EQ
Power Management data for Quad targets. Stored as an array of bytes.
The data is read directly from VPD and stored in this attribute without
being altered.
NOTE: you may need to handle correcting endiannessif you are using this
attribute.
uint8
61
ATTR_POUNDW_BUCKET_DATA
TARGET_TYPE_EQ
Power Management data for Quad targets. Stored as an array of bytes.
The data is read directly from VPD and stored in this attribute without
being altered.
NOTE: you may need to handle correcting endianness if you are using this
attribute.
uint8
135
ATTR_WOF_TABLE_DATA
TARGET_TYPE_SYSTEM
WOF data from PNOR which contains WOF header data + VFRT data (vfrt header +
data for 8 Vdn, 21Vdd and 6 Quads)
Consumed by p9_pstate_parameter_block procedure
uint8
131072
ATTR_DUMP_STOP_INFO_SUPPRESS_ERROR_TRACE
TARGET_TYPE_PROC_CHIP
if set to 1, FAPI_ERR records are suppressed from being produced by
p9_dump_stop_info.
uint8
ATTR_DUMP_STOP_INFO_ENABLE_ERRORLOG
TARGET_TYPE_PROC_CHIP
if set to 1, p9_dump_stop_info output will be written to error logs
uint8
ATTR_SYSTEM_VDM_DISABLE
TARGET_TYPE_SYSTEM
Disables the enablement of Voltage Droop Monitors (VDM) in the system.
Producer: MRW
Consumers:
p9_pstate_parameter_block to clear flag for CME QuadManager Hcode
reaction
uint8
OFF = 0x00, ON = 0x01
OFF
ATTR_VDM_DROOP_SMALL_OVERRIDE
TARGET_TYPE_SYSTEM
Voltage Droop Monitor (VDM) Small Threshold Select Value per VPD point
The enum indicates a negative value below the VDM setting that will
trigger a small droop event.
Array of 5 entries:
0 = PowerSave, 1 = Nominal; 2 = Turbo; 3 = UltraTurbo; 4 = Enable
If index 4 is non-zero, the other entries are considered valid.
Producer: Override
uint8
OFF = 0x00,
8mV = 0x01,
16mV = 0x02,
24mV = 0x03,
32mV = 0x04,
40mV = 0x05,
48mV = 0x06,
56mV = 0x07,
64mV = 0x08,
72mV = 0x09,
80mV = 0x0A,
88mV = 0x0B,
92mV = 0x0C,
96mV = 0x0D
5
ATTR_VDM_DROOP_LARGE_OVERRIDE
TARGET_TYPE_SYSTEM
Voltage Droop Monitor (VDM) Large Threshold Select Value per VPD point
The enum indicates a negative value below the VDM setting that will
trigger a large droop event.
Array of 5 entries:
0 = PowerSave, 1 = Nominal; 2 = Turbo; 3 = UltraTurbo; 4 = Enable
If index 4 is non-zero, the other entries are considered valid.
Producer: Override
uint8
OFF = 0x00,
8mV = 0x01,
16mV = 0x02,
24mV = 0x03,
32mV = 0x04,
40mV = 0x05,
48mV = 0x06,
56mV = 0x07,
64mV = 0x08,
72mV = 0x09,
80mV = 0x0A,
88mV = 0x0B,
92mV = 0x0C,
96mV = 0x0D
5
ATTR_VDM_DROOP_EXTREME_OVERRIDE
TARGET_TYPE_SYSTEM
Voltage Droop Monitor (VDM) Extreme Threshold Select Value per VPD point.
The enum indicates a negative value below the VDM setting that will
trigger an extreme droop event.
Array of 5 entries:
0 = PowerSave, 1 = Nominal; 2 = Turbo; 3 = UltraTurbo; 4 = Enable
If index 4 is non-zero, the other entries are considered valid.
Producer: Override
uint8
OFF = 0x00,
8mV = 0x01,
16mV = 0x02,
24mV = 0x03,
32mV = 0x04,
40mV = 0x05,
48mV = 0x06,
56mV = 0x07,
64mV = 0x08,
72mV = 0x09,
80mV = 0x0A,
88mV = 0x0B,
92mV = 0x0C,
96mV = 0x0D
5
ATTR_VDM_OVERVOLT_OVERRIDE
TARGET_TYPE_SYSTEM
Voltage Droop Monitor (VDM) OverVoltage Threshold Select Value per VPD
point. The enum indicates a positive value above the VDM setting that will
indicate an overvolt droop condition.
Array of 5 entries:
0 = PowerSave, 1 = Nominal; 2 = Turbo; 3 = UltraTurbo; 4 = Enable
If index 4 is non-zero, the other entries are considered valid.
Producer: Override
uint8
FORCE = 0x00,
8mV = 0x01,
16mV = 0x02,
24mV = 0x03,
32mV = 0x04,
40mV = 0x05,
48mV = 0x06,
56mV = 0x07,
64mV = 0x08
5
ATTR_VDM_SMALL_FREQ_DROP_N_S_OVERRIDE
TARGET_TYPE_SYSTEM
DPLL response override of the respective #W VPD content for a Voltage Droop
Monitor (VDM) Small Frequency Drop (eg Normal to Small). Values are in
1/32ths with legal values being of N being less than or equal to 8.
Array of 5 entries:
0 = PowerSave, 1 = Nominal; 2 = Turbo; 3 = UltraTurbo; 4 = Enable
If index 4 is non-zero, the other entries are considered valid.
Producer: Override
uint8
5
ATTR_VDM_LARGE_FREQ_DROP_N_L_OVERRIDE
TARGET_TYPE_SYSTEM
DPLL response override of the respective #W VPD content for a Voltage Droop
Monitor (VDM) Large Frequency Drop (eg Normal to Large). Values are in
1/32ths with legal values being of N being less than or equal to 8.
Array of 5 entries:
0 = PowerSave, 1 = Nominal; 2 = Turbo; 3 = UltraTurbo; 4 = Enable
If index 4 is non-zero, the other entries are considered valid.
Producer: Override
uint8
5
ATTR_VDM_FREQ_RETURN_L_S_OVERRIDE
TARGET_TYPE_SYSTEM
DPLL response override of the respective #W VPD content for returning
from a Large Frequency Droop value to the Small value. Values are in
1/32ths with legal values being of N being less than or equal to 8.
Array of 5 entries:
0 = PowerSave, 1 = Nominal; 2 = Turbo; 3 = UltraTurbo; 4 = Enable
If index 4 is non-zero, the other entries are considered valid.
Producer: Override
uint8
5
ATTR_VDM_FREQ_RETURN_S_N_OVERRIDE
TARGET_TYPE_SYSTEM
DPLL response override of the respective #W VPD content for returning
from a Small Frequency Droop value to the Normal value. Values are in
1/32ths with legal values being of N being less than or equal to 8.
Array of 5 entries:
0 = PowerSave, 1 = Nominal; 2 = Turbo; 3 = UltraTurbo; 4 = Enable
If index 4 is non-zero, the other entries are considered valid.
Producer: Override
uint8
5
ATTR_VDM_EXTREME_THOTTLE_ENABLE
TARGET_TYPE_SYSTEM
Controls the enablement of Voltage Droop Monitors (VDM) to throttle
the core upon an extreme droop event.
Producer: Machine Readable Workbook
Consumers:
p9_hcode_image_build to set flag for CME QuadManager Hcode
reaction
uint8
OFF = 0x00, ON = 0x01
ATTR_VDM_FMAX_OVERRIDE_KHZ
TARGET_TYPE_SYSTEM
Producer: Override
uint16
5
ATTR_VDM_FMIN_OVERRIDE_KHZ
TARGET_TYPE_SYSTEM
Producer: Override
uint16
5
ATTR_VDM_VID_COMPARE_OVERRIDE_MV
TARGET_TYPE_SYSTEM
Voltage Droop Monitor (VDM) Voltage Compare Voltage to expect when no
droop is present (binary in mV). A default value of 0 indicates no
override
Array of 5 entries:
0 = PowerSave, 1 = Nominal; 2 = Turbo; 3 = UltraTurbo; 4 = Enable
Producer: Override
uint8
5
ATTR_VDM_VID_COMPARE_BIAS_0P5PCT
TARGET_TYPE_PROC_CHIP
VDM Voltage Compare Bias - % of bias (signed twos complement in
0.5 percent steps) that is applied to the #W VDM VID Compare before
placement in the respective Pstate Paramter Blocks that will be consumed
by Hcode.
Array of 4 entries:
0 = PowerSave, 1 = Nominal; 2 = Turbo; 3 = UltraTurbo
Producer: Override
int8
4
ATTR_DPLL_VDM_RESPONSE
TARGET_TYPE_SYSTEM
Indicates the response of the DPLL frequency upon VDM events if
ATTR_SYSTEM_VDM_DISABLE is not ON.
NONE -> DPLL Mode 2
DROOP_PROTECT -> DPLL Mode 3
DROOP_PROTECT_OVERVOLT -> DPLL Mode 3.5
DYNAMIC -> DPLL Mode 4
DYNAMIC_PROTECT -> DPLL Mode 5
Producer: MRWB.
uint8
DROOP_PROTECT = 0x00,
DROOP_PROTECT_OVERVOLT = 0x01,
DYNAMIC = 0x02,
DYNAMIC_PROTECT = 0x03,
NONE = 0x04
ATTR_IVRM_DEADZONE_MV
TARGET_TYPE_SYSTEM
Override value for the value of the deadzone where the iVRM cannot regulate
(binary in millivolts).
The deadzone is the difference between the voltage from the external VRM
after load line and other losses are removed and the request regulation
voltage. If this difference is smaller than the value of this attribute,
the iVRM is forced in to bypass to use the external voltage.
Producer: Override
Consumer: p9_pstate_parameter_block ->
CME pstate parameter block
PGPE pstate parameter block
Handling: p9_pstate_parameter_block reads this attribute. If zero, the
value of 50 (0x32) is used. If non-zero, this value is used.
uint8
ATTR_IVRM_STRENGTH_LOOKUP
TARGET_TYPE_SYSTEM
Override Lookup table used to as part of determining the PFET width to use
based on the voltage across the PFET header.
Producer: Override
Consumer: p9_pstate_parameter_block ->
CME pstate parameter block
PGPE pstate parameter block
uint8
64
ATTR_IVRM_VIN_MULTIPLIER
TARGET_TYPE_SYSTEM
Overide the hardcoded multiplier table used with the strength
lookup to determine the IVRM PFET width.
Producer: Override
Consumer: p9_pstate_parameter_block ->
CME pstate parameter block
PGPE pstate parameter block
uint8
64
ATTR_IVRM_VIN_MAX_MV
TARGET_TYPE_SYSTEM
Override voltage maximum that is used for the IVRM PFET width
calculation. Setting to 0 will use the default 1100mV. Setting this to a
non-zero value will cause this value to be used instead.
Producer: Override
Consumer: p9_pstate_parameter_block ->
CME pstate parameter block
PGPE pstate parameter block
uint16
ATTR_IVRM_STEP_DELAY_NS
TARGET_TYPE_SYSTEM
Override time (in nanoseconds) to wait between IVRM steps that
are part of a larger transition to the ultimate destination voltage.
Producer: Override
Consumer: p9_pstate_parameter_block ->
CME pstate parameter block
PGPE pstate parameter block
uint16
ATTR_IVRM_STABILIZATION_DELAY_NS
TARGET_TYPE_SYSTEM
Override time (in nanoseconds) to wait after the iVRM indicates "done" in
the event extra time is required. A zero value will have the hardcoded
default to be used.
Producer: MRWB.
Consumer: p9_pstate_parameter_block ->
CME pstate parameter block
PGPE pstate parameter block
uint16
ATTR_TDP_RDP_CURRENT_FACTOR
TARGET_TYPE_PROC_CHIP
TODO RTC 157943 -- Placeholder description
This overrides the RDP to TDP Scaling Factor IQ VPD field that is used for
Workload Optimized Frequency (WOF) voltage uplifting.
Consumers: p9_pstate_parameter_block
uint32
ATTR_SYSTEM_RESCLK_DISABLE
TARGET_TYPE_SYSTEM
Disables the enablement of resonant clocking in the system.
Producer: Override
Consumers:
p9_pstate_parameter_block to clear the flag for CME QuadManager Hcode
reaction
uint8
OFF = 0x00, ON = 0x01
ATTR_SYSTEM_RESCLK_STEP_DELAY
TARGET_TYPE_SYSTEM
Minimum delay (in nanoseconds) between clock grid management transition
steps
Producer: MRWB from clock team
Consumers: p9_build_pstate_datablock ->
CME Quad Pstate Region (CQPR) for CM Quad Manager
Platform default: 0
uint16
ATTR_SYSTEM_RESCLK_FREQ_REGIONS
TARGET_TYPE_PROC_CHIP
Frequency discontinuity region points that defines the lower edge of a
Resonant Region and where F[i] LT F[i+1] and 0 LE i LE 7.
This yields:
ATTR_RESCLK_FREQ_REGIONS[0] LE Region 0 LT ATTR_RESCLK_FREQ_REGIONS[1]
ATTR_RESCLK_FREQ_REGIONS[1] LE Region 1 LT ATTR_RESCLK_FREQ_REGIONS[2]
ATTR_RESCLK_FREQ_REGIONS[2] LE Region 2 LT ATTR_RESCLK_FREQ_REGIONS[3]
etc.
Producer: MRWB from clock team
Consumers: p9_pstate_parameter_block
uint16
8
ATTR_SYSTEM_RESCLK_FREQ_REGION_INDEX
TARGET_TYPE_PROC_CHIP
Defines the index into ATTR_RESCLK_VALUE[] to use for the frequency region.
The frequency associated with the region is defined by
ATTR_RESCLK_FREQ_REGIONS[i] and ATTR_RESCLK_FREQ_REGIONS[i+1] for
0 LE i LE 7.
Producer: MRWB from clock team
Consumers: p9_pstate_parameter_block
uint8
8
ATTR_SYSTEM_RESCLK_VALUE
TARGET_TYPE_PROC_CHIP
Array of Clock strength values that will we written in QACCR by CME Hcode
Producer: MRWB from clock team
Consumers: p9_pstate_parameter_block
uint16
64
ATTR_SYSTEM_RESCLK_L3_VALUE
TARGET_TYPE_PROC_CHIP
Array of L3 Clock strength values to be used going between "High and Normal
Voltage" and "Low Voltage" mode. Low Voltage mode is define by
ATTR_RESCLK_L3_VOLTAGE_THRESHOLD_MV.
Entry 0 = "High and Normal Voltage" setting
Entry 3 = "High and Normal Voltage" setting
Entry 1 = transitional setting defined by the clock team
Entry 2 = transitional setting defined by the clock team
Contents of each entry will be written directly into L3 control bits in the
QACCR(16:23) a RMW operations. If the circuits demand a grey code whereby
only 1 bit of this field can change at a time, the entries must be deal with
such encoding. The Hcode that these values does not perform that function;
it merely steps from 0->3 when going below the voltage defined by
ATTR_RESCLK_L3_VOLTAGE_THRESHOLD_MV and then steps 3->0 when going at or
above the voltage defined by ATTR_RESCLK_L3_VOLTAGE_THRESHOLD_MV.
Producer: MRWB from clock team
Consumers: p9_pstate_parameter_block
uint8
4
ATTR_SYSTEM_RESCLK_L3_VOLTAGE_THRESHOLD_MV
TARGET_TYPE_PROC_CHIP
Voltage value (in millivolts) whereby voltage below this value will have
the L3 clock strength moved to "Low" mode while values at or above this
value will have the L3 clock strength moved to "High" mode. The L3 clock
strength values put in the hardware for this mode transtion are defined by
ATTR_RESCLK_L3_VALUE.
Producer: MRWB from clock team
Consumers: p9_pstate_parameter_block
uint16
ATTR_SYSTEM_RING_DBG_MODE
Debug modes supported for CME/SGPE Scan layout in HOMER.
TARGET_TYPE_SYSTEM
uint8
SCAN_RING_NO_DEBUG = 0x00, SCAN_RING_TRACE_DEBUG = 0x01, SCAN_RING_DEEP_DEBUG = 0x02
ATTR_PERF_24x7_INVOCATION_TIME_MS
Time between invocations of the 24x7 performance collection function on
GPE1. The time (in milliseconds) is derived as 2^PERF_24x7_INVOCATION_TIME_MS
with 0 indicating the function is OFF.
Consumer: p9_hcode_image_build.c ->
SGPE Header field
Provided by the Machine Readable Workbook to tune the collection.
Platform default: 1
TARGET_TYPE_SYSTEM
uint8
ATTR_CME_INSTRUCTION_TRACE_ENABLE
Enables the SGPE Hcode to enable the CME instruction traces into the L3
Trace array for debug. Note: all configured CMEs will be put into this
mode if this attribute is ON.
Consumer: p9_hcode_image_build.c ->
SGPE Header field
Platform default: OFF
TARGET_TYPE_PROC_CHIP
uint8
OFF = 0x00, ON = 0x01
ATTR_CME_CHTM_TRACE_ENABLE
Enables the SGPE Hcode to enable the CME instruction traces into the CHTM
for debug. Note: all configured CMEs will be put into this
mode if this attribute is ON.
Consumer: p9_hcode_image_build.c ->
SGPE Header field
Platform default: OFF
TARGET_TYPE_PROC_CHIP
uint8
OFF = 0x00, ON = 0x01
ATTR_CME_CHTM_TRACE_MEMORY_CONFIG
CHTM Trace Memory Configuration value goes directly into CHTM_MEM register.
User is responsible to put correct data for each bit field of the register.
Consumer: p9_hcode_image_build.c ->
SGPE Header field
Platform default: 0
TARGET_TYPE_PROC_CHIP
uint64
ATTR_PGPE_HCODE_FUNCTION_ENABLE
Enables the PGPE Hcode to physically perform frequency and voltage operations
based on constructed parameters (eg #V VPD, system parameters, biases, WPF
VFRTs. etc). If OFF, the PGPE provides an immedicate good response to all
Pstate/WOF IPC operations from the OCC for firmware integration testing purposes.
Consumer: p9_hcode_image_build.c ->
PGPE Header field
Platform default: ON
TARGET_TYPE_SYSTEM
uint8
OFF = 0x00, ON = 0x01
ATTR_POUND_W_STATIC_DATA_ENABLE
Enables pstate parameter block code to use the static #W data
Consumer: p9_pstate_parameter_block.C ->
Platform default: OFF
TARGET_TYPE_SYSTEM
uint8
OFF = 0x00, ON = 0x01
ATTR_AUX_FUNC_INVOCATION_TIME_MS
Time between invocations of auxiliary function on
GPE1. The time (in milliseconds) is derived as 2^ATTR_AUX_FUNC_INVOCATION_TIME_MS
with 0 indicating the function is OFF.
Consumer: p9_hcode_image_build.c ->
SGPE Header field
Provided by the Machine Readable Workbook to tune the collection.
Platform default: 1
TARGET_TYPE_SYSTEM
uint8
ATTR_SYS_VFRT_STATIC_DATA_ENABLE
Enables pstate parameter block code to use the static system vfrt data
Consumer: p9_pstate_parameter_block.C ->
Platform default: OFF
TARGET_TYPE_SYSTEM
uint8
OFF = 0x00, ON = 0x01, VDN_STEP_OFF = 0x02
ATTR_NEST_LEAKAGE_PERCENT
SYSTEM Attribute
Nest leakage percentage used to calculate the Core leakage.
Will eventually be read into OCC Pstate Parameter Block
so the OCC can see it for it's calculations.
Valid Values: 0% thru 100%
Producer: Machine Readable Workbook
Consumer: OCC Firmware
TARGET_TYPE_SYSTEM
uint8
ATTR_SYSTEM_PSTATES_MODE
TARGET_TYPE_SYSTEM
Controls the mode of Pstate Protocol for testing.
ON: Boots the PGPE in "OCC Pstate Mode" but does NOT start the Pstate
protocol
OFF: Does NOT boot the PGPE
AUTO: Boots the PGPE and automatically starts the Pstate protocol.
PMCR operations to move Pstates are honored
Producer: Override
Consumers:
p9_pstate_parameter_block and p9_pm_pstate_gpe_init
uint8
ON = 0x00, OFF = 0x01, AUTO = 0x02
ATTR_CORE_THROTTLE_ASSERT_COUNT
TARGET_TYPE_PROC_CHIP
The number of PGPE Fixed Timer Interrupts (see Hcode documentation for
durations) to assert a core throttle when
OCC Scratch 2[Core Throttle Continuous Change Enable] is set.
A value of 0 when Continuous Change Enable is set will deassert throttle.
Producer: Override/Lab
Consumers:
p9_hcode_image_build.c ->
PGPE Header field
uint32
ATTR_CORE_THROTTLE_DEASSERT_COUNT
TARGET_TYPE_PROC_CHIP
The number of PGPE Fixed Timer Interrupts (see Hcode documentation for
machine dependent durations) to deassert core throttle when
OCC Scratch 2[Core Throttle Continuous Change Enable] is set.
A value of 0 when Continuous Change Enable is set and
ATTR_CORE_THROTTLE_ASSERT_COUNT is non-0, throttling is always on.
Producer: Override/Lab
Consumers:
p9_hcode_image_build.c ->
PGPE Header field
uint32
ATTR_PM_GLOBAL_FIR_TRACE_EN
TARGET_TYPE_SYSTEM
Enable Global FIR tracing through PM Complex Reset/Initialization
uint8
ATTR_FREQ_PB_MHZ_POUNDV_FALLBACK
TARGET_TYPE_SYSTEM
The powerbus frequency that should be used to locate a valid #V bucket
in the processor Module VPD if the actual ATTR_FREQ_PB_MHZ value isn't
present.
uint32
NO_FALLBACK = 0,
1600 = 1600,
1866 = 1866,
2000 = 2000,
2133 = 2133,
2400 = 2400
NO_FALLBACK
ATTR_SKIP_WAKEUP
TARGET_TYPE_SYSTEM
The PM_RESET hwp calls special wakeup enable on all EX targets, then
will clear auto-special wakeup bit on the core if special wakeup is done.
In some cases hostboot does not want these steps of the PM_RESET. This
attribute gives the platform the ability to decide if they want to enable
special wakeup and clear autowakeup on the cores during PM_RESET
uint8
0
ATTR_PM_MALF_ALERT_ENABLE
TARGET_TYPE_SYSTEM
Switch to enable or disable Power Management Malfunction Alert Handling
based on the platform support. e.g. True for PHYP based systems and False
for KVM based systems depending on support available.
Producer: Initialized by Hostboot firmware based on platform support
Consumers: Read by p9_pm_reset.C p9_pm_stop_gpe_init.C
uint8
FALSE = 0x00, TRUE = 0x01
ATTR_PM_RESET_FFDC_ENABLE
TARGET_TYPE_SYSTEM
Switch to enable or disable Power Management Complex FFDC collection to HOMER.
When set, the PM Complex Reset flow will collect PM Complex data to the chip
HOMER region to assist with failure analysis and recovery.
Producer: HB must set or reset this based on the platform use-case and state.
Consumer: p9_pm_reset.C, p9_pm_callout.C
uint8
FALSE = 0x00, TRUE = 0x01
ATTR_NEST_24x7_PERF_ACCUM_ENABLE
TARGET_TYPE_SYSTEM
Switch to enable or disable 24x7 IMA. Based on the attribute value, a field of
QPMR header of HOMER is populated while building HOMER. Based on the value in
that field 24x7 code, which runs on GPE1, either starts or stops Nest IMA.
Producer: Initialized by Hostboot firmware based on platform support
Consumers: Read by p9_hcode_image_build.C
uint8
FALSE = 0x00, TRUE = 0x01
TRUE
ATTR_UNSECURE_HOMER_ADDRESS
TARGET_TYPE_PROC_CHIP
Address is allocated by hostboot and HBRT and is populated
by p9_hcode_image_build with sc2 instruction. It enables CME to invoke
a transition from HV to UV during STOP entry on an SMF enabled system.
Address value should be aligned with 2MB boundary.
Producer: Initialized by Hostboot firmware based on platform support
Consumers: Read by p9_hcode_image_build.C
uint64
ATTR_UNSECURE_HOMER_SIZE
TARGET_TYPE_SYSTEM
Size of memory in bytes which hostboot must copy from a temp buffer to
an unsecure region of main store memory. Once HOMER is built, hostboot reads
the attribute and copies the amount of memory specified in this attribute from
a temp buffer to an unsecure region of main memory specifed in an attribute
ATTR_UNSECURE_HOMER_ADDRESS
Producer: Initialized by hostboot firmware based on platform support
Consumers: Read by p9_hcode_image_build.C
uint32
1024
ATTR_PMCR_MOST_RECENT_MODE
TARGET_TYPE_PROC_CHIP
Enables the platform mode where the most recent PMCR update
will be the controlling value for Pstate changes. If disabled,
the legacy "fastest one wins" algorithm is used.
Producer: p9_build_pstate_datablock
Consumers: p9_hcode_image_build ->
PGPE Header
CME Header
uint8
FALSE=0, TRUE=1
ATTR_ENABLED_OBUS_BRICKS
TARGET_TYPE_PROC_CHIP
Bitstring that describes the enabled OBUS Bricks on this processor.
The first brick is position bit0, etc
Producer: Initialized by Hostboot firmware based on platform support
Consumers: Read by p9_check_proc_config.C
uint64