ATTR_PROC_NPU_REGION_ENABLED
TARGET_TYPE_PROC_CHIP
Boolean indicating accessibilty of NPU logic region
uint8
ATTR_CLOCK_PLL_MUX_TOD
TARGET_TYPE_PROC_CHIP
Axone only - setup clock mux settings for TOD Refclk input
0b0 = 16 MHz I/O Filter PLL Output
0b1 = 32 MHz LPC reference clock
uint8
ATTR_CLOCK_PLL_MUX
TARGET_TYPE_PROC_CHIP
setup clock mux settings
uint32
ATTR_CLOCK_PLL_MUX0
TARGET_TYPE_PROC_CHIP
Clock Mux#0 settings
uint8
ATTR_I2C_BUS_DIV_REF
TARGET_TYPE_PROC_CHIP
Ref clock I2C bus divider consumed by code running out of OTPROM
uint16
ATTR_EQ_GARD
TARGET_TYPE_PROC_CHIP
Capturing EQ Gard value
uint8
ATTR_EC_GARD
TARGET_TYPE_PROC_CHIP
Capturing EC Gard Value
uint32
ATTR_ISTEP_MODE
TARGET_TYPE_PROC_CHIP
Indicates istep IPL
uint8
NON_IPL = 0x0,IPL = 0x1
ATTR_SBE_RUNTIME_MODE
TARGET_TYPE_PROC_CHIP
Indicates that SBE should go directly to runtime functionality
uint8
FALSE = 0x0,TRUE = 0x1
ATTR_IS_SP_MODE
TARGET_TYPE_PROC_CHIP
Indicates whether we are connected to FSP or not
uint8
FSP_LESS = 0x0,FSP = 0x1
ATTR_SBE_FFDC_ENABLE
TARGET_TYPE_PROC_CHIP
Indicates whether SBE should collect FFDC
uint8
FALSE = 0x0,TRUE = 0x1
ATTR_SBE_INTERNAL_FFDC_ENABLE
TARGET_TYPE_PROC_CHIP
Indicates that the SBE should send back internal FFDC on any
chipOp failure response
uint8
FALSE = 0x0,TRUE = 0x1
ATTR_NEST_PLL_BUCKET
TARGET_TYPE_SYSTEM
Select Nest I2C and pll setting from one of the supported frequencies
uint8
ATTR_FILTER_PLL_BUCKET
TARGET_TYPE_PROC_CHIP
Select Filter PLL bucket
uint8
ATTR_MRW_FILTER_PLL_BUCKET
TARGET_TYPE_SYSTEM
System specific value for Filter PLL bucket, provided by MRW.
If non-zero, this value will directly set ATTR_FILTER_PLL_BUCKET (used by SBE to select bucket).
If zero, VPD MK content will set ATTR_FILTER_PLL_BUCKET.
uint8
ATTR_FORCE_SYNC_SS_PLL_SPREAD
TARGET_TYPE_SYSTEM
Use TOD to synchronize SS filter PLL spreading across system,
overriding ATTR_CHIP_EC_FEATURE_SYNC_SS_PLL_SPREAD
uint8
ATTR_OB0_PLL_BUCKET
TARGET_TYPE_PROC_CHIP
Select OBUS0 pll setting from one of the supported frequencies
uint8
ATTR_OB1_PLL_BUCKET
TARGET_TYPE_PROC_CHIP
Select OBUS1 pll setting from one of the supported frequencies
uint8
ATTR_OB2_PLL_BUCKET
TARGET_TYPE_PROC_CHIP
Select OBUS2 pll setting from one of the supported frequencies
uint8
ATTR_OB3_PLL_BUCKET
TARGET_TYPE_PROC_CHIP
Select OBUS3 pll setting from one of the supported frequencies
uint8
ATTR_BOOT_FREQ_MULT
TARGET_TYPE_PROC_CHIP
EQ boot frequency multiplier
The equation for this setting is BOOT_FREQ(MHz)/(REFCLK/DPLL_DIVIDER) where
the DPLL DIVIDER is planned for being set to 8. The value needs to be loaded
right justified. The value's right most 11 bits (becoming 0:10) is written
as bits 17:27 of PPM DPLL freq ctrl register. Bits 0:7 become DPLL.MULT_INTG(0:7)
and bits 8:10 are DPLL.MULT_FRAC(0:2).
As an example: 3000MHz / (133MHz/8) = 3000 / 16.667 = ~180 => 0xB4
uint16
ATTR_RISK_LEVEL
TARGET_TYPE_SYSTEM
HWP/Init "risk level" enabled. Used by HB to pass to HB driven
HWPs
uint8
RL0 = 0x0,RL1 = 0x1,RL2 = 0x2,RL3 = 0x3,RL4 = 0x4, RL5 = 0x5
ATTR_DISABLE_HBBL_VECTORS
TARGET_TYPE_SYSTEM
BootLoader HWP flag to not place 12K exception vectors.
This flag is only applicable when security is disabled.
uint8
FALSE = 0x0,TRUE = 0x1
FALSE
ATTR_BACKUP_SEEPROM_SELECT
TARGET_TYPE_PROC_CHIP
Set with Primary SEEPROM
uint8
ATTR_BOOT_FLAGS
TARGET_TYPE_SYSTEM
Switch to using a flag to indicate SEEPROM side SBE
uint32
ATTR_BOOT_FREQ_MHZ
TARGET_TYPE_PROC_CHIP
EQ boot frequency
uint32
2400
ATTR_BRANCH_PIBMEM_ADDR
TARGET_TYPE_PROC_CHIP
FIXME - NEEDS DESCRIPTION
uint8
ATTR_CHIP_REGIONS_TO_ENABLE
TARGET_TYPE_PROC_CHIP
FIXME - NEEDS DESCRIPTION
uint32
ATTR_DEVICE_ID
TARGET_TYPE_PROC_CHIP
FIXME - NEEDS DESCRIPTION
uint8
ATTR_ECID
TARGET_TYPE_PROC_CHIP, TARGET_TYPE_MEMBUF_CHIP, TARGET_TYPE_OCMB_CHIP
Populated by HWP called during IPL.
PROC, MEMBUF: Bits 0 to 63 of the ECID in array entry 0 and bits 64 to 127 in ECID array entry 1
OCMB: Explorer: Data Inserted HIGH:LOW, ex. ATTR_ECID[0] = [PE_DATA_3:PE_DATA_2:PE_DATA_1:PE_DATA_0]
OCMB: Gemini: 64-bit ECID inserted in ATTR_ECID[0]
TK/FIXME/TODO: This needs to be made larger to support the entire Explorer ECID.
uint64
2
ATTR_I2C_BUS_DIV_NEST
TARGET_TYPE_PROC_CHIP
I2C Bus speed based on nest freq, ref clock
uint8
ATTR_LEN_OF_SEEPROM_DATA
TARGET_TYPE_PROC_CHIP
FIXME - NEEDS DESCRIPTION
uint8
ATTR_MB_BIT_RATE_DIVISOR_PLL
TARGET_TYPE_PROC_CHIP
FIXME - NEEDS DESCRIPTION
uint8
ATTR_MB_BIT_RATE_DIVISOR_REFCLK
TARGET_TYPE_PROC_CHIP
FIXME - NEEDS DESCRIPTION
uint8
ATTR_MC_SYNC_MODE
TARGET_TYPE_PROC_CHIP
MC mesh to use Nest mesh or not
uint8
IN_SYNC = 1, NOT_IN_SYNC = 0
ATTR_PG
TARGET_TYPE_PERV
Chiplet Partial good info attribute
This should be a direct copy of the data from the PG keyword of VPD.
uint16
ATTR_PROC_PB_BNDY_DMIPLL_DATA
TARGET_TYPE_PROC_CHIP
Ring image for pb_bndy_dmipll ring creator: platform firmware notes:
uint8
ATTR_PROC_PB_BNDY_DMIPLL_FOR_DCCAL_DATA
TARGET_TYPE_PROC_CHIP
Ring image for pb_bndy_dmipll ring for DC cal creator: platform firmware notes:
uint8
ATTR_PROC_PERV_BNDY_PLL_DATA
TARGET_TYPE_PROC_CHIP
Ring image for perv_bndy_pll ring containing filter plls and xb_pll,nest_pll creator: platform firmware notes:
uint8
ATTR_PROC_SBE_MASTER_CHIP
TARGET_TYPE_PROC_CHIP
Indicates if SBE on this chip is serving as hosboot drawer master
uint8
FALSE = 0x0,TRUE = 0x1
ATTR_SBE_SEEPROM_I2C_DEVICE_ADDRESS
TARGET_TYPE_PROC_CHIP
FIXME - NEEDS DESCRIPTION
uint64
ATTR_SBE_SEEPROM_I2C_PORT
TARGET_TYPE_PROC_CHIP
FIXME - NEEDS DESCRIPTION
uint64
ATTR_START_PIBMEM_ADDR
TARGET_TYPE_PROC_CHIP
FIXME - NEEDS DESCRIPTION
uint8
ATTR_START_SEEPROM_ADDR
TARGET_TYPE_PROC_CHIP
FIXME - NEEDS DESCRIPTION
uint8
ATTR_WAIT_N0
TARGET_TYPE_PROC_CHIP
FIXME - NEEDS DESCRIPTION
uint8
ATTR_WAIT_N1
TARGET_TYPE_PROC_CHIP
FIXME - NEEDS DESCRIPTION
uint8
ATTR_WAIT_N2
TARGET_TYPE_PROC_CHIP
FIXME - NEEDS DESCRIPTION
uint8
ATTR_WAIT_N3
TARGET_TYPE_PROC_CHIP
FIXME - NEEDS DESCRIPTION
uint8
ATTR_SYS_FORCE_ALL_CORES
TARGET_TYPE_SYSTEM
Indicate that p9_sbe_select_ex should force selection to ALL good
EX chiplets having good cores even if only a single EX chiplet mode is executed.
uint8
ATTR_MASTER_CORE
TARGET_TYPE_PROC_CHIP
Indicates the master boot core chiplet selected by p9_sbe_select_ex.
uint8
ATTR_MASTER_EX
TARGET_TYPE_PROC_CHIP
Indicates the EX targert associated with the master boot core selected
by p9_sbe_select_ex.
uint8
ATTR_SECURITY_ENABLE
TARGET_TYPE_SYSTEM
Holds the state of Security Access Bit (SAB)
uint8
ATTR_SECURITY_MODE
TARGET_TYPE_SYSTEM
SBE context: If SBE image has ATTR_SECURITY_MODE == 0b1, leave
SAB bit as is. Otherwise (ATTR_SECURITY_MODE == 0b0), query mailbox scratch
register 3 bit 6 and if set, clear the SAB bit. Non-SBE context: If
ATTR_SECURITY_MODE == 0b1, do not attempt to clear the SAB bit via the FSI
path. Otherwise (ATTR_SECURITY_MODE == 0b0), attempt to clear the SAB bit
via the FSI path. Customer level chips will silently ignore such a request,
whereas early lab versions may honor it for debug purposes.
uint8
ATTR_PFET_OFF_CONTROLS
TARGET_TYPE_PROC_CHIP
To disable force pfet off control from fuse status
uint32
ATTR_OBUS_RATIO_VALUE
TARGET_TYPE_PROC_CHIP
Holds Obus ratio value
0b00 Normal speed.
0b01 Half speed.
uint8
ATTR_PIBMEM_REPAIR0
TARGET_TYPE_SYSTEM
Pibmem repair attribute 0
uint64
ATTR_PIBMEM_REPAIR1
TARGET_TYPE_SYSTEM
Pibmem repair attribute 1
uint64
ATTR_PIBMEM_REPAIR2
TARGET_TYPE_SYSTEM
Pibmem repair attribute 2
uint64
ATTR_SENSEADJ_STEP
TARGET_TYPE_EQ
IPL for skew adjust and duty cycle adjust
uint8
ATTR_CP_FILTER_BYPASS
TARGET_TYPE_PROC_CHIP
To skip the locking sequence and check for lock of CP filter PLL
uint8
ATTR_SS_FILTER_BYPASS
TARGET_TYPE_PROC_CHIP
To skip the locking sequence and check for lock of SS filter PLL
uint8
ATTR_IO_FILTER_BYPASS
TARGET_TYPE_PROC_CHIP
To skip the locking sequence and check for lock of IO filter PLL
uint8
ATTR_DPLL_BYPASS
TARGET_TYPE_PROC_CHIP
Skip locking sequence and check for lock of DPLL
uint8
ATTR_NEST_MEM_X_O_PCI_BYPASS
TARGET_TYPE_PROC_CHIP
Skip the locking sequence and check for lock of NEST/MEM/XBUS/OBUS/PCI PLLs
uint8
ATTR_TARGET_HAS_POWER
TARGET_TYPE_PERV
Functional Target has power
uint8
ATTR_TARGET_HAS_CLOCK
TARGET_TYPE_PERV
Functional Target has clock
uint8
ATTR_TARGET_IS_SCOMMABLE
TARGET_TYPE_PERV
Functional Target is scommable
uint8
ATTR_SBE_SYS_CONFIG
TARGET_TYPE_SYSTEM
System Configurtion information - 1 indicates a chip present
uint64
ATTR_CP_REFCLOCK_RCVR_TERM
TARGET_TYPE_SYSTEM
Defines system specific value of processor refclock receiver termination
NONE = 0, FIFTY_OHM = 1
uint8
ATTR_IO_REFCLOCK_RCVR_TERM
TARGET_TYPE_SYSTEM
Defines system specific value of PCI refclock receiver termination
NONE = 0, FIFTY_OHM = 1, ONE_HUNDRED_OHM = 3
uint8
ATTR_SECUREBOOT_PROTECT_DECONFIGURED_TPM
TARGET_TYPE_PROC_CHIP
To deconfigure a TPM in a secure system - 01 to set TDP bit
uint8
ATTR_SECTOR_BUFFER_STRENGTH
TARGET_TYPE_SYSTEM
Sector buffer strength
uint8
ATTR_PULSE_MODE_ENABLE
TARGET_TYPE_SYSTEM
enable the pulse mode
uint8
ATTR_PULSE_MODE_VALUE
TARGET_TYPE_SYSTEM
value for pulse mode
uint8
ATTR_NDL_MESHCTRL_SETUP
TARGET_TYPE_PROC_CHIP
Control NDL training:meshctrl setup
uint8
ATTR_START_CBS_FIFO_RESET_SKIP
TARGET_TYPE_SYSTEM
Allow skipping fifo reset during p9_start_cbs,
to enable systems without cfam access to fifo registers (WAFER/RBI).
uint8
FALSE = 0x0,TRUE = 0x1
ATTR_SYSTEM_CORECACHE_SKEWADJ_DISABLE
TARGET_TYPE_SYSTEM
To allow for selective enablement for lab testing
To allow skew function to be enabled/disabled.
uint8
FALSE = 0x0,TRUE = 0x1
ATTR_SYSTEM_CORECACHE_DCADJ_DISABLE
TARGET_TYPE_SYSTEM
To allow for selective enablement for lab testing
To allow dcadj function to be enabled/disabled.
uint8
FALSE = 0x0,TRUE = 0x1
ATTR_MC_PLL_BUCKET
TARGET_TYPE_SYSTEM
MC pll bucket selection.
See MEM_PLL_FREQ_LIST for Cumulus.
See OMI_PLL_FREQ_LIST for Axone.
uint8
ATTR_PROC_MEM_TO_USE
TARGET_TYPE_PROC_CHIP
This attribute denotes where our master proc's memory is
located. In the case that the master-proc does not have usable memory,
we are going to use another proc's memory to boot. The attribute will be
set to the chip and group ID of which proc we want to use.
uint8
ATTR_ORIG_FIR_SETTINGS_ACTION0
TARGET_TYPE_SYSTEM
This attribute is saving the fir settings for action0. During
different points of the IPL we want to turn off unit checkstops.
This attribute saves the original value.
uint64
ATTR_ORIG_FIR_SETTINGS_ACTION1
TARGET_TYPE_SYSTEM
This attribute is saving the fir settings for action1. During
different points of the IPL we want to turn off unit checkstops.
This attribute saves the original value.
uint64
ATTR_LPC_CONSOLE_CNFG
TARGET_TYPE_PROC_CHIP
Indicates if LPC console is enabled on system
uint8
ENABLE = 0x1,DISABLE = 0x0
DISABLE