ATTR_PROC_FSP_BAR_ENABLE TARGET_TYPE_PROC_CHIP FSP BAR enable creator: platform consumer: p9_setup_bars firmware notes: none uint8 DISABLE = 0x0, ENABLE = 0x1 ATTR_PROC_FSP_BAR_BASE_ADDR_OFFSET TARGET_TYPE_SYSTEM FSP BAR creator: platform consumer: p9_setup_bars firmware notes: Defines range mapped for FSP MMIO Attribute holds offset (relative to chip MMIO origin) to program into chip address range field of BAR -- RA bits 22:43 uint64 ATTR_PROC_FSP_BAR_SIZE TARGET_TYPE_SYSTEM FSP BAR size value creator: platform consumer: p9_setup_bars firmware notes: none uint64 4_GB = 0xFFFFFC00FFFFFFFF, 2_GB = 0xFFFFFC007FFFFFFF, 1_GB = 0xFFFFFC003FFFFFFF, 512_MB = 0xFFFFFC001FFFFFFF, 256_MB = 0xFFFFFC000FFFFFFF, 128_MB = 0xFFFFFC0007FFFFFF, 64_MB = 0xFFFFFC0003FFFFFF, 32_MB = 0xFFFFFC0001FFFFFF, 16_MB = 0xFFFFFC0000FFFFFF, 8_MB = 0xFFFFFC00007FFFFF, 4_MB = 0xFFFFFC00003FFFFF, 2_MB = 0xFFFFFC00001FFFFF, 1_MB = 0xFFFFFC00000FFFFF ATTR_PROC_FSP_MMIO_MASK_SIZE TARGET_TYPE_SYSTEM FSP MMIO mask size value creator: platform consumer: p9_setup_bars firmware notes: AND mask applied to RA 32:35 when transmitting address to FSP NOTE: RA 8:31 are always replaced with zero uint64 4_GB = 0x00F0000000000000, 2_GB = 0x0070000000000000, 1_GB = 0x0030000000000000, 512_MB = 0x0010000000000000, 256_MB = 0x0000000000000000 ATTR_PROC_NPU_PHY0_BAR_ENABLE TARGET_TYPE_PROC_CHIP NPU PHY0 (stack0) BAR enable creator: platform consumer: p9_setup_bars firmware notes: none uint8 DISABLE = 0x0, ENABLE = 0x1 ATTR_PROC_NPU_PHY0_BAR_BASE_ADDR_OFFSET TARGET_TYPE_SYSTEM NPU PHY0 (stack0) BAR creator: platform consumer: p9_setup_bars firmware notes: Defines 2MB range (size implied) mapped to PHY0 registers Attribute holds offset (relative to chip MMIO origin) to program into chip address range field of BAR -- RA bits 22:42 (excludes system/memory select/group/chip fields) uint64 ATTR_PROC_NPU_PHY1_BAR_ENABLE TARGET_TYPE_PROC_CHIP NPU PHY1 (stack1) BAR enable creator: platform consumer: p9_setup_bars firmware notes: none uint8 DISABLE = 0x0, ENABLE = 0x1 ATTR_PROC_NPU_PHY1_BAR_BASE_ADDR_OFFSET TARGET_TYPE_SYSTEM NPU PHY1 (stack1) BAR creator: platform consumer: p9_setup_bars firmware notes: Defines 2MB range (size implied) mapped to PHY1 registers Attribute holds offset (relative to chip MMIO origin) to program into chip address range field of BAR -- RA bits 22:42 (excludes system/memory select/group/chip fields) uint64 ATTR_PROC_NPU_MMIO_BAR_ENABLE TARGET_TYPE_PROC_CHIP NPU MMIO (stack2) BAR enable creator: platform consumer: p9_setup_bars firmware notes: none uint8 DISABLE = 0x0, ENABLE = 0x1 ATTR_PROC_NPU_MMIO_BAR_BASE_ADDR_OFFSET TARGET_TYPE_SYSTEM NPU MMIO (stack2) BAR creator: platform consumer: p9_setup_bars firmware notes: Defines 16MB range mapped to all NPU registers Attribute holds offset (relative to chip MMIO origin) to program into chip address range field of BAR -- RA bits 22:39 (excludes system/memory select/group/chip fields) uint64 ATTR_PROC_NPU0_MMIO_BAR_ENABLE TARGET_TYPE_PROC_CHIP NPU0 MMIO BAR enable creator: platform consumer: p9_setup_bars firmware notes: none uint8 DISABLE = 0x0, ENABLE = 0x1 ATTR_PROC_NPU0_MMIO_BAR_BASE_ADDR_OFFSET TARGET_TYPE_SYSTEM NPU MMIO BAR creator: platform consumer: p9_setup_bars firmware notes: Defines 16MB range mapped to NPU0 registers Attribute holds offset (relative to chip MMIO origin) to program into chip address range field of BAR -- Bits 15:39 of the RA (excludes system/memory select/group/chip fields) uint64 ATTR_PROC_NPU1_MMIO_BAR_ENABLE TARGET_TYPE_PROC_CHIP NPU1 MMIO BAR enable creator: platform consumer: p9_setup_bars firmware notes: none uint8 DISABLE = 0x0, ENABLE = 0x1 ATTR_PROC_NPU1_MMIO_BAR_BASE_ADDR_OFFSET TARGET_TYPE_SYSTEM NPU1 MMIO BAR creator: platform consumer: p9_setup_bars firmware notes: Defines 16MB range mapped to NPU1 registers Attribute holds offset (relative to chip MMIO origin) to program into chip address range field of BAR -- Bits 15:39 of the RA (excludes system/memory select/group/chip fields) uint64 ATTR_PROC_NPU2_MMIO_BAR_ENABLE TARGET_TYPE_PROC_CHIP NPU2 MMIO BAR enable creator: platform consumer: p9_setup_bars firmware notes: none uint8 DISABLE = 0x0, ENABLE = 0x1 ATTR_PROC_NPU2_MMIO_BAR_BASE_ADDR_OFFSET TARGET_TYPE_SYSTEM NPU2 MMIO BAR creator: platform consumer: p9_setup_bars firmware notes: Defines 16MB range mapped to NPU2 registers Attribute holds offset (relative to chip MMIO origin) to program into chip address range field of BAR -- Bits 15:39 of the RA (excludes system/memory select/group/chip fields) uint64 ATTR_PROC_NPU0_PRI_CONFIG TARGET_TYPE_PROC_CHIP NPU0 NTL Private Register Interface (PRI) Configuration register settings Array 0 = SM0 value 1 = SM1 value 2 = SM2 value 3 = SM3 value Bits of values: 0 PRI_CONFIG_DISABLE: Disable 1 Disable (this will disable NTL from decoding the NDL register space) 1:2 PRI_CONFIG_NDL: NDL indication sent in the PRI Read/Write access 00 = NDL 0 01 = NDL 1 10 = NDL 2 11 = NDL 3 3:4 PRI_CONFIG_PHY: Indicates if NTL should decode a PHY register space 00 = Decode PHY0 register space 01 = Decode PHY1 register space 1- = Do not decode any PHY register space uint8 4 ATTR_PROC_NPU1_PRI_CONFIG TARGET_TYPE_PROC_CHIP NPU1 NTL Private Register Interface (PRI) Configuration register settings Array 0 = SM0 value 1 = SM1 value 2 = SM2 value 3 = SM3 value Bits of values: 0 PRI_CONFIG_DISABLE: Disable 1 Disable (this will disable NTL from decoding the NDL register space) 1:2 PRI_CONFIG_NDL: NDL indication sent in the PRI Read/Write access 00 = NDL 0 01 = NDL 1 10 = NDL 2 11 = NDL 3 3:4 PRI_CONFIG_PHY: Indicates if NTL should decode a PHY register space 00 = Decode PHY0 register space 01 = Decode PHY1 register space 1- = Do not decode any PHY register space uint8 4 ATTR_PROC_NPU2_PRI_CONFIG TARGET_TYPE_PROC_CHIP NPU2 NTL Private Register Interface (PRI) Configuration register settings Array 0 = SM0 value 1 = SM1 value 2 = SM2 value 3 = SM3 value Bits of values: 0 PRI_CONFIG_DISABLE: Disable 1 Disable (this will disable NTL from decoding the NDL register space) 1:2 PRI_CONFIG_NDL: NDL indication sent in the PRI Read/Write access 00 = NDL 0 01 = NDL 1 10 = NDL 2 11 = NDL 3 3:4 PRI_CONFIG_PHY: Indicates if NTL should decode a PHY register space 00 = Decode PHY0 register space 01 = Decode PHY1 register space 1- = Do not decode any PHY register space uint8 4 ATTR_PROC_PSI_BRIDGE_BAR_ENABLE TARGET_TYPE_PROC_CHIP PSI Bridge BAR enable creator: platform consumer: p9_setup_bars firmware notes: none uint8 DISABLE = 0x0, ENABLE = 0x1 ATTR_PROC_PSI_BRIDGE_BAR_BASE_ADDR_OFFSET TARGET_TYPE_SYSTEM PSI Bridge BAR base address offset creator: platform consumer: p9_setup_bars firmware notes: Defines 1MB range (size implied) mapped for PSI host-bridge Attribute holds offset (relative to chip MMIO origin) to program into chip address range field of BAR -- RA bits 22:43 (excludes system/memory select/group/chip fields) uint64 ATTR_PROC_NX_RNG_BAR_ENABLE TARGET_TYPE_PROC_CHIP NX RNG BAR enable creator: platform consumer: p9_rng_init_phase2 firmware notes: none uint8 DISABLE = 0x0, ENABLE = 0x1 ATTR_PROC_NX_RNG_BAR_BASE_ADDR_OFFSET TARGET_TYPE_SYSTEM NX RNG BAR creator: platform consumer: p9_rng_init_phase2 firmware notes: Defines 8KB range (size implied) mapped for NX RNG function Attributes holds offset (relative to chip MMIO origin) to program into chip address range field of BAR -- RA bits 22:51 (excludes system/memory select/group/chip fields) uint64 ATTR_PROC_NX_RNG_FAILED_INT_ENABLE TARGET_TYPE_PROC_CHIP Enable optional post of interrupt when both NX RNG noise sources have failed creator: platform consumer: p9_rng_init_phase2 firmware notes: none uint8 DISABLE = 0x0, ENABLE = 0x1 ATTR_PROC_NX_RNG_FAILED_INT_ADDR TARGET_TYPE_PROC_CHIP Address used to post interrupt when both NX RNG noise sources have failed creator: platform consumer: p9_rng_init_phase2 firmware notes: 64-bit address representing RA NOTE: register covers RA 8:51 uint64 ATTR_PROC_INT_CQ_PC_BAR_ENABLE TARGET_TYPE_PROC_CHIP INT CQ PC BAR enable creator: platform consumer: p9_setup_bars firmware notes: none uint8 DISABLE = 0x0, ENABLE = 0x1 ATTR_PROC_INT_CQ_PC_BAR_BASE_ADDR_OFFSET TARGET_TYPE_SYSTEM INT CQ PC BAR base address offset creator: platform consumer: p9_setup_bars firmware notes: Attribute holds offset (relative to chip MMIO origin) to program into chip address range field of BAR (excludes system/memsel/group/chip fields) uint64 ATTR_PROC_INT_CQ_PC_BAR_BASE_ADDR_OFFSET_MASK TARGET_TYPE_SYSTEM INT CQ PC BAR base address offset mask creator: platform consumer: p9_setup_bars firmware notes: Attribute holds offset mask (relative to chip MMIO origin) to program into chip address range field of BAR mask (excludes system/memsel/group/chip fields) Value defines which bits of VC_BAR are used during address compares uint64 ATTR_PROC_INT_CQ_VC_BAR_ENABLE TARGET_TYPE_PROC_CHIP INT CQ VC BAR enable creator: platform consumer: p9_setup_bars firmware notes: none uint8 DISABLE = 0x0, ENABLE = 0x1 ATTR_PROC_INT_CQ_VC_BAR_BASE_ADDR_OFFSET TARGET_TYPE_SYSTEM INT CQ VC BAR base address offset creator: platform consumer: p9_setup_bars firmware notes: Attribute holds offset (relative to chip MMIO origin) to program into chip address range field of BAR (excludes system/memsel/group/chip fields) uint64 ATTR_PROC_INT_CQ_VC_BAR_BASE_ADDR_OFFSET_MASK TARGET_TYPE_SYSTEM INT CQ VC BAR base address offset mask creator: platform consumer: p9_setup_bars firmware notes: Attribute holds offset mask (relative to chip MMIO origin) to program into chip address range field of BAR mask (excludes system/memsel/group/chip fields) Value defines which bits of VC_BAR are used during address compares uint64 ATTR_PROC_INT_CQ_TM1_BAR_ENABLE TARGET_TYPE_PROC_CHIP INT CQ TM1 BAR enable creator: platform consumer: p9_setup_bars firmware notes: none uint8 DISABLE = 0x0, ENABLE = 0x1 ATTR_PROC_INT_CQ_TM1_BAR_BASE_ADDR_OFFSET TARGET_TYPE_SYSTEM INT CQ TM1 BAR base address offset creator: platform consumer: p9_setup_bars firmware notes: Attribute holds offset (relative to chip MMIO origin) to program into chip address range field of BAR (excludes system/memsel/group/chip fields) uint64 ATTR_PROC_INT_CQ_TM1_BAR_PAGE_SIZE TARGET_TYPE_SYSTEM INT CQ TM1 BAR page size creator: platform consumer: p9_setup_bars firmware notes: none uint8 4K = 0x0, 64K = 0x1 ATTR_PROC_INT_CQ_IC_BAR_ENABLE TARGET_TYPE_PROC_CHIP INT CQ IC BAR enable creator: platform consumer: p9_setup_bars firmware notes: none uint8 DISABLE = 0x0, ENABLE = 0x1 ATTR_PROC_INT_CQ_IC_BAR_BASE_ADDR_OFFSET TARGET_TYPE_SYSTEM INT CQ IC BAR base address offset creator: platform consumer: p9_setup_bars firmware notes: Attribute holds offset (relative to chip MMIO origin) to program into chip address range field of BAR (excludes system/memsel/group/chip fields) uint64 ATTR_PROC_INT_CQ_IC_BAR_PAGE_SIZE TARGET_TYPE_SYSTEM INT CQ IC (Interrupt Controller) BAR page size creator: platform consumer: p9_setup_bars firmware notes: none uint8 4K = 0x0, 64K = 0x1