ATTR_PROC_PCIE_IOP_CONFIG
TARGET_TYPE_PEC
PCIE IOP lane configuration
creator: platform
consumer: p9_pcie_scominit
firmware notes:
These are config dependent attributes based on PCIe Lane/sideband signal routing and PCIe endpoints attached.
Encoded PCIE IOP lane configuration
PEC0:
PHB0 CFG[0:1]
SWP[0]
Examples:
Config #1 PEC0 Lane Config[0:1] = 0b00
PHB0 Swap bit[0] = 0 (Straight lane wiring)
Config #2 PEC0 Lane Config[0:1] = 0b00
PHB0 Swap bit[0] = 1 (Reverse lane wiring)
PEC1:
PHB1 CFG[0:1]
SWP[0]
PHB2 CFG[2:3]
SWP[1]
Examples:
Config #1 PEC1 Lane Config[0:3] = 0b0000
PHB1 Swap bit[0] = 0 (Straight lane wiring)
PHB2 Swap bit[1] = 0 (Straight lane wiring)
Config #2 PEC1 Lane Config[0:3] = 0b0000
PHB1 Swap bit[0] = 1 (Reverse lane wiring)
PHB2 Swap bit[1] = 0 (Straight lane wiring)
PEC2:
CFG[0:1] = 0b00 PHB3 CFG[2:3]; SWP[0]
CFG[4:5] = don't care
SWP[1:2] = don't care
CFG[0:1] = 0b01 PHB3 CFG[2:3]; SWP[0]
PHB4 CFG[4:5]; SWP[1]
PHB5 SWP[2] = don't care
CFG[0:1] = 0b10 PHB3 CFG[2:3]; SWP[0]
PHB4 CFG[4]; SWP[1]
PHB5 CFG[5]; SWP[2]
Examples:
Config #1 (PEC2 Lane Config[0:5] = 0b000000)
PHB3 Swap bit[0] = 0 (Straight lane wiring)
PHB4 Swap bit[1] = don't care
PHB5 Swap bit[2] = don't care
Config #1 (PEC2 Lane Config[0:5] = 0b010000)
PHB3 Swap bit[0] = 1 (Reverse lane wiring)
PHB4 Swap bit[1] = 0 (Straight lane wiring)
PHB5 Swap bit[2] = don't care
Config #3 (PEC2 Lane Config[0:5] = 0b100000)
PHB3 Swap bit[0] = 1 (Reverse lane wiring)
PHB4 Swap bit[1] = 0 (Straight lane wiring)
PHB5 Swap bit[2] = 1 (Reverse lane wiring)
uint8
ATTR_PROC_PCIE_IOP_SWAP
TARGET_TYPE_PEC
PCIE IOP swap configuration
creator: platform
consumer: p9_pcie_scominit
firmware notes:
These are config dependent attributes based on PCIe Lane/sideband signal routing and PCIe endpoints attached.
Encoded PCIE IOP swap configuration
PEC0 - SWP[0] => SWP[0] = PHB0(0:15)
PEC1 - SWP[0:1] => SWP[0] = PHB1(0:7)
=> SWP[1] = PHB2(0:7)
PEC2 - SWP[0:2] => SWP[0] = PHB3(0:7) or PHB3(0:15)
=> SWP[1] = PHB4(0:3) or PHB4(0:7) or don't care if disabled
=> SWP[2] = PHB5(0:3) or don't care if disabled
uint8
ATTR_PROC_PCIE_IOVALID_ENABLE
TARGET_TYPE_PEC
PCIE iovalid enable valid mask
creator: platform
consumer: p9_pcie_scominit
firmware notes:
These are config dependent attributes based on PCIe Lane/sideband signal routing and PCIe endpoints attached.
Encoded PCIE IO Valid configuration
PEC0 - IOVALID[0] => IOVALID[0] = PHB0
PEC1 - IOVALID[0:1] => IOVALID[0] = PHB1
=> IOVALID[1] = PHB2
PEC2 - IOVALID[0:2] => IOVALID[0] = PHB3
=> IOVALID[1] = PHB4
=> IOVALID[2] = PHB5
uint8
ATTR_PROC_PCIE_REFCLOCK_ENABLE
TARGET_TYPE_PEC
PCIE refclock enable valid mask
creator: platform
consumer: p9_pcie_scominit
firmware notes:
These are config dependent attributes based on PEC enablement.
Only one REFCLK enable bit exists across all PECs. There is no granualarity
to control REFCLK enables on a per PHB basis.
uint8
ATTR_PROC_PCIE_BAR_ENABLE
TARGET_TYPE_PHB
PCIE MMIO BAR enable
creator: platform
consumer: p9_pcie_config
firmware notes:
Array index: BAR number (0:2)
index 0~1 for MMIO BAR0/1
index 2 for PHB register space
uint8
DISABLE = 0x0, ENABLE = 0x1
3
ATTR_PROC_PCIE_MMIO_BAR0_BASE_ADDR_OFFSET
TARGET_TYPE_SYSTEM
PCIE MMIO0 BAR base address offset
creator: platform
consumer: p9_setup_bars
firmware notes:
Attribute holds offset (relative to chip MMIO origin) to program into
chip address range field of BAR -- RA bits 8:47
(excludes system/memory select/group/chip fields)
Array index: PHB number (0:5)
uint64
6
ATTR_PROC_PCIE_MMIO_BAR1_BASE_ADDR_OFFSET
TARGET_TYPE_SYSTEM
PCIE MMIO1 BAR base address offset
creator: platform
consumer: p9_setup_bars
firmware notes:
Attribute holds offset (relative to chip MMIO origin) to program into
chip address range field of BAR -- RA bits 8:47
(excludes system/memory select/group/chip fields)
Array index: PHB number (0:5)
uint64
6
ATTR_PROC_PCIE_REGISTER_BAR_BASE_ADDR_OFFSET
TARGET_TYPE_SYSTEM
PCIE PHB register space BAR base address offset
creator: platform
consumer: p9_setup_bars
firmware notes:
Attribute holds offset (relative to chip MMIO origin) to program into
chip address range field of BAR -- RA bits 8:49
(excludes system/memory select/group/chip fields)
Array index: PHB number (0:5)
uint64
6
ATTR_PROC_PCIE_BAR_SIZE
TARGET_TYPE_SYSTEM
PCIE MMIO BAR size values
creator: platform
consumer: p9_pcie_config
firmware notes:
Array index: BAR number (0:2)
NOTE: supported MMIO BAR0/1 sizes are from 64KB-32PB
NOTE: only supported PHB register size is 16KB
uint64
32_PB = 0x8000000000000000,
16_PB = 0xC000000000000000,
8_PB = 0xE000000000000000,
4_PB = 0xF000000000000000,
2_PB = 0xF800000000000000,
1_PB = 0xFC00000000000000,
512_TB = 0xFE00000000000000,
256_TB = 0xFF00000000000000,
128_TB = 0xFF80000000000000,
64_TB = 0xFFC0000000000000,
32_TB = 0xFFE0000000000000,
16_TB = 0xFFF0000000000000,
8_TB = 0xFFF8000000000000,
4_TB = 0xFFFC000000000000,
2_TB = 0xFFFE000000000000,
1_TB = 0xFFFF000000000000,
512_GB = 0xFFFF800000000000,
256_GB = 0xFFFFC00000000000,
128_GB = 0xFFFFE00000000000,
64_GB = 0xFFFFF00000000000,
32_GB = 0xFFFFF80000000000,
16_GB = 0xFFFFFC0000000000,
8_GB = 0xFFFFFE0000000000,
4_GB = 0xFFFFFF0000000000,
2_GB = 0xFFFFFF8000000000,
1_GB = 0xFFFFFFC000000000,
512_MB = 0xFFFFFFE000000000,
256_MB = 0xFFFFFFF000000000,
128_MB = 0xFFFFFFF800000000,
64_MB = 0xFFFFFFFC00000000,
32_MB = 0xFFFFFFFE00000000,
16_MB = 0xFFFFFFFF00000000,
8_MB = 0xFFFFFFFF80000000,
4_MB = 0xFFFFFFFFC0000000,
2_MB = 0xFFFFFFFFE0000000,
1_MB = 0xFFFFFFFFF0000000,
512_KB = 0xFFFFFFFFF8000000,
256_KB = 0xFFFFFFFFFC000000,
128_KB = 0xFFFFFFFFFE000000,
64_KB = 0xFFFFFFFFFF000000,
16_KB = 0xFFFFFFFFFFFFFFFF
3
ATTR_PROC_PCIE_PCS_RX_CDR_GAIN
TARGET_TYPE_PEC
PCS rx cdr gains
creator: platform
consumer: p9_pcie_scominit
firmware notes:
This is a MRW seting.
The value of rx cdr gains for PCS.
Array index: Configuration number
index 0~3 for CONFIG0~3
uint8
4
ATTR_PROC_PCIE_PCS_RX_PK_INIT
TARGET_TYPE_PEC
PCS rx vga peak init value
creator: platform
consumer: p9_pcie_scominit
firmware notes:
This is a MRW setting.
The value of rx vga peak init for PCS.
Array index: Configuration number
index 0~3 for CONFIG0~3
lane 0~15 for each PCIE Lane
uint8
4 16
ATTR_PROC_PCIE_PCS_RX_INIT_GAIN
TARGET_TYPE_PEC
PCS rx vga gain init value
creator: platform
consumer: p9_pcie_scominit
firmware notes:
This is a MRW setting.
The value of rx vga gain init for PCS.
Array index: Configuration number
index 0~3 for CONFIG0~3
lane 0~15 for each PCIE Lane
uint8
4 16
ATTR_PROC_PCIE_PCS_RX_SIGDET_LVL
TARGET_TYPE_PEC
PCS rx sigdet lvl value
creator: platform
consumer: p9_pcie_scominit
firmware notes:
This is a MRW setting.
The value of rx sigdet lvl for PCS.
Array index: Configuration number
index 0~3 for CONFIG0~3
uint8
4
0xA,0xA,0xA,0xA
ATTR_PROC_PCIE_PCS_RX_ROT_CDR_LOOKAHEAD
TARGET_TYPE_PEC
Value of PCS RX ROT CNTL CDR lookahead
creator: platform
consumer: p9_pcie_scominit
firmware notes:
This is a MRW setting.
0 for disable (default)
1 for enable
Used for spread spectrum enablement.
uint8
ATTR_PROC_PCIE_PCS_RX_ROT_CDR_SSC
TARGET_TYPE_PEC
Value of PCS RX ROT CNTL CDR ssc
creator: platform
consumer: p9_pcie_scominit
firmware notes:
This is a MRW setting.
0 for disable (default)
1 for enable
Used for Spread Spectrum enablement.
uint8
ATTR_PROC_PCIE_PCS_RX_ROT_EXTEL
TARGET_TYPE_PEC
Value of PCS RX ROT extel latch
creator: p9_getecid
consumer: p9_pcie_scominit
firmware notes:
0 for internal (default)
1 for external (freezes phase rotators)
For DD1.00 parts, this needs to be set to 1.
uint8
ATTR_PROC_PCIE_PCS_RX_ROT_RST_FW
TARGET_TYPE_PEC
Value of PCS RX ROT rstfw latch
creator: platform
consumer: p9_pcie_scominit
firmware notes:
This is a common setting that can be overwritten by code logic.
0 normal, flywheel is enabled (default)
1 assert reset to the phase rotator flywheel (disable the flywheel)
uint8
ATTR_PROC_PCIE_PCS_PCLCK_CNTL_PLLA
TARGET_TYPE_PEC
Value of PCS pclck control plla
creator: platform
consumer: p9_pcie_scominit
firmware notes:
This is a common setting that can be overwritten by code logic.
uint8
ATTR_PROC_PCIE_PCS_PCLCK_CNTL_PLLB
TARGET_TYPE_PEC
Value of PCS pclck control pllb
creator: platform
consumer: p9_pcie_scominit
firmware notes:
This is a common setting that can be overwritten by code logic.
uint8
ATTR_PROC_PCIE_PCS_TX_DCLCK_ROT
TARGET_TYPE_PEC
Value of PCS tx dclck rotator override
creator: platform
consumer: p9_pcie_scominit
firmware notes:
This is a common setting that can be overwritten by code logic.
uint16
ATTR_PROC_PCIE_PCS_TX_PCIE_RECV_DETECT_CNTL_REG1
TARGET_TYPE_PEC
Value of PCS tx pcie receiver detect control register 1
creator: platform
consumer: p9_pcie_scominit
firmware notes:
This is a common setting that can be overwritten by code logic.
uint16
ATTR_PROC_PCIE_PCS_TX_PCIE_RECV_DETECT_CNTL_REG2
TARGET_TYPE_PEC
Value of PCS tx pcie receiver detect control register 2
creator: platform
consumer: p9_pcie_scominit
firmware notes:
This is a common setting that can be overwritten by code logic.
uint16
ATTR_PROC_PCIE_PCS_TX_POWER_SEQ_ENABLE
TARGET_TYPE_PEC
Value of PCS tx power sequence enable
creator: platform
consumer: p9_pcie_scominit
firmware notes:
This is a common setting that can be overwritten by code logic.
uint8
ATTR_PROC_PCIE_PCS_RX_VGA_CNTL_REG1
TARGET_TYPE_PEC
Value of PCS rx vga control register 1
creator: platform
consumer: p9_pcie_scominit
firmware notes:
This is a common setting that can be overwritten by code logic.
uint16
ATTR_PROC_PCIE_PCS_RX_VGA_CNTL_REG2
TARGET_TYPE_PEC
Value of PCS rx vga control register 2
creator: platform
consumer: p9_pcie_scominit
firmware notes:
This is a common setting that can be overwritten by code logic.
uint16
ATTR_PROC_PCIE_PCS_RX_DFE_FDDC
TARGET_TYPE_PEC
Value of PCS rx dfe func fddc control latch
creator: p9_getecid
consumer: p9_pcie_scominit
firmware notes:
0 disable Dynamic Data Centering
1 enable Dynamic Data Centering (default)
For DD1.0X parts, this needs to be set to 0.
uint8
ATTR_PROC_PCIE_PCS_SYSTEM_CNTL
TARGET_TYPE_PEC
Value of PCS system control
creator: platform
consumer: p9_pcie_scominit
firmware notes:
These are config dependent attributes based on PCIe Lane/sideband signal routing and PCIe endpoints attached.
There are four groups of four lanes: 0-3 (A-D), 4-7 (E-H), 8-11(I-L), and 12-15(M-P). Each lane group can be assigned to a MAC interface. The supported configurations are as follows:
1. MAC #1 = x16, MAC #2 = N/A, MAC #3 = N/A, MAC #4 = N/A : PCS_SYSTEM_CONTROL_REG = 0x0000.
2. MAC #1 = x8, MAC #2 = x8, MAC #3 = N/A, MAC #4 = N/A : PCS_SYSTEM_CONTROL_REG = 0x0050.
3. MAC #1 = x8, MAC #2 = x4, MAC #3 = x4, MAC #4 = N/A : PCS_SYSTEM_CONTROL_REG = 0x0090.
All other configurations are not supported.
uint16
ATTR_PROC_PCIE_PCS_M_CNTL
TARGET_TYPE_PEC
Value of PCS m1-m4 control
creator: platform
consumer: p9_pcie_scominit
This is a common setting that can be overwritten by code logic.
Array index:
0 -> M1
1 -> M2
2 -> M3
3 -> M4
uint16
4