ATTR_NHTM_TRACE_TYPE
TARGET_TYPE_PROC_CHIP
The Nest HTM trace type desired to be collected. This setting
is applied to both NHTM0 and NHTM1.
uint8
DISABLE = 0x0, FABRIC = 0x1, EVENT = 0x2, OCC = 0x3
ATTR_CHTM_TRACE_TYPE
TARGET_TYPE_PROC_CHIP
The Core HTM trace type desired to be collected.
uint8
24
DISABLE = 0x0, CORE = 0x1, LLAT = 0x2, PPE = 0x3, DMW = 0x4
ATTR_HTMSC_TTYPEFILT_PAT
TARGET_TYPE_PROC_CHIP
Nest HTM: defines the TTYPE pattern to match in Fabric trace
mode. These bits are used with the ttype Filter Mask to
indicate the TTYPE value that should be matched on the rcmd.
HTM Ttype Filter Control Register (1:7).
uint8
ATTR_HTMSC_TSIZEFILT_PAT
TARGET_TYPE_PROC_CHIP
Nest HTM: defines the TSIZE pattern to match in Fabric trace
mode. These bits are used with the tsize filter mask to indicate
the TSIZE value that should be matched on the rcmd
HTM Ttype Filter Control Register (8:15).
uint8
ATTR_HTMSC_TTYPEFILT_MASK
TARGET_TYPE_PROC_CHIP
Nest HTM: TTYPE pattern mask.
If mask bit is clear to 0, then do not need to match w/ the pattern.
If all mask bits are clear, no TTYPE pattern/masking is done.
The inversion of this attribute value will be programmed into
bits 17:23 of HTM Ttype Filter Control Register.
uint8
ATTR_HTMSC_TSIZEFILT_MASK
TARGET_TYPE_PROC_CHIP
Nest HTM: TSIZE pattern mask.
If mask bit is clear to 0, then do not need to match w/ the pattern.
If all mask bits are clear, no TSIZE pattern/masking is done.
The inversion of this attribute value will be programmed into
bits 24:31 of HTM Ttype Filter Control Register.
uint8
ATTR_HTMSC_TTYPEFILT_INVERT
TARGET_TYPE_PROC_CHIP
Nest HTM: TTYPE/TSIZE Capture Invert.
HTM Ttype Filter Control Register (32).
This bit controls the inversion of the ttype/tsize filter.
0 : Capture record based on ttype/tsize pattern matching
1 : Capture record based on ttype/tsize pattern NOT matching
uint8
MATCH = 0x0, NOT_MATCH = 0x1
ATTR_HTMSC_CRESPFILT_INVERT
TARGET_TYPE_PROC_CHIP
Nest HTM: CRESP Filter Capture Invert.
HTM Ttype Filter Control Register (33).
This bit controls the inversion of the cresp filter.
0: Capture record based on cresp filter pattern/mask match
1: Capture record based on cresp filter pattern/mask NOT matching.
uint8
MATCH = 0x0, NOT_MATCH = 0x1
ATTR_HTMSC_FILT_PAT
TARGET_TYPE_PROC_CHIP
Nest HTM: Filter Pattern.
HTM Filter Control Register (0:22).
In Fabric trace mode, defines the TTAG/Scope/Source pattern to
match in the RCMD and CRESP:
0:3 rcmd_ttag(0:2) Group ID Pattern for rcmd and cresp
filtering.
4:6 rcmd_ttag(3:5) Chip ID Pattern for rcmd and cresp
filtering.
7:16 rcmd_ttag(6:13) Unit ID Pattern for rcmd and cresp
(if from this chip) filtering.
17:19 rcmd_scope(0:2) Scope Pattern for rcmd and cresp
filtering.
20:21 rcmd_source(0:1) Source Pattern for rcmd filtering.
22 Powerbus PORT pattern for rcmd and cresp filtering.
In OCC trace mode, defines the occ_trace_data(0:22) pattern
to match:
0:22 occ_trace_data(0:22) pattern.
uint32
ATTR_HTMSC_FILT_CRESP_PAT
TARGET_TYPE_PROC_CHIP
Nest HTM: defines the CRESP Filter pattern in FABRIC trace mode.
HTM Filter Control Register (27:31).
uint8
ATTR_HTMSC_FILT_MASK
TARGET_TYPE_PROC_CHIP
Nest HTM FABRIC: Pattern mask.
HTM Filter Control Register (32:54).
Bits clear to 0 in this mask do not need to match with the
Filter Pattern.
If all bits are clear, no pattern/masking is done and all
Cresp/rcmd are captured in Fabric trace mode and all
OCC commands are captured in OCC mode.
The inversion of this attribute value will be programmed into
bits 32:54 of HTM Ttype Filter Control Register.
In Fabric Trace Mode:
32:35: rcmd_ttag(0:3) Group ID Mask
36:38: rcmd_ttag(4:6) Chip ID Mask
39:48: rcmd_ttag(7:16) Unit ID Pattern
49:51: rcmd_scope(0:2) Mask
52:53: rcmd_source(0:1) Mask
54in the : PowerBus PORT MASK (for rcmd and cresp filtering0
In OCC Trace Mode
32:54 occ_trace_data(0:22) Mask
uint32
ATTR_HTMSC_FILT_CRESP_MASK
TARGET_TYPE_PROC_CHIP
Nest HTM FABRIC: CRESP Filter Mask.
HTM Filter Control Register (59:63).
If mask bit is clear to 0, then do not need to match w/ the CRESP
Filter pattern.
If all mask bits are clear, no pattern matching is done.
The inversion of this attribute value will be programmed into
bits 59:63 of HTM Ttype Filter Control Register.
uint8
ATTR_NHTM_HTMSC_MODE_CONTENT_SEL
TARGET_TYPE_PROC_CHIP
Nest HTM: defines the NHTM trace mode.
HTM Collection Mode Register (1:2).
Only FABRIC is supported at this time.
uint8
FABRIC = 0x0, EVENT = 0x1, OCC = 0x2
ATTR_NHTM_HTMSC_MODE_CAPTURE_GENERATED_WRITES
TARGET_TYPE_PROC_CHIP
Nest HTM: defines if the generated data writes are captured.
HTM Collection Mode Register (4).
0 - Ignore HTM generated data writes
1 - Capture even HTM generated writes if they meet the filtering
criteria.
uint8
DISABLE = 0x0, ENABLE = 0x1
ATTR_NHTM_HTMSC_MODE_CAPTURE_ENABLE_FILTER_ALL
TARGET_TYPE_PROC_CHIP
Nest HTM: defines if the filtering will apply to ttype=PMISC
and ttype=Report Hang commands when filtering is enabled.
HTM Collection Mode Register (5).
0 - filtering ignored on PMISC
1 - Apply filtering to PMISC also
uint8
DISABLE = 0x0, ENABLE = 0x1
ATTR_NHTM_HTMSC_MODE_CAPTURE_PRECISE_CRESP_MODE
TARGET_TYPE_PROC_CHIP
Nest HTM: defines if Precise cresp mode is enabled.
0 - Enable precisce cresp mode
1 - Disable precisce cresp mode
uint8
ENABLE = 0x0, DISABLE = 0x1
ATTR_NHTM_HTMSC_MODE_CAPTURE_LIMIT_MEM_ALLOCATION
TARGET_TYPE_PROC_CHIP
Nest HTM: defines Limit Memory Allocation mode.
0 - Pre-allocate maximum memory buffers (NHTM=8)
1 - Pre-allocate only one half maximum memory buffers
uint8
DISABLE = 0x0, ENABLE = 0x1
ATTR_NHTM_HTMSC_MODE_CAPTURE_PMISC_ONLY_CMD
TARGET_TYPE_PROC_CHIP
Nest HTM: defines PMISC only Command trace mode.
0 rCmd amd cResp port 0 only goes to NHTM0
1 rCmd and Cresp port 0 is stored alternately to NHTM0 and
NHTM1, switching based for each valid
uint8
DISABLE = 0x0, ENABLE = 0x1
ATTR_NHTM_HTMSC_MODE_SYNC_STAMP_FORCE
TARGET_TYPE_PROC_CHIP
Control the number of cycles to wait to force a synchronization
stamp or reset the timer. For NHTM only.
HTM Collection Mode Register (19:21).
uint8
ATTR_NHTM_HTMSC_MODE_WRITETOIO
TARGET_TYPE_PROC_CHIP
Use space option. For NHTM only.
HTM Collection Mode Register (22).
0 = Use HTM_CL_Write op to target system memory.
Do pre-allocation sequence. (default)
1 = Use ci_pr_st op to target anywhere else.
Dont do pre-allocate sequence.
uint8
DISABLE = 0x0, ENABLE = 0x1
ATTR_CHTM_HTMSC_MODE_CONTENT_SEL
TARGET_TYPE_PROC_CHIP
Core HTM: defines the CHTM trace mode.
HTM Collection Mode Register (1:2).
Only Direct Memory Write mode (IMA) is supported at this time.
uint8
CI = 0x0, LLAT = 0x1, PPE = 0x2, DMW = 0x3
ATTR_CHTM_HTMSC_MODE_CAPTURE
TARGET_TYPE_PROC_CHIP
Core HTM: defines capture mode according to trace mode.
HTM Collection Mode Register (4:9).
When htm_mode_q(1 TO 2) == 00, i.e. Core Instruction Trace
00xxxx : tc_pc_trace_active asserted when HTM_STAT[Tracing]=1 to purge the ERAT when entering and exitting trace
01xxxx : tc_pc_trace_active asserted when HTM_MODE[HTM_Trace_enable]=1 to purge the ERAT only at the beginning
When htm_mode_q(1 TO 2) == 01, i.e. LLAT Trace
0xxxxx : capture on assertion of l2_htm_llat_disp_req, i.e. any dispatch request
1xxxxx : capture on assertion of l2_htm_llat_disp_req AND l2_llat_htm_rcdisp_occurred, i.e. only on passed dispatch
x0xxxx : capture on assertion of l2_htm_llat_disp_req, i.e. loads or stores
x1xxxx : capture on assertion of l2_htm_llat_disp_req AND l2_llat_htm_rcdisp_ld_not_st, i.e. only loads
xx0xxx : capture on assertion of l2_llat_htm_pbl3hit_dval
xx1xxx : no capture on assertion of l2_llat_htm_pbl3hit_dval - enable embedded timestamp
When htm_mode_q(1 TO 2) == 11, i.e. Direct Memory Write
1xxxxx : Enable HPMC-IMA Mode
uint32
ATTR_CHTM_HTMSC_MODE_CORE_INSTR_STALL
TARGET_TYPE_PROC_CHIP
For CHTM only.
0: Core execution is stalled whenever the data buffers are almost full to prevent losing records.
1: Core execution is never stalled and entries may be discarded when buffer is full
uint8
ENABLE = 0x0, DISABLE = 0x1
ATTR_HTMSC_MODE_WRAP
TARGET_TYPE_PROC_CHIP
Trace Wrap mode, used for both NHTM and CHTM
HTM Collection Mode Register (13).
0 = Wrap trace to beginning of Trace Memory
1 = Stop trace when top of Trace Memory is reached
uint8
ENABLE = 0x0, DISABLE = 0x1
ATTR_HTMSC_MODE_DIS_TSTAMP
TARGET_TYPE_PROC_CHIP
TimeStamp Writes option, used for both NHTM and CHTM
HTM Collection Mode Register (14).
0 = Write of timestamps enabled to indicate elapsed time
between records.
1 = Timestamps written only to indicate record loss
uint8
ENABLE = 0x0, DISABLE = 0x1
ATTR_HTMSC_MODE_SINGLE_TSTAMP
TARGET_TYPE_PROC_CHIP
Overflow Timestamps option, used for both NHTM and CHTM.
HTM Collection Mode Register (15).
0 = Timestamp written to indicate elapsed time overflow.
1 = Only one timestamp is written between entries, overflow
indication is lost
uint8
DISABLE = 0x0, ENABLE = 0x1
ATTR_HTMSC_MODE_MARKERS_ONLY
TARGET_TYPE_PROC_CHIP
Nest HTM: Stamp/Marker only mode.
HTM Collection Mode Register (17).
0 = Normal trace
1 = Ignore incoming trace data and save only markers caused
by HTM_TRIG writes,
uint8
DISABLE = 0x0, ENABLE = 0x1
ATTR_HTMSC_MODE_DIS_FORCE_GROUP_SCOPE
TARGET_TYPE_PROC_CHIP
Nest HTM: Group scope option.
HTM Collection Mode Register (18).
This is a powerbus debug bit
0 = htm write ops sent with group scope
1 = htm write ops sent with Vg scope using programmed
target bits.
uint8
DISABLE = 0x0, ENABLE = 0x1
ATTR_HTMSC_MODE_VGTARGET
TARGET_TYPE_PROC_CHIP
Nest HTM: VG target mode.
Stores inverse of HTM Collection Mode Register (24:39).
Vg Target bits should be configured if HTM_MEM[scope] is Vg
or if Disable Group Scope=1
uint32
ATTR_HTMSC_MEM_SCOPE
TARGET_TYPE_PROC_CHIP
Setting of memory scope for HTM collection.
HTM Memory Configuration Register (1:3)
uint8
LOCAL = 0x0, NEARNODE = 0x1, GROUP = 0x3, REMOTE = 0x4, VECTORED = 0x5
ATTR_HTMSC_MEM_PRIORITY
TARGET_TYPE_PROC_CHIP
Setting of memory priority for HTM collection.
HTM Memory Configuration Register (4)
uint8
LOW = 0x0, HIGH = 0x1
ATTR_NHTM_CTRL_TRIG
TARGET_TYPE_PROC_CHIP
Setting of Trigger control for NHTM.
HTM Trigger Control Register (0:1)
00 local triggers are not forwarded to the PowerBus, it is
inserted into the trace when tracing. Both local and
global triggers control the HTM
01 local triggers are not forwarded to the PowerBus, it is
inserted into the traCe when tracing. Only local triggers
control the HTM
1x local triggers are forwarded to the PowerBus, it is not
inserted into the trace when tracing. Only global
triggers control the HTM
uint8
LOCAL_GLOBAL = 0x0, LOCAL = 0x1, GLOBAL = 0x2
ATTR_NHTM_CTRL_MARK
TARGET_TYPE_PROC_CHIP
Setting of Mark control for NHTM.
HTM Trigger Control Register (4:5)
00 local markers are not forwarded to the PowerBus. Both
local and global markers are inserted into the trace
01 local markers are not forwarded to the PowerBus. Only
local markers are inserted into the trace
10 local markers are forwarded to the PowerBus. Only global
markers are inserted into the trace
11 local markers are forwarded to the PowerBus. Markers
are not inserted into the trace (Fabric Trace Mode)
uint8
LOCAL_GLOBAL = 0x0, LOCAL_MARK = 0x1, GLOBAL_MARK = 0x2,
NO_MARK = 0x3
ATTR_CHTM_CTRL_TRIG
TARGET_TYPE_PROC_CHIP
Setting of Trigger control.
HTM Trigger Control Register (0:1)
00 local triggers are not forwarded to the PowerBus, it is
inserted into the trace when tracing. Both local and
global triggers control the HTM
01 local triggers are not forwarded to the PowerBus, it is
inserted into the traCe when tracing. Only local triggers
control the HTM
1x local triggers are forwarded to the PowerBus, it is not
inserted into the trace when tracing. Only global
triggers control the HTM
uint8
LOCAL_GLOBAL = 0x0, LOCAL = 0x1, GLOBAL = 0x2
ATTR_CHTM_CTRL_MARK
TARGET_TYPE_PROC_CHIP
Setting of Mark control.
HTM Trigger Control Register (4:5)
00 local markers are not forwarded to the PowerBus. Both
local and global markers are inserted into the trace
01 local markers are not forwarded to the PowerBus. Only
local markers are inserted into the trace
10 local markers are forwarded to the PowerBus. Only global
markers are inserted into the trace
11 local markers are forwarded to the PowerBus. Markers
are not inserted into the trace (Fabric Trace Mode)
uint8
LOCAL_GLOBAL = 0x0, LOCAL_MARK = 0x1, GLOBAL_MARK = 0x2,
NO_MARK = 0x3
ATTR_HTMSC_CTRL_DBG0_STOP
TARGET_TYPE_PROC_CHIP
Enable Stop on PB Chiplet Debug Trigger 0.
HTM Trigger Control Register (6)
uint8
DISABLE = 0x0, ENABLE = 0x1
ATTR_HTMSC_CTRL_DBG1_STOP
TARGET_TYPE_PROC_CHIP
Enable Stop on PB Chiplet Debug Trigger 1.
HTM Trigger Control Register (7)
uint8
DISABLE = 0x0, ENABLE = 0x1
ATTR_HTMSC_CTRL_RUN_STOP
TARGET_TYPE_PROC_CHIP
Enable trace stop on falling edge of PB chiplet trace run.
HTM Trigger Control Register (8)
uint8
DISABLE = 0x0, ENABLE = 0x1
ATTR_HTMSC_CTRL_OTHER_DBG0_STOP
TARGET_TYPE_PROC_CHIP
Enable Stop using OCC Control.
HTM Trigger Control Register (9)
uint8
DISABLE = 0x0, ENABLE = 0x1
ATTR_HTMSC_CTRL_XSTOP_STOP
TARGET_TYPE_PROC_CHIP
Enable Stop on chiplet XSTOP.
HTM Trigger Control Register (13)
Platform to default to 0x1
uint8
ENABLE = 0x0, DISABLE = 0x1
ATTR_HTMSC_CTRL_CHIP0_STOP
TARGET_TYPE_PROC_CHIP
Stop on PC_TC_DBG_Trigger0
1 = stop trigger Core Debug Trigger 0
0 = ignore Core Debug Trigger 0
uint8
DISABLE = 0x0, ENABLE = 0x1
ATTR_HTMSC_CTRL_CHIP1_STOP
TARGET_TYPE_PROC_CHIP
Stop on PC_TC_DBG_Trigger1
1 = stop trigger Core Debug Trigger 1
0 = ignore Core Debug Trigger 1
uint8
DISABLE = 0x0, ENABLE = 0x1
ATTR_HTMSC_IMA_PDBAR_SPLIT_CORE_MODE
TARGET_TYPE_PROC_CHIP
This bit controls the indexing of the PDBAR address for the
starting address of the write to the PDBAR space.
For CHTM only.
0 'Big Core' mode.
1 'Split Core' mode.
uint8
DISABLE = 0x0, ENABLE = 0x1
ATTR_HTMSC_IMA_PDBAR_SCOPE
TARGET_TYPE_PROC_CHIP
This register defines the starting Scope of the PowerBus
operation. The Scope will be increased if necessary however
it is more efficient to have the request issued according to
where the target memory is located.
000 LOCAL scope
001 Reserved
010 NEAR NODE scope (Nn)
011 GROUP scope (G).
100 REMOTE scope (Rn).
101 VECTORED group scope (Vg).
110 Reserved
111 Reserved
Note 1: Since P9 uses a Group Class MCD, the HTM will always
force a 'Nodal' scope to 'Group' scope. If the scope is
initialized to 'Vectored Group Scope', the HTM_MODE[Vg_Target]
bits must also be initialized.
uint8
LOCAL = 0x0, NEARNODE = 0x2, GROUP = 0x3, REMOTE = 0x4, VECTORED = 0x5
ATTR_HTMSC_IMA_PDBAR_ADDR
TARGET_TYPE_PROC_CHIP
IMA Write Physical Base Address
uint64