ATTR_EFF_DRAM_GEN
TARGET_TYPE_MCS
DRAM Device Type.
Decodes SPD byte 2.
Generation of memory: DDR3, DDR4.
creator: mss_eff_config
consumer: various
firmware notes: none
uint8
EMPTY = 0, DDR3 = 1, DDR4 = 2
2 2
eff_dram_gen
ATTR_EFF_DIMM_TYPE
TARGET_TYPE_MCS
Base Module Type.
Decodes SPD Byte 3 (bits 3~0).
Type of DIMM: RDIMM, UDIMM, LRDIMM as specified by the JEDEC standard.
creator: mss_eff_config
consumer: various
firmware notes: none
uint8
EMPTY = 0, RDIMM = 1, UDIMM = 2, LRDIMM = 3
2 2
eff_dimm_type
ATTR_EFF_HYBRID_MEMORY_TYPE
TARGET_TYPE_MCS
Hybrid Media.
Decodes SPD Byte 3 (bits 6~4)
creator: mss_eff_config
consumer: various
firmware notes: none
uint8
NONE = 0, NVDIMM = 1
2 2
eff_hybrid_memory_type
ATTR_EFF_HYBRID
TARGET_TYPE_MCS
Hybrid.
Decodes SPD Byte 3 (bit 7)
creator: mss_eff_config
consumer: various
firmware notes: none
uint8
NOT_HYBRID = 0, IS_HYBRID= 1
2 2
eff_hybrid
ATTR_EFF_DRAM_DENSITY
TARGET_TYPE_MCS
DRAM Density.
Decodes SPD Byte 4 (bits 3~0).
Total SDRAM capacity per die.
For multi-die stacks (DDP, QDP, or 3DS), this represents
the capacity of each DRAM die in the stack.
creator: mss_eff_config
consumer: various
firmware notes: none
uint8
4G = 4, 8G = 8, 16G = 16
2 2
Gb
eff_dram_density
ATTR_EFF_DRAM_BANK_BITS
TARGET_TYPE_MCS
Number of DRAM bank address bits.
Actual number of banks is 2^N, where
N is the number of bank address bits.
Decodes SPD Byte 4 (bits 5~4).
creator: spd_decoder
consumer: various
firmware notes: none
uint8
2 2
eff_dram_bank_bits
ATTR_EFF_DRAM_BANK_GROUP_BITS
TARGET_TYPE_MCS
Bank Groups Bits.
Decoded SPD Byte 4 (bits 7~6).
Actual number of bank groups is 2^N,
where N is the number of bank address bits.
This value represents the number of bank groups
into which the memory array is divided.
creator: mss_eff_config
consumer: various
firmware notes: none
uint8
2 2
eff_dram_bank_group_bits
ATTR_EFF_DRAM_COLUMN_BITS
TARGET_TYPE_MCS
Column Address Bits.
Decoded SPD Byte 5 (bits 2~0).
Actual number of DRAM columns is 2^N,
where N is the number of column address bits
creator: mss_eff_config
consumer: various
firmware notes: none
uint8
2 2
eff_dram_columns_bits
ATTR_EFF_DRAM_ROW_BITS
TARGET_TYPE_MCS
Row Address Bits.
Decodes Byte 5 (bits 5~3).
Number of DRAM column address bits.
Actual number of DRAM rows is 2^N,
where N is the number of row address bits
creator: mss_eff_config
consumer: various
firmware notes: none
uint8
NUM14 = 14, NUM15 = 15, NUM16 = 16, NUM17 = 17, NUM18 = 18
2 2
eff_dram_row_bits
ATTR_EFF_PRIM_STACK_TYPE
TARGET_TYPE_MCS
Primary SDRAM Package Type.
Decodes Byte 6.
This byte defines the primary set of SDRAMs.
Monolithic = SPD, Multi-load stack = DDP/QDP, Single-load stack = 3DS
creator: mss_eff_config
consumer: various
firmware notes: none
uint8
SDP = 0, DDP_QDP = 1, 3DS = 2
2 2
eff_prim_stack_type
ATTR_EFF_DRAM_PPR
TARGET_TYPE_MCS
Post Package Repair. Used in various locations and is evaluated in mss_eff_cnfg.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
NOT_SUPPORTED = 0, SUPPORTED = 1
2 2
eff_dram_ppr
ATTR_EFF_DRAM_SOFT_PPR
TARGET_TYPE_MCS
Soft Post Package Repair. Used in various locations and is evaluated in mss_eff_cnfg.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
NOT_SUPPORTED = 0, SUPPORTED = 1
2 2
eff_dram_soft_ppr
ATTR_EFF_DRAM_TRCD
TARGET_TYPE_MCS
Minimum RAS to CAS Delay Time
in nck (number of clock cyles).
Decodes SPD byte 25 (7~0) and byte 112 (7~0).
Each memory channel will have a value.
creator: eff_config
consumer: various
firmware notes: none
uint8
2
nck
eff_dram_trcd
ATTR_EFF_DRAM_TRP
TARGET_TYPE_MCS
SDRAM Row Precharge Delay Time
in nck (number of clock cycles).
Decodes SPD byte 26 (bits 7~0) and byte 121 (bits 7~0).
Each memory channel will have a value.
creator: eff_config
consumer: various
uint8
2
nck
eff_dram_trp
ATTR_EFF_DRAM_TRAS
TARGET_TYPE_MCS
Minimum Active to Precharge Delay Time
in nck (number of clock cycles).
Decodes SPD byte 27 (bits 3~0) and byte 28 (7~0).
Each memory channel will have a value.
creator: mss_eff_cnfg_timing
consumer: various
uint8
2
nck
eff_dram_tras
ATTR_EFF_DRAM_TRC
TARGET_TYPE_MCS
Minimum Active to Active/Refresh Delay
in nck (number of clock cyles).
Decodes SPD byte 27 (bits 7~4), byte 29 (bits 7~0), and byte 120.
Each memory channel will have a value.
creator: eff_confg
consumer: various
firmware notes: none
uint8
2
nck
eff_dram_trc
ATTR_EFF_DRAM_TRFC
TARGET_TYPE_MCS
DDR4 Spec defined as Refresh Cycle Time (tRFC).
SPD Spec refers it to the Minimum Refresh Recovery Delay Time.
In nck (number of clock cyles).
Decodes SPD byte 31 (bits 15~8) and byte 30 (bits 7~0) for tRFC1.
Decodes SPD byte 33 (bits 15~8) and byte 32 (bits 7~0) for tRFC2.
Decodes SPD byte 35 (bits 15~8) and byte 34 (bits 7~0) for tRFC4.
Selected tRFC value depends on MRW attribute that selects refresh mode.
For 3DS, The tRFC time to the same logical rank is defined as tRFC_slr and is
specificed as the value as for a monolithic DDR4 SDRAM of equivalent density.
creator: eff_config
consumer: various
firmware notes: none
uint16
2
nck
eff_dram_trfc
ATTR_EFF_DRAM_TFAW
TARGET_TYPE_MCS
Minimum Four Activate Window Delay Time
in nck (number of clock cycles).
Decodes SPD byte 36 (bits 3~0) and byte 37 (bits 7~0).
For 3DS, tFAW time to the same logical rank is defined as
tFAW_slr_x4 or tFAW_slr_x8 (for x4 and x8 devices only) and
specificed as the value as for a monolithic DDR4 SDRAM
equivalent density.
Each memory channel will have a value.
creator: eff_cnfg
consumer: various
firmware notes: none
uint8
2
nck
eff_dram_tfaw
ATTR_EFF_DRAM_TRRD_S
TARGET_TYPE_MCS
Minimum Activate to Activate Delay Time, different bank group
in nck (number of clock cycles).
Decodes SPD byte 38 (bits 7~0).
For 3DS, The tRRD_S time to a different bank group in the
same logical rank is defined as tRRD_slr and is
specificed as the value as for a monolithic
DDR4 SDRAM of equivalent density.
Each memory channel will have a value.
creator: eff_confg
consumer: various
firmware notes: none
uint8
2
nck
eff_dram_trrd_s
ATTR_EFF_DRAM_TRRD_L
TARGET_TYPE_MCS
Minimum Activate to Activate Delay Time, same bank group
in nck (number of clock cycles).
Decodes SPD byte 39 (bits 7~0).
For 3DS, The tRRD_L time to the same bank group in the
same logical rank is defined as tRRD_L_slr and is
specificed as the value as for a monolithic
DDR4 SDRAM of equivalent density.
Each memory channel will have a value.
creator: eff_confg
consumer: various
firmware notes: none
uint8
2
nck
eff_dram_trrd_l
ATTR_EFF_DRAM_TCCD_L
TARGET_TYPE_MCS
Minimum CAS to CAS Delay Time, same bank group
in nck (number of clock cycles).
Decodes SPD byte 40 (bits 7~0) and byte 117 (bits 7~0).
This is for DDR4 MRS6.
Each memory channel will have a value.
Creator: eff_config
Consumer:various
Firmware notes: none
uint8
4NCK = 4, 5NCK = 5, 6NCK = 6, 7NCK = 7, 8NCK = 8
2
nck
eff_dram_tccd_l
ATTR_EFF_DRAM_TWR
TARGET_TYPE_MCS
Minimum Write Recovery Time.
Decodes SPD byte 41 (bits 3~0) and byte 42 (bits 7~0).
Each memory channel will have a value.
creator: mss_eff_cnfg_timing
consumer: various
firmware notes: none
uint8
2
nck
eff_dram_twr
ATTR_EFF_DRAM_TWTR_S
TARGET_TYPE_MCS
Minimum Write to Read Time, different bank group
in nck (number of clock cycles).
Decodes SPD byte 43 (3~0) and byte 44 (bits 7~0).
Each memory channel will have a value.
creator: eff_config
consumer: various
firmware notes: none
uint8
2
nck
eff_dram_twtr_s
ATTR_EFF_DRAM_TWTR_L
TARGET_TYPE_MCS
Minimum Write to Read Time, same bank group
in nck (number of clock cycles).
Decodes byte 43 (7~4) and byte 45 (bits 7~0).
Each memory channel will have a value.
creator: eff_config
consumer: various
firmware notes: none
uint8
2
nck
eff_dram_twtr_l
ATTR_EFF_DRAM_TMAW
TARGET_TYPE_MCS
Maximum Activate Window
in nck (number of clock cycles).
Decodes SPD byte 7 (bits 5~4).
Depends on tREFI multiplier.
Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint16
2
nck
eff_dram_tmaw
ATTR_EFF_DRAM_WIDTH
TARGET_TYPE_MCS
SDRAM Device Width
Decodes SPD Byte 12 (bits 2~0).
Options: X4 (4 bits), X8 (8 bits), X16 (16 bits), X32 (32 bits).
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
X4 = 4, X8 = 8, X16 = 16, X32 = 32
bits
2 2
eff_dram_width
ATTR_EFF_DRAM_RANK_MIX
TARGET_TYPE_MCS
DRAM Device Rank Mix
Decodes SPD Byte 12 (bits 5~3).
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
SYMMETRICAL = 0, ASYMMETICAL = 1
decode from SPD spec
2 2
eff_dram_rank_mix
ATTR_EFF_NUM_RANKS_PER_DIMM
TARGET_TYPE_MCS
Total number of ranks in each DIMM.
For monolithic and multi-load stack modules (SDP/DDP) this is the same as
the number of package ranks per DIMM (SPD Byte 12 bits 5~3).
For single load stack (3DS) modules this value represents the number
of logical ranks per DIMM.
Logical rank refers the individually addressable die in a 3DS stack
and has no meaning for monolithic or multi-load stacked SDRAMs.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
1R = 1, 2R = 2, 4R = 4, 8R = 8, 16R = 16
2 2
eff_num_ranks_per_dimm
ATTR_EFF_REGISTER_TYPE
TARGET_TYPE_MCS
Register Type
Decodes SPD Byte 131
creator: mss_eff_cnfg
consumer: eff_dimm
RCD01 = 0x0, RCD02 = 0x1
uint8
2 2
eff_register_type
ATTR_EFF_DRAM_MFG_ID
TARGET_TYPE_MCS
DRAM Manufacturer ID Code
Decodes SPD Byte 350 and 351
creator: mss_eff_cnfg
consumer: power_thermal::decoder
MICRON = 0x802C, SAMSUNG = 0x80CE, HYNIX = 0x80AD
uint16
2 2
eff_dram_mfg_id
ATTR_EFF_RCD_MFG_ID
TARGET_TYPE_MCS
Register Manufacturer ID Code
Decodes SPD Byte 133 and 134
creator: mss_eff_cnfg
INPHI = 0xB304, MONTAGE = 0x3286, IDT = 0xB380
uint16
2 2
eff_rcd_mfg_id
ATTR_EFF_REGISTER_REV
TARGET_TYPE_MCS
Register Revision Number
Decodes SPD Byte 135
creator: mss_eff_cnfg
uint8
2 2
eff_register_rev
ATTR_EFF_PACKAGE_RANK_MAP
TARGET_TYPE_MCS
Package Rank Map
Decodes SPD Byte 60 - 77 (Bits 7~6)
creator: mss_eff_cnfg
uint8
2 2 18
eff_package_rank_map
ATTR_EFF_NIBBLE_MAP
TARGET_TYPE_MCS
Nibble Map
Decodes SPD Byte 60 - 77 (Bits 5~0)
creator: mss_eff_cnfg
uint8
2 2 18
eff_nibble_map
ATTR_ROW_REPAIR_DATA
TARGET_TYPE_DIMM
Row Repair Data for a DIMM target.
Data for 4 master ranks * 32 bits per row repair
Each row repair contains:
-5 bits: DRAM position (x8: 0-9, x4: 0-19)
-3 bits: slave ranks (0-7)
-2 bits: bank group (0-3)
-3 bits: bank (0-7)
-18 bits: row
-1 bits: unused
uint8
4 4
row_repair_data