ATTR_MSS_VPD_MT_0_VERSION_LAYOUT TARGET_TYPE_MCS MT Keyword Layout Version Number. Increases when attributes are added, removed, or redefined. Does not reset. uint8 num 0 1 vpd_mt_0_version_layout ATTR_MSS_VPD_MT_1_VERSION_DATA TARGET_TYPE_MCS MT Keyword Data Version Number. Increases when data changes with the above layout version. Resets when layout version number increments. uint8 num 1 1 vpd_mt_1_version_data ATTR_MSS_VPD_MT_2_SIGNATURE_HASH TARGET_TYPE_MCS Hash Signature for the MT Keyword. The hash signature is 32bits for 256 bytes of data. uint32 2 4 vpd_mt_2_signature_hash ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CA TARGET_TYPE_MCS Register Clock Driver, Input Bus Termination for Command/Address in tens of Ohms. uint8 IBT_OFF = 0, IBT_100 = 10, IBT_150 = 15, IBT_300 = 30 ohm 6 4 vpd_mt_dimm_rcd_ibt_ca 2 2 ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CKE TARGET_TYPE_MCS Register Clock Driver, Input Bus Termination for Clock Enable in tens of Ohms. uint8 IBT_OFF = 0, IBT_100 = 10, IBT_150 = 15, IBT_300 = 30 ohm 10 4 vpd_mt_dimm_rcd_ibt_cke 2 2 ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CS TARGET_TYPE_MCS Register Clock Driver, Input Bus Termination for Chip Select in tens of Ohms. uint8 IBT_OFF = 0, IBT_100 = 10, IBT_150 = 15, IBT_300 = 30 ohm 14 4 vpd_mt_dimm_rcd_ibt_cs 2 2 ATTR_MSS_VPD_MT_DIMM_RCD_IBT_ODT TARGET_TYPE_MCS Register Clock Driver, Input Bus Termination for On Die Termination in tens of Ohms. uint8 IBT_OFF = 0, IBT_100 = 10, IBT_150 = 15, IBT_300 = 30 ohm 18 4 vpd_mt_dimm_rcd_ibt_odt 2 2 ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS TARGET_TYPE_MCS DQ and DQS Drive Impedance for [Port][DIMM][RANK]. uint8 OHM30 = 30, OHM34 = 34, OHM40 = 40, OHM48 = 48 ohm 22 16 vpd_mt_dram_drv_imp_dq_dqs 2 2 4 ATTR_MSS_VPD_MT_DRAM_RTT_NOM TARGET_TYPE_MCS DRAM side Nominal Termination Resistance in Ohms. uint8 DISABLE = 0, OHM34 = 34, OHM40 = 40, OHM48 = 48, OHM60 = 60, OHM80 = 80, OHM120 = 120, OHM240 = 240 ohm 38 16 vpd_mt_dram_rtt_nom 2 2 4 ATTR_MSS_VPD_MT_DRAM_RTT_PARK TARGET_TYPE_MCS DRAM side Park Termination Resistance in Ohms. uint8 DISABLE = 0, 60OHM = 60, 120OHM = 120, 40OHM = 40, 240OHM = 240, 48OHM = 48, 80OHM = 80, 34OHM = 34 ohm 54 16 vpd_mt_dram_rtt_park 2 2 4 ATTR_MSS_VPD_MT_DRAM_RTT_WR TARGET_TYPE_MCS DRAM side Write Termination Resistance in Ohms. uint8 DISABLE = 0, OHM80 = 80, OHM120 = 120, OHM240 = 240, HIGHZ = 1 ohm 70 16 vpd_mt_dram_rtt_wr 2 2 4 ATTR_MSS_VPD_MT_MC_BIAS_TRIM TARGET_TYPE_MCS Adjusts the receiver internal current bias. ONLY set range 0-7. Default value is 3. [VPD Value] = [Binary bit value set in register] 0 = 110 (Minimal power) 1 = 010 2 = 100 3 = 000 (Default) 4 = 111 5 = 011 6 = 101 7 = 001 (Maximum power) uint8 86 2 vpd_mt_mc_bias_trim 2 ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_RD_UP TARGET_TYPE_MCS Selects the number of enabled pullup branches during READ mode. ONLY set range 0-7. Eg. 0x02 = b010 (1 branch selected), 0x06 = b110 (2 branches selected) Bit 0-2 = DP16 Block 0 (DQ Bits 0-7) Bit 3-5 = DP16 Block 0 (DQ Bits 8-15) Bit 6-8 = DP16 Block 1 (DQ Bits 0-7) Bit 9-11 = DP16 Block 1 (DQ Bits 8-15) Bit 12-14 = DP16 Block 2 (DQ Bits 0-7) Bit 15-17 = DP16 Block 2 (DQ Bits 8-15) Bit 18-20 = DP16 Block 3 (DQ Bits 0-7) Bit 21-23 = DP16 Block 3 (DQ Bits 8-15) Bit 24-26 = DP16 Block 4 (DQ Bits 0-7) Bit 27-29 = DP16 Block 4 (DQ Bits 8-15) uint32 88 8 vpd_mt_mc_dq_acboost_rd_up 2 ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_DOWN TARGET_TYPE_MCS Selects the number of enabled pulldown branches during WRITE mode. ONLY set range 0-7. Eg. 0x02 = b010 (1 branch selected), 0x06 = b110 (2 branches selected) Bit 0-2 = DP16 Block 0 (DQ Bits 0-7) Bit 3-5 = DP16 Block 0 (DQ Bits 8-15) Bit 6-8 = DP16 Block 1 (DQ Bits 0-7) Bit 9-11 = DP16 Block 1 (DQ Bits 8-15) Bit 12-14 = DP16 Block 2 (DQ Bits 0-7) Bit 15-17 = DP16 Block 2 (DQ Bits 8-15) Bit 18-20 = DP16 Block 3 (DQ Bits 0-7) Bit 21-23 = DP16 Block 3 (DQ Bits 8-15) Bit 24-26 = DP16 Block 4 (DQ Bits 0-7) Bit 27-29 = DP16 Block 4 (DQ Bits 8-15) uint32 96 8 vpd_mt_mc_dq_acboost_wr_down 2 ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_UP TARGET_TYPE_MCS Selects the number of enabled pullup branches during WRITE mode. ONLY set range 0-7. Eg. 0x02 = b010 (1 branch selected), 0x06 = b110 (2 branches selected) Bit 0-2 = DP16 Block 0 (DQ Bits 0-7) Bit 3-5 = DP16 Block 0 (DQ Bits 8-15) Bit 6-8 = DP16 Block 1 (DQ Bits 0-7) Bit 9-11 = DP16 Block 1 (DQ Bits 8-15) Bit 12-14 = DP16 Block 2 (DQ Bits 0-7) Bit 15-17 = DP16 Block 2 (DQ Bits 8-15) Bit 18-20 = DP16 Block 3 (DQ Bits 0-7) Bit 21-23 = DP16 Block 3 (DQ Bits 8-15) Bit 24-26 = DP16 Block 4 (DQ Bits 0-7) Bit 27-29 = DP16 Block 4 (DQ Bits 8-15) uint32 104 8 vpd_mt_mc_dq_acboost_wr_up 2 ATTR_MSS_VPD_MT_MC_DQ_CTLE_CAP TARGET_TYPE_MCS Sets the capacitance value in the RC source degeneration. ONLY set range 0-3. (b00 = No capacitor selected, b01 = more caps selected, b10 = even more caps selected, b11 = maximum capacitors selected) Bit 0-1 = DP16 Block 0 Nibble 0 Bit 16-17 = DP16 Block 2 Nibble 0 Bit 32-33 = DP16 Block 4 Nibble 0 Bit 2-3 = DP16 Block 0 Nibble 1 Bit 18-19 = DP16 Block 2 Nibble 1 Bit 34-35 = DP16 Block 4 Nibble 1 Bit 4-5 = DP16 Block 0 Nibble 2 Bit 20-21 = DP16 Block 2 Nibble 2 Bit 36-37 = DP16 Block 4 Nibble 2 Bit 6-7 = DP16 Block 0 Nibble 3 Bit 22-23 = DP16 Block 2 Nibble 3 Bit 38-39 = DP16 Block 4 Nibble 3 Bit 8-9 = DP16 Block 1 Nibble 0 Bit 24-25 = DP16 Block 3 Nibble 0 Bit 10-11 = DP16 Block 1 Nibble 1 Bit 26-27 = DP16 Block 3 Nibble 1 Bit 12-13 = DP16 Block 1 Nibble 2 Bit 28-29 = DP16 Block 3 Nibble 2 Bit 14-15 = DP16 Block 1 Nibble 3 Bit 30-31 = DP16 Block 3 Nibble 3 uint64 112 16 vpd_mt_mc_dq_ctle_cap 2 ATTR_MSS_VPD_MT_MC_DQ_CTLE_RES TARGET_TYPE_MCS Sets the resistance value in the RC source degeneration. Also defines the CTLE's DC Gain. ONLY set range 0-7. (b000 = max resistance, b001 to b110 = decreasing resistance, b111 = min resistance) Bit 0-2 = DP16 Block 0 Nibble 0 Bit 24-26 = DP16 Block 2 Nibble 0 Bit 48-50 = DP16 Block 4 Nibble 0 Bit 3-5 = DP16 Block 0 Nibble 1 Bit 27-29 = DP16 Block 2 Nibble 1 Bit 51-53 = DP16 Block 4 Nibble 1 Bit 6-8 = DP16 Block 0 Nibble 2 Bit 30-32 = DP16 Block 2 Nibble 2 Bit 54-56 = DP16 Block 4 Nibble 2 Bit 9-11 = DP16 Block 0 Nibble 3 Bit 33-35 = DP16 Block 2 Nibble 3 Bit 57-59 = DP16 Block 4 Nibble 3 Bit 12-14 = DP16 Block 1 Nibble 0 Bit 36-38 = DP16 Block 3 Nibble 0 Bit 15-17 = DP16 Block 1 Nibble 1 Bit 39-41 = DP16 Block 3 Nibble 1 Bit 18-20 = DP16 Block 1 Nibble 2 Bit 42-44 = DP16 Block 3 Nibble 2 Bit 21-23 = DP16 Block 1 Nibble 3 Bit 45-47 = DP16 Block 3 Nibble 3 uint64 128 16 vpd_mt_mc_dq_ctle_res 2 ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK TARGET_TYPE_MCS Memory Controller side Drive Impedance for Clock in Ohms. uint8 OHM30 = 30, OHM40 = 40 ohm 144 2 vpd_mt_mc_drv_imp_clk 2 ATTR_MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR TARGET_TYPE_MCS Memory Controller side Drive Impedance for Address, Bank Address, Bank Group and Activate Lines in Ohms. uint8 OHM30 = 30, OHM40 = 40 ohm 146 2 vpd_mt_mc_drv_imp_cmd_addr 2 ATTR_MSS_VPD_MT_MC_DRV_IMP_CNTL TARGET_TYPE_MCS Memory Controller side Drive Impedance for Clock Enable, ODT, Parity, and Reset Lines in Ohms. uint8 OHM30 = 30, OHM40 = 40 ohm 148 2 vpd_mt_mc_drv_imp_cntl 2 ATTR_MSS_VPD_MT_MC_DRV_IMP_CSCID TARGET_TYPE_MCS Memory Controller side Drive Impedance for Chip Select and Chip ID Lines in Ohms. uint8 OHM30 = 30, OHM40 = 40 ohm 150 2 vpd_mt_mc_drv_imp_cscid 2 ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS TARGET_TYPE_MCS Memory Controller side Drive Impedance for [PORT][DP16] Data and Data Strobe Lines in Ohms. uint8 DISABLE = 0, OHM34 = 34, OHM40 = 40, OHM48 = 48, OHM60 = 60, OHM80 = 80, OHM120 = 120, OHM240 = 240 ohm 152 10 vpd_mt_mc_drv_imp_dq_dqs 2 5 ATTR_MSS_VPD_MT_MC_RCV_IMP_DQ_DQS TARGET_TYPE_MCS Memory Controller side Receiver Impedance for [PORT][DP16] Data and Data Strobe Lines in Ohms. uint8 DISABLE = 0, OHM34 = 34, OHM40 = 40, OHM48 = 48, OHM60 = 60, OHM80 = 80, OHM120 = 120, OHM240 = 240 ohm 162 10 vpd_mt_mc_rcv_imp_dq_dqs 2 5 ATTR_MSS_VPD_MT_ODT_RD TARGET_TYPE_MCS READ, On Die Termination triggering bitmap. Use bitmap to determine which ODT to fire for the designated rank. The bits in 8 bit field are [Dimm0 ODT0][Dimm0 ODT1][N/A][N/A][Dimm1 ODT0][Dimm1 ODT1][N/A][N/A] uint8 172 16 vpd_mt_odt_rd 2 2 4 ATTR_MSS_VPD_MT_ODT_WR TARGET_TYPE_MCS WRITE, On Die Termination triggering bitmap. Use bitmap to determine which ODT to fire for the designated rank. The bits in 8 bit field are [Dimm0 ODT0][Dimm0 ODT1][N/A][N/A][Dimm1 ODT0][Dimm1 ODT1][N/A][N/A] uint8 188 16 vpd_mt_odt_wr 2 2 4 ATTR_MSS_VPD_MT_PREAMBLE TARGET_TYPE_MCS Number of clocks used for read/write preamble. Calibration only uses 1 nCK preamble (DEFAULT). Mainline has both 1 nCK and 2 nCK preamble option. The value of "0" means 1 nCK preamble, the value of "1" means 2 nCK preamble. Bit 3 for READ preamble, and Bit 7 for WRITE preamble. E.g. 0b00010001 means 2 nCK preamble for both READ and WRITE uint8 nCK 204 2 vpd_mt_preamble 2 ATTR_MSS_VPD_MT_VREF_DRAM_WR TARGET_TYPE_MCS DRAM side Write Vref setting for DDR4. Bit encode is 01234567. Bit 0 is unused. Bit 1 is the Range. Bits 2-7 is the Value. Refer to the VrefDQ Training Table in JEDEC. uint8 206 2 vpd_mt_vref_dram_wr 2 ATTR_MSS_VPD_MT_VREF_MC_RD TARGET_TYPE_MCS Memory Controller side Read Vref setting. Dividing by 1000 gives you percentage of Vdd uint32 VDD91875 = 91875, VDD91333 = 91333, VDD90791 = 90791, VDD90250 = 90250, VDD89708 = 89708, VDD89166 = 89166, VDD88625 = 88625, VDD88083 = 88083, VDD87541 = 87541, VDD87000 = 87000, VDD86458 = 86458, VDD85916 = 85916, VDD85375 = 85375, VDD84833 = 84833, VDD84291 = 84291, VDD83750 = 83750, VDD83208 = 83208, VDD82666 = 82666, VDD82125 = 82125, VDD81583 = 81583, VDD81041 = 81041, VDD80500 = 80500, VDD79958 = 79958, VDD79416 = 79416, VDD78875 = 78875, VDD78333 = 78333, VDD77791 = 77791, VDD77250 = 77250, VDD76708 = 76708, VDD76166 = 76166, VDD75625 = 75625, VDD75083 = 75083, VDD74541 = 74541, VDD74000 = 74000, VDD73458 = 73458, VDD72916 = 72916, VDD72375 = 72375, VDD71833 = 71833, VDD71291 = 71291, VDD70750 = 70750, VDD70208 = 70208, VDD69666 = 69666, VDD69125 = 69125, VDD68583 = 68583, VDD68041 = 68041, VDD67500 = 67500, VDD66958 = 66958, VDD66416 = 66416, VDD65875 = 65875, VDD65333 = 65333, VDD64791 = 64791, VDD64250 = 64250, VDD63708 = 63708, VDD63166 = 63166, VDD62625 = 62625, VDD62083 = 62083, VDD61541 = 61541, VDD61000 = 61000, VDD60458 = 60458, VDD59916 = 59916, VDD59375 = 59375, VDD58833 = 58833, VDD58291 = 58291, VDD57750 = 57750, VDD57208 = 57208, VDD56666 = 56666, VDD56125 = 56125, VDD55583 = 55583, VDD55041 = 55041, VDD54500 = 54500, VDD53958 = 53958, VDD53416 = 53416, VDD52875 = 52875, VDD52333 = 52333, VDD51791 = 51791, VDD51250 = 51250, VDD50708 = 50708, VDD50166 = 50166, VDD49625 = 49625, VDD49083 = 49083, VDD48541 = 48541, VDD48000 = 48000, VDD47458 = 47458, VDD46916 = 46916, VDD46375 = 46375, VDD45833 = 45833, VDD45291 = 45291, VDD44750 = 44750, VDD44208 = 44208, VDD43666 = 43666, VDD43125 = 43125, VDD42583 = 42583, VDD42041 = 42041, VDD41500 = 41500, VDD40958 = 40958, VDD40416 = 40416, VDD39875 = 39875, VDD39333 = 39333, VDD38791 = 38791, VDD38250 = 38250, VDD37708 = 37708, VDD37166 = 37166, VDD36625 = 36625, VDD36083 = 36083, VDD35541 = 35541, VDD35000 = 35000, VDD34458 = 34458, VDD33916 = 33916, VDD33375 = 33375, VDD32833 = 32833, VDD32291 = 32291, VDD31750 = 31750, VDD31208 = 31208 percent of Vdd 208 8 vpd_mt_vref_mc_rd 2 ATTR_MSS_VPD_MT_WINDAGE_RD_CTR TARGET_TYPE_MCS Derived from calibration/characterization of read centering. Number of windage offset in units of pico-seconds[ps]. Default is 0 Specification of the value in this file is 2's compliment hex int16 signed 216 4 vpd_mt_windage_rd_ctr 2