ATTR_MSS_MRW_SAFEMODE_MEM_THROTTLED_N_COMMANDS_PER_PORT
TARGET_TYPE_SYSTEM
Machine Readable Workbook safe mode throttle value for numerator cfg_nm_n_per_port
Set to below optimum value/ rate.
On a per port (MCA) basis
Also used for emergency mode throttle MBA_FARB4Q_EMERGENCY_N
Used to thermally protect the system in all supported environmental conditions when OCC is not functional
Consumer: thermal_init, initfile
uint16
32
mrw_safemode_mem_throttled_n_commands_per_port
ATTR_MSS_MRW_THERMAL_MEMORY_POWER_LIMIT
TARGET_TYPE_SYSTEM
Machine Readable Workbook Thermal Memory Power Limit
Used to calculate throttles to be at or under the power limit
Per DIMM basis
KEY (0-19): In order
DIMM_SIZE = bits 0-3,
DIMM_GEN = 4-5,
DIMM_TYPE = 6-7,
DIMM_WIDTH = 8-10,
DIMM_DENSITY = 11-13,
DIMM_STACK_TYPE = 14-15,
DRAM_MFGID = 16-18,
DIMMS_PER_PORT = 19-20,
Bits 21-32: Not used
VALUE (bits 32-63) in cW:
VMEM+VPP thermal power limit per DIMM = 32-63
Consumers: eff_config_thermal and bulk_pwr_throttles
uint64
cW
0xfffff80000000794
10
mrw_thermal_memory_power_limit
ATTR_MSS_MRW_PWR_INTERCEPT
TARGET_TYPE_SYSTEM
Machine Readable Workbook Power Curve Intercept for DIMM
Used to get the VDDR and VDDR+VPP power curve for each DIMM
Decoded and used to set ATTR_MSS_TOTAL_PWR_INTERCEPT
Key Value pair
KEY (0-19): In order
DIMM_SIZE = bits 0-3,
DIMM_GEN = 4-5,
DIMM_TYPE = 6-7,
DIMM_WIDTH = 8-10,
DIMM_DENSITY = 11-13,
DIMM_STACK_TYPE = 14-15,
DRAM_MFGID = 16-18,
DIMMS_PER_PORT = 19-20,
Bits 21-32: Not used
VALUE (bits 32-63) in cW:
VMEM power curve = 32-47
VMEM+VPP power curve = 48-63
Consumers: eff_config_thermal
uint64
100
0xfffff8000384044C
mrw_pwr_intercept
ATTR_MSS_MRW_PWR_SLOPE
TARGET_TYPE_SYSTEM
Machine Readable Workbook Power Curve Slope for DIMM
Used to get the VDDR and VDDR+VPP power curve for each DIMM
Decoded and used to set ATTR_MSS_TOTAL_PWR_INTERCEPT
Key Value pair
KEY (0-19): In order
DIMM_SIZE = bits 0-3,
DIMM_GEN = 4-5,
DIMM_TYPE = 6-7,
DIMM_WIDTH = 8-10,
DIMM_DENSITY = 11-13,
DIMM_STACK_TYPE = 14-15,
DRAM_MFGID = 16-18,
DIMMS_PER_PORT = 19-20,
Bits 21-32: Not used
VALUE (bits 32-63) in cW:
VMEM power curve = 32-47
VMEM+VPP power curve = 48-63
Consumers: eff_config_thermal
uint64
100
0xfffff800041A044C
mrw_pwr_slope
ATTR_MSS_MRW_REFRESH_RATE_REQUEST
TARGET_TYPE_SYSTEM
Machine Readable Workbook Refresh Rate
Desired refresh interval used in refresh register 0, MBAREF0Q_CFG_REFRESH_INTERVAL
7.8 us (SINGLE)
3.9 us (DOUBLE)
7.02 us (SINGLE_10_PERCENT_FASTER)
3.51 us (DOUBLE_10_PERCENT_FASTER)
uint8
DOUBLE=0,
SINGLE=1,
SINGLE_10_PERCENT_FASTER=2,
DOUBLE_10_PERCENT_FASTER=3
0x0
mrw_refresh_rate_request
ATTR_MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT
TARGET_TYPE_SYSTEM
Machine Readable Workbook DIMM power curve percent uplift
for this system at max utilization.
Value should be 0 for ISDIMMs
uint8
0x0
mrw_dimm_power_curve_percent_uplift
ATTR_MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT_IDLE
TARGET_TYPE_SYSTEM
Machine Readable Workbook DIMM power curve percent uplift
for this system at idle utilization.
Value should be 0 for ISDIMMs
uint8
0x0
mrw_dimm_power_curve_percent_uplift_idle
ATTR_MSS_MRW_MEM_M_DRAM_CLOCKS
TARGET_TYPE_SYSTEM
Machine Readable Workbook for the number of M DRAM clocks.
One approach to curbing DRAM power usage is by throttling
traffic through a programmable N commands over M window.
uint32
0x00000200
mrw_mem_m_dram_clocks
ATTR_MSS_MRW_MAX_DRAM_DATABUS_UTIL
TARGET_TYPE_SYSTEM
Machine Readable Workbook value for maximum dram data bus utilization in centi percent (c%).
Used to determine memory throttle values.
Max databus utilization on a per port basis
Default to 90%
uint32
c%
0x00002328
mrw_max_dram_databus_util
ATTR_MSS_MRW_MCS_PREFETCH_RETRY_THRESHOLD
TARGET_TYPE_SYSTEM
Option to control MCS prefetch retry threshold, for performance optimization.
This attribute controls the number of retries in the prefetch engine.
Retry threshold available ranges from 16 to 30.
Note: Values outside those ranges will default to 30.
In MRW.
uint8
ATTR_MSS_MRW_IDLE_POWER_CONTROL_REQUESTED
TARGET_TYPE_SYSTEM
Memory power control settings for IDLE powersave mode
Used by OCC when entering idle power-save mode
uint8
OFF = 0x00, POWER_DOWN = 0x01, PD_AND_STR = 0x02, PD_AND_STR_CLK_STOP = 0x03
OFF
mrw_idle_power_control_requested
ATTR_MSS_MRW_VMEM_REGULATOR_POWER_LIMIT_PER_DIMM_ADJ_ENABLE
TARGET_TYPE_SYSTEM
Machine Readable Workbook enablement of the HWP code to adjust the
VMEM regulator power limit based on number of installed DIMMs.
uint8
FALSE = 0, TRUE = 1
ATTR_MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM_DDR3
TARGET_TYPE_SYSTEM
Machine Readable Workbook VMEM regulator power limit per CDIMM assuming a full configuration. Units in cW
Used for Cumulus
Consumed in mss_eff_config_thermal
uint32
cW
ATTR_MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM_DDR4
TARGET_TYPE_SYSTEM
Machine Readable Workbook VMEM regulator power limit per DIMM assuming a full configuration. Units in cW
Consumed in mss_eff_config_thermal
uint32
cW
0x000006A4
mrw_vmem_regulator_power_limit_per_dimm_ddr4
ATTR_MSS_MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR
TARGET_TYPE_SYSTEM
Machine Readable Workbook value for the maximum possible number
of dimms that can be installed under any of the VMEM regulators.
Consumed in eff_config_thermal to calculate mem_watt_target
uint8
mrw_max_number_dimms_possible_per_vmem_regulator
ATTR_MSS_MRW_AVDD_OFFSET_ENABLE
TARGET_TYPE_SYSTEM
Used for to determine whether to apply an offset to AVDD. Supplied by MRW.
uint8
ENABLE = 1, DISABLE = 0
ATTR_MSS_MRW_VDD_OFFSET_ENABLE
TARGET_TYPE_SYSTEM
Used for to determine whether to apply an offset to VDD. Supplied by MRW.
uint8
ENABLE = 1, DISABLE = 0
ATTR_MSS_MRW_VCS_OFFSET_ENABLE
TARGET_TYPE_SYSTEM
Used for to determine whether to apply an offset to VCS. Supplied by MRW.
uint8
ENABLE = 1, DISABLE = 0
ATTR_MSS_MRW_VPP_OFFSET_ENABLE
TARGET_TYPE_SYSTEM
Used for to determine whether to apply an offset to VCS. Supplied by MRW.
uint8
ENABLE = 1, DISABLE = 0
ATTR_MSS_MRW_VDDR_OFFSET_ENABLE
TARGET_TYPE_SYSTEM
Used for to determine whether to apply an offset to VDDR. Supplied by MRW.
uint8
ENABLE = 1, DISABLE = 0
ATTR_MSS_MRW_FINE_REFRESH_MODE
TARGET_TYPE_SYSTEM
Fine refresh mode.
Sets DDR4 MRS3.
ZZ uses normal mode.
From JEDEC DDR4 Spec 1716.78C from 07-2016
Page 47 Table 4.9.1
uint8
NORMAL = 0,
FIXED_2X = 1,
FIXED_4X = 2,
FLY_2X = 5,
FLY_4X = 6
NORMAL
mrw_fine_refresh_mode
ATTR_MSS_MRW_TEMP_REFRESH_RANGE
TARGET_TYPE_SYSTEM
Temperature refresh range.
Sets DDR4 MRS4.
Should be defaulted to extended range.
NORMAL for running at 85 degrees C or less, EXTENDED for 95 or less degrees C
Used for calculating periodic refresh intervals
JEDEC DDR4 spec 1716.78C from 07-2016
page 46 4.8.1
uint8
NORMAL = 0, EXTEND = 1
EXTEND
mrw_temp_refresh_range
ATTR_MSS_MRW_RESET_DELAY_BEFORE_CAL
TARGET_TYPE_SYSTEM
For resetting the phy delay values at the beginning of calling mss_draminit_training. YES means the vaules will be reset.
uint8
YES = 0, NO = 1
YES
mrw_reset_delay_before_cal
ATTR_MSS_MRW_PREFETCH_ENABLE
TARGET_TYPE_SYSTEM
Value of on or off. Determines if prefetching enabled or not.
uint8
ON = 1, OFF = 0
ON
ATTR_MSS_MRW_CLEANER_ENABLE
TARGET_TYPE_SYSTEM
Value of on or off.
Determines if the cleaner of the L4 cache (write modified entries to memory on idle cycles)
enabled or not. See chapter 7 of the Centaur Workbook.
uint8
OFF = 0, ON = 1
OFF
ATTR_MSS_MRW_PERIODIC_MEMCAL_MODE_OPTIONS
TARGET_TYPE_SYSTEM
Describes the settings for periodic calibration for all ports:
Reading left to right. (DEFAULT: 0xD90C -> Byte 0(11011001), Byte 1(00001100))
For each bit: OFF = 0, ON = 1. Setting to 0 indicates to disable periodic memcal.
Byte 0:
0: ZCAL
1: SYSCK_ALIGN
2: RDCENTERING
3: RDLCK_ALIGN
4: DQS_ALIGN
5: RDCLK_UPDATE
6: PER_DUTYCYCLE
7: PERCAL_PWR_DIS
Byte 1:
0: PERCAL_REPEAT
1: PERCAL_REPEAT
2: PERCAL_REPEAT
3: SINGLE_BIT_MPR
4: MBA_CFG_0
5: MBA_CFG_1
6: SPARE
7: SPARE
uint16
encoded settings for periodic calibration
0xD90C
mrw_periodic_memcal_mode_options
ATTR_MSS_MRW_PERIODIC_ZQCAL_MODE_OPTIONS
TARGET_TYPE_SYSTEM
Describes the settings for periodic ZQ calibration for all ports:
Reading left to right. For each bit: OFF = 0, ON = 1.
Setting to 0 indicates to disable periodic zqcal.
Byte 0:
0: ZQCAL
All others reserved for future use
uint16
encoded settings for periodic calibration
0x8000
mrw_periodic_zqcal_mode_options
ATTR_MSS_MRW_DRAM_2N_MODE
TARGET_TYPE_SYSTEM
Allows user to manually turn on and off 2N Mode.
AUTO indicates to use Signal Integrity generated setting (from VPD).
uint8
AUTO = 0, FORCE_TO_1N_MODE = 1, FORCE_TO_2N_MODE = 2
encoded settings for 2N Mode
AUTO
mrw_dram_2n_mode
ATTR_MSS_MRW_UNSUPPORTED_RANK_CONFIG
TARGET_TYPE_MCS
Each MCA value is a 64-bit vector, where each byte represents an unsupported rank configuration.
Each nibble in the byte represents the total count of ranks (master and slave)
on each DIMM. The left-most nibble represents slot 0 and the right represents 1.
uint64
2
0
mrw_unsupported_rank_config
ATTR_MSS_MRW_DRAM_WRITE_CRC
TARGET_TYPE_SYSTEM
Enables DRAM Write CRC
uint8
DISABLE = 0, ENABLE = 1
0
mrw_dram_write_crc
ATTR_MSS_MRW_TEMP_REFRESH_MODE
TARGET_TYPE_SYSTEM
Used in MR4 A3
Temperature refresh mode
Should be defaulted to disable
uint8
DISABLE = 0, ENABLE = 1
0
mrw_temp_refresh_mode
ATTR_MSS_MRW_FORCE_BCMODE_OFF
TARGET_TYPE_SYSTEM
An override switch to shut off broadcast mode
Enum values:
YES: broadcast mode is forced off
NO: broadcast mode uses the default value
uint8
NO = 0, YES = 1
mrw_force_bcmode_off
ATTR_MSS_MRW_NVDIMM_PLUG_RULES
TARGET_TYPE_SYSTEM
A bitmap containing the plug rules for NVDIMM.
1 if a DIMM supports an NVDIMM being plugged in, 0 if it does not
DIMM slot 0 is the left most bit
The index to the bitmap is the position of the DIMM target
As such, a bitmap of 0b10010000, would allow NVDIMM plugged into DIMM0 and DIMM3
Note: this attribute is a 64 bit number to account for 16 DIMM per processor if there is ever a 4 processor system
uint64
0
NO_NVDIMM = 0, NVDIMM_CAPABLE = 1
mrw_nvdimm_plug_rules
ATTR_MSS_MRW_ALLOW_UNSUPPORTED_RCW
TARGET_TYPE_SYSTEM
Switch that allows unsupported raw card references by providing a
default raw card setting.
uint8
1
DISABLE = 0, ENABLE = 1
mrw_allow_unsupported_rcw
ATTR_MSS_MRW_SUPPORTED_DRAM_WIDTH
TARGET_TYPE_SYSTEM
Bitmap of DRAM widths supported by a system. A 1 indicates that the system supports a density.
Enums below represent the the bit location in the attribute for a given DRAM width.
Default value is 0xC -> both x4/x8 supported
uint8
0xc0
X4 = 0, X8 = 1
mrw_supported_dram_width