ATTR_MSS_VOLT_VDDR
TARGET_TYPE_MCBIST
DRAM Voltage, each voltage rail would need to have a value.
Computed in mss_volt C code - in millivolts
creator: mss_volt
consumer: mss_eff_cnfg, others
firmware notes: none
uint32
volt_vddr
ATTR_MSS_VOLT_VPP
TARGET_TYPE_MCBIST
DRAM VPP Voltage, each voltage rail would need to have a value.
Computed in mss_volt C code - in millivolts. 0V - DDR3, 2.5V - DDR4
creator: mss_volt
consumer: mss_eff_cnfg, others
firmware notes: none
uint32
volt_vpp
ATTR_MSS_FREQ_OVERRIDE
TARGET_TYPE_MCBIST
FOR LAB USE ONLY: Frequency override of this memory channel in MT/s
comprising of up to three DIMMs.
Set by config file or an attribute writing program.
Consumed by mss_freq.
The default of AUTO means mss_freq will find the best frequencies given the DIMMs plugged in and other rules.
Otherwise, this is the system frequency.
uint64
AUTO = 0
freq_override
ATTR_MSS_FREQ
TARGET_TYPE_MCBIST
Frequency of this memory channel in MT/s (Mega Transfers per second),
comprising of three DIMMs.
Computed in mss_freq
creator: mss_freq
consumer: mss_eff_cnfg, others
firmware notes: none
uint64
MT1866 = 1866,
MT2133 = 2133,
MT2400 = 2400,
MT2666 = 2666
MT/s
freq
ATTR_MSS_FREQ_BIAS_PERCENTAGE
TARGET_TYPE_MCBIST
Percentage to increase/decrease MEM frequency - two's complement number.
Measured in 100's. So the value of 100 is one percent increase.
This frequency change comes from changing multipliers and dividers to get the desired frequency.
The supported frequencies come from Tim Diemoz.
Creator: platform set this to 0. Users can set this to a valid value.
VALID Values: (TBD % to TBD %) (Tuleta) (TBD % to TBD %) (Glacier)
Set by: PLL settings written by Dave Cadigan
uint32
freq_bias_percentage
ATTR_EFF_DIMM_SPARE
TARGET_TYPE_MCS
Spare DRAM availability. Used in various locations and is computed in mss_eff_cnfg.
creator: mss_eff_cnfg consumer: various firmware notes: load from spd
OBSOLETE: Use ATTR_VPD_DIMM_SPARE
uint8
NO_SPARE = 0, LOW_NIBBLE = 1, HIGH_NIBBLE = 2, FULL_BYTE = 3
2 2 4
eff_dimm_spare
ATTR_EFF_DRAM_WR_VREF
TARGET_TYPE_MCS
DRAM Write Vref.
Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination.
creator: VPD(MT) or mss_eff_cnfg_termination
consumer: various.C and initfile
firmware notes: none
This is the nominal value
This is for DDR3
uint32
VDD420 = 420,
VDD425 = 425,
VDD430 = 430,
VDD435 = 435,
VDD440 = 440,
VDD445 = 445,
VDD450 = 450,
VDD455 = 455,
VDD460 = 460,
VDD465 = 465,
VDD470 = 470,
VDD475 = 475,
VDD480 = 480,
VDD485 = 485,
VDD490 = 490,
VDD495 = 495,
VDD500 = 500,
VDD505 = 505,
VDD510 = 510,
VDD515 = 515,
VDD520 = 520,
VDD525 = 525,
VDD530 = 530,
VDD535 = 535,
VDD540 = 540,
VDD545 = 545,
VDD550 = 550,
VDD555 = 555,
VDD560 = 560,
VDD565 = 565,
VDD570 = 570,
VDD575 = 575
2
eff_dram_wr_vref
ATTR_EFF_DRAM_WR_VREF_SCHMOO
TARGET_TYPE_MCS
Enables for which VREF to use on the WR Schmoo.
The LSB corresponds to the highest WR Vref
uint32
2
eff_dram_wr_vref_schmoo
ATTR_EFF_DRAM_WRDDR4_VREF_SCHMOO
TARGET_TYPE_MCS
Enables for which VREF to use on the WR Schmoo.
The LSB corresponds to the highest WR Vref
uint32
2
eff_dram_wrddr4_vref_schmoo
ATTR_EFF_DIMM_SIZE
TARGET_TYPE_MCS
DIMM Size, in GB Used in various locations and is computed in mss_eff_cnfg.
uint32
2 2
GB
eff_dimm_size
ATTR_EFF_DRAM_CL
TARGET_TYPE_MCS
CAS Latency.
Each memory channel will have a value.
creator: mss_freq
consumer: various
firmware notes: none
uint8
2
eff_dram_cl
ATTR_EFF_DRAM_AL
TARGET_TYPE_MCS
Additive Latency.
Used in various locations and is computed in mss_eff_cnfg_timing.
Each memory channel will have a value.
creator: mss_eff_cnfg_timing
consumer: various
firmware notes: none
uint8
DISABLE = 0, CL_MINUS_1 = 1, CL_MINUS_2 = 2
2
eff_dram_al
ATTR_EFF_DRAM_CWL
TARGET_TYPE_MCS
CAS Write Latency.
Used in various locations and is computed in mss_eff_cnfg_timing.
Each memory channel will have a value.
creator: mss_eff_cnfg_timing
consumer: various
firmware notes: none
uint8
2
eff_dram_cwl
ATTR_EFF_DRAM_RBT
TARGET_TYPE_MCS
Read Burst Type.
Used in various locations and is computed in mss_eff_cnfg.
Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
SEQUENTIAL = 0, INTERLEAVE = 1
2 2
eff_dram_rbt
ATTR_EFF_DRAM_TM
TARGET_TYPE_MCS
Test Mode.
Used in various locations and is computed in mss_eff_cnfg.
Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
NORMAL= 0, TEST = 1
2 2
eff_dram_tm
ATTR_EFF_DRAM_DLL_RESET
TARGET_TYPE_MCS
DLL Reset.
Used in various locations and is computed in mss_eff_cnfg.
Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
NO = 0, YES = 1
2 2
eff_dram_dll_reset
ATTR_EFF_DRAM_DLL_PPD
TARGET_TYPE_MCS
DLL Precharge PD.
Used in various locations and is computed in mss_eff_cnfg.
Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
SLOWEXIT = 0, FASTEXIT = 1
2
eff_dram_dll_ppd
ATTR_EFF_DRAM_DLL_ENABLE
TARGET_TYPE_MCS
DLL Enable.
Used in various locations and is computed in mss_eff_cnfg.
Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
YES = 1, NO = 0
YES
2 2
eff_dram_dll_enable
ATTR_EFF_DRAM_WR_LVL_ENABLE
TARGET_TYPE_MCS
Write Level Enable.
Used in various locations and is computed in mss_eff_cnfg.
Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
DISABLE = 0, ENABLE = 1
2
eff_dram_wr_lvl_enable
ATTR_EFF_DRAM_OUTPUT_BUFFER
TARGET_TYPE_MCS
DRAM Qoff.
Enables or disables DRAM output.
Used in various locations and is computed in mss_eff_cnfg.
Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
ENABLE = 0, DISABLE = 1
2
eff_dram_output_buffer
ATTR_EFF_DRAM_PASR
TARGET_TYPE_MCS
Partial Array Self-Refresh.
Used in various locations and is computed in mss_eff_cnfg.
Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
FULL = 0,
FIRST_HALF = 1,
FIRST_QUARTER = 2,
FIRST_EIGHTH = 3,
LAST_THREE_FOURTH = 4,
LAST_HALF = 5,
LAST_QUARTER = 6,
LAST_EIGHTH = 7
2
eff_dram_pasr
ATTR_EFF_DRAM_ASR
TARGET_TYPE_MCS
Auto Self-Refresh.
Used in various locations and is computed in mss_eff_cnfg.
Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
SRT = 0, ASR = 1
2
eff_dram_asr
ATTR_EFF_DRAM_SRT
TARGET_TYPE_MCS
Self-Refresh Temperature Range.
Used in various locations and is computed in mss_eff_cnfg.
Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
NORMAL = 0, EXTEND = 1
2
eff_dram_srt
ATTR_EFF_MPR_LOC
TARGET_TYPE_MCS
Multi Purpose Register Location.
Used in various locations and is computed in mss_eff_cnfg.
Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
2
eff_mpr_loc
ATTR_EFF_MPR_MODE
TARGET_TYPE_MCS
Multi Purpose Register Mode.
Used in various locations and is computed in mss_eff_cnfg.
Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
DISABLE = 0, ENABLE = 1
2
eff_mpr_mode
ATTR_EFF_DIMM_DDR4_RC00
TARGET_TYPE_MCS
F0RC00: Global Features Control Word.For normal operation, output inversion is always enabled.
For DIMM vendor test purpose, output inversion can be disabled.
When disabled, register tPDM is not guaranteed to be met.
NOTE: Default value - 0x00. Values Range from 0-8.
00 - Normal Operation; 01 - Output Inversion Disabled; 02 - Weak Drive Enabled; 04 - A outputs disabled; 08 - B outputs disabled; So on.
No need to calculate; User can override with desired experimental value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
eff_dimm_ddr4_rc00
ATTR_EFF_DIMM_DDR4_RC01
TARGET_TYPE_MCS
F0RC01 - Clock Driver Enable Control Word.1. Output clocks may be individually turned on or off to conserve power.
The system must read the module SPD to determine which clock outputs are used by the module.
The PLL remains locked on CK_t/CK_c unless the system stops the clock inputs to the DDR4RCD02 to enter the lowest power mode.
Default value - 0x00. Values Range from 0-8. No need to calculate; User can override with desired experimental value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
eff_dimm_ddr4_rc01
ATTR_EFF_DIMM_DDR4_RC02
TARGET_TYPE_MCS
F0RC02: Timing and IBT Control Word; Default value - 0x00.
Values Range from 0-8. No need to calculate;
User can override with desired experimental value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
eff_dimm_ddr4_rc02
ATTR_EFF_DIMM_DDR4_RC03
TARGET_TYPE_MCS
F0RC03 - CA and CS Signals Driver Characteristics Control Word;
Default value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD byte 137, 1st Nibble for CS and CA.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
eff_dimm_ddr4_rc03
ATTR_EFF_DIMM_DDR4_RC04
TARGET_TYPE_MCS
F0RC04 - ODT and CKE Signals Driver Characteristics Control Word;
Default value - 0x05 (Moderate Drive).
Values Range from 00 to 0F. Has to be picked up from SPD byte 137, 2nd Nibble for ODT and CKE.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
eff_dimm_ddr4_rc04
ATTR_EFF_DIMM_DDR4_RC05
TARGET_TYPE_MCS
F0RC05 - Clock Driver Characteristics Control Word;
Default value - 0x05 (Moderate Drive).
Values Range from 00 to 0F. Has to be picked up from SPD byte 138, 2nd Nibble for CK.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
eff_dimm_ddr4_rc05
ATTR_EFF_DIMM_DDR4_RC06_07
TARGET_TYPE_MCS
F0RC06: Command Space Control Word definition;
Default value - 0xF0 (NOP). Values Range from 00 to F0. F0RC07 not used. RDIMM
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
eff_dimm_ddr4_rc06_07
ATTR_EFF_DIMM_DDR4_RC08
TARGET_TYPE_MCS
F0RC06: Command Space Control Word definition;
Default value - 0x03. Values Range from 00 to 08 decimal.
Check the stack height and calculate dynamically;
00 = Stack height_8; 01 = Stack height_4;
02 = Stack height_2;
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
eff_dimm_ddr4_rc08
ATTR_EFF_DIMM_DDR4_RC09
TARGET_TYPE_MCS
F0RC06: Command Space Control Word definition; Default value - 0xF0 (NOP). Values Range from 00 to F0. No need to calculate; User can override with desired experimental value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
eff_dimm_ddr4_rc09
ATTR_EFF_DIMM_DDR4_RC10
TARGET_TYPE_MCS
RDIMM Operating Speed; Read from ATTR_MSS_FREQ; Default value - 00. Values Range from 00 to 09. No need to calculate; User can override with desired experimental value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
eff_dimm_ddr4_rc10
ATTR_EFF_DIMM_DDR4_RC11
TARGET_TYPE_MCS
Operating Voltage VDD and VrefCA Source Control Word; Read from ATTR_MSS_VOLT_VDDR. Default value - 14. Values Range from 00 to 15 decimal. No need to calculate; User can override with desired experimental value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
eff_dimm_ddr4_rc11
ATTR_EFF_DIMM_DDR4_RC12
TARGET_TYPE_MCS
F0RC0C - Training Control Word; Default value - 00. Values Range from 00 to 07 decimal.No need to calculate; User can override with desired experimental value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
eff_dimm_ddr4_rc12
ATTR_EFF_DIMM_DDR4_RC13
TARGET_TYPE_MCS
F0RC0D - DIMM Configuration Control Word; Default value - 0B. Values Range from 00 to 15 decimal. Dynamically calculated using 4 bits[0:3] Bit 0 - Address Mirroring; Bit 1 - Rdimm(1)/Lrdimm (0) ; Bit 2 - N/A ; Bit 3 - CS Mode (Direct / Quad CS mode etc);
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
eff_dimm_ddr4_rc13
ATTR_EFF_DIMM_DDR4_RC14
TARGET_TYPE_MCS
F0RC0E - Parity Control Word; Default value - 00. Check from ATTR_EFF_CA_PARITY and assign; Values Range from 00 to 0F.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
eff_dimm_ddr4_rc14
ATTR_EFF_DIMM_DDR4_RC15
TARGET_TYPE_MCS
F0RC0F - Command Latency Adder Control Word; Default value - 04. Values Range from 00 to 04. No need to calculate; User can override with desired experimental value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
eff_dimm_ddr4_rc15
ATTR_EFF_DIMM_DDR4_RC_1x
TARGET_TYPE_MCS
F0RC1x - Internal VrefCA Control Word; Default value - 00. Values Range from 00 to 3F.No need to calculate; User can override with desired experimental value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
eff_dimm_ddr4_rc_1x
ATTR_EFF_DIMM_DDR4_RC_2x
TARGET_TYPE_MCS
F0RC2x: I2C Bus Control Word; Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
eff_dimm_ddr4_rc_2x
ATTR_EFF_DIMM_DDR4_RC_3x
TARGET_TYPE_MCS
F0RC3x - Fine Granularity RDIMM Operating Speed; Default value = (Operating Freq - 1250)/20. Values Range from 00 to 61 Hex.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
eff_dimm_ddr4_rc_3x
ATTR_EFF_DIMM_DDR4_RC_4x
TARGET_TYPE_MCS
F0RC4x: CW Source Selection Control Word; Default value - 00. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
eff_dimm_ddr4_rc_4x
ATTR_EFF_DIMM_DDR4_RC_5x
TARGET_TYPE_MCS
F0RC5x: CW Destination Selection and Write/Read Additional QxODT[1:0] Signal High; Default value - 00. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
eff_dimm_ddr4_rc_5x
ATTR_EFF_DIMM_DDR4_RC_6x
TARGET_TYPE_MCS
F0RC6x: CW Data Control Word; Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
eff_dimm_ddr4_rc_6x
ATTR_EFF_DIMM_DDR4_RC_7x
TARGET_TYPE_MCS
F0RC7x: IBT Control Word; Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
eff_dimm_ddr4_rc_7x
ATTR_EFF_DIMM_DDR4_RC_8x
TARGET_TYPE_MCS
F0RC8x: ODT Input Buffer/IBT, QxODT Output Buffer and Timing Control Word; Default value - 00. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
eff_dimm_ddr4_rc_8x
ATTR_EFF_DIMM_DDR4_RC_9x
TARGET_TYPE_MCS
F0RC9x1: QxODT[1:0] Write Pattern Control Word; Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
eff_dimm_ddr4_rc_9x
ATTR_EFF_DIMM_DDR4_RC_Ax
TARGET_TYPE_MCS
F0RCAx1: QxODT[1:0] Read Pattern Control Word; Default value - 00.
Values Range from 00 to FF. No need to calculate;
User can override with desired experimental value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
eff_dimm_ddr4_rc_ax
ATTR_EFF_DIMM_DDR4_RC_Bx
TARGET_TYPE_MCS
F0RCBx: IBT and MRS Snoop Control Word; Default value - 07.
Values Range from 00 to FF. No need to calculate;
User can override with desired experimental value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
eff_dimm_ddr4_rc_bx
ATTR_EFF_DIMM_RCD_MIRROR_MODE
TARGET_TYPE_MCS
RCD Mirroring. Used in mss_dram_init and is computed in mss_eff_cnfg.
Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
OFF = 0, ON = 1
2 2
eff_dimm_rcd_mirror_mode
ATTR_EFF_SCHMOO_MODE
TARGET_TYPE_MCS
Specifies the schmoo mode to use during draminit_train_adv.
uint8
FAST = 0, ONE_SLOW = 1, QUARTER_SLOW = 2, HALF_SLOW = 3, FULL_SLOW = 4, ONE_CHAR = 5, QUARTER_CHAR = 6, HALF_CHAR = 7, FULL_CHAR = 8
2
eff_schmoo_mode
ATTR_EFF_SCHMOO_ADDR_MODE
TARGET_TYPE_MCS
Specifies the schmoo mode to use during draminit_train_adv
uint8
FEW_ADDR= 0, QUARTER_ADDR = 1, HALF_ADDR = 2, FULL_ADDR = 3
2
eff_schmoo_addr_mode
ATTR_EFF_SCHMOO_TEST_VALID
TARGET_TYPE_MCS
Specifies the schmoo test to run during draminit_train_adv. Bit wise.
uint8
NONE = 0x00,
MCBIST = 0x01,
WR_EYE = 0x02,
RD_EYE = 0x04,
WR_DQS = 0x08,
RD_DQS = 0x10
2
eff_schmoo_test_valid
ATTR_EFF_SCHMOO_PARAM_VALID
TARGET_TYPE_MCS
Specifies the schmoo parameters to use during draminit_train_adv. Bit wise.
uint8
PARAM_NONE = 0x00,
DELAY_REG = 0x01,
DRV_IMP = 0x02,
SLEW_RATE = 0x04,
WR_VREF = 0x08,
RD_VREF = 0x10,
RCV_IMP = 0x20
2
eff_schmoo_param_valid
ATTR_EFF_SCHMOO_WR_EYE_MIN_MARGIN
TARGET_TYPE_MCS
Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.
uint8
2
eff_schmoo_wr_eye_min_margin
ATTR_EFF_SCHMOO_RD_EYE_MIN_MARGIN
TARGET_TYPE_MCS
Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.
uint8
2
eff_schmoo_rd_eye_min_margin
ATTR_EFF_SCHMOO_DQS_CLK_MIN_MARGIN
TARGET_TYPE_MCS
Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.
uint8
2
eff_schmoo_dqs_clk_min_margin
ATTR_EFF_SCHMOO_RD_GATE_MIN_MARGIN
TARGET_TYPE_MCS
Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.
uint8
2
eff_schmoo_rd_gate_min_margin
ATTR_EFF_SCHMOO_ADDR_CMD_MIN_MARGIN
TARGET_TYPE_MCS
Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.
uint8
2
eff_schmoo_addr_cmd_min_margin
ATTR_EFF_MEMCAL_INTERVAL
TARGET_TYPE_MCS
Specifies the memcal interval in clocks.
uint32
DISABLE = 0
2
eff_memcal_interval
ATTR_EFF_ZQCAL_INTERVAL
TARGET_TYPE_MCS
Specifies the zqcal interval in clocks.
uint32
DISABLE = 0
2
eff_zqcal_interval
ATTR_EFF_IBM_TYPE
TARGET_TYPE_MCS
Specifies the memory topology type. See centaur workbook.
uint8
UNDEFINED = 0,
TYPE_1A = 1,
TYPE_1B = 2,
TYPE_1C = 3,
TYPE_1D = 4,
TYPE_2A = 5,
TYPE_2B = 6,
TYPE_2C = 7,
TYPE_3A = 8,
TYPE_3B = 9,
TYPE_3C = 10,
TYPE_4A = 11,
TYPE_4B = 12,
TYPE_4C = 13,
TYPE_5A = 14,
TYPE_5B = 15,
TYPE_5C = 16,
TYPE_5D = 17,
TYPE_6A = 18,
TYPE_6B = 19,
TYPE_6C = 20,
TYPE_7A = 21,
TYPE_7B = 22,
TYPE_7C = 23,
TYPE_8A = 24,
TYPE_8B = 25,
TYPE_8C = 26
2 2
eff_ibm_type
ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM
TARGET_TYPE_MCS
Specifies the number of master ranks per DIMM.
uint8
2 2
eff_num_master_ranks_per_dimm
ATTR_EFF_DIMM_RANKS_CONFIGED
TARGET_TYPE_MCS
Bit wise representation of master ranks in each DIMM that are used for reads and writes.
Used by PRD.
uint8
2 2
eff_dimm_ranks_configed
ATTR_EFF_NUM_PACKAGES_PER_RANK
TARGET_TYPE_MCS
Specifies the number of DRAM packages per rank.
uint8
2 2
eff_num_packages_per_rank
ATTR_EFF_PRIM_DIE_COUNT
TARGET_TYPE_MCS
Specifies the number of DRAM dies per package.
uint8
2 2
eff_prim_die_count
ATTR_MSS_MEM_THROTTLED_N_COMMANDS_PER_PORT
TARGET_TYPE_MCS
This is the throttled N commands per window
of M DRAM clocks setting for cfg_nm_n_per_port.
uint32
2
mem_throttled_n_commands_per_port
ATTR_MSS_MEM_M_DRAM_CLOCKS
TARGET_TYPE_MCS
This is the throttled M DRAM clocks setting for cfg_nm_m.
creator: mss_eff_cnfg
consumer: mss_eff_config_thermal
firmware notes: none
uint32
2
mem_m_dram_clocks
ATTR_MSS_MEM_THROTTLED_N_COMMANDS_PER_SLOT
TARGET_TYPE_MCS
This is the throttle numerator setting for cfg_nm_n_per_slot
uint32
2
mem_throttled_n_commands_per_slot
ATTR_MSS_MEM_WATT_TARGET
TARGET_TYPE_MCS
Total memory power used to throttle for each dimm
Used to compute the throttles on the channel and/or dimms for OCC
OCC sets after IPL
creator: mss_eff_config
consumer: mss_bulk_pwr_throttle, mss_utils_to_throttle
firmware notes: none.
cW
uint32
2 2
mem_watt_target
ATTR_MSS_TOTAL_PWR_SLOPE
TARGET_TYPE_MCS
VDDR+VPP Power slope value for dimm
creator: mss_eff_config
consumer: mss_bulk_pwr_throttles
uint16
2 2
total_pwr_slope
ATTR_MSS_TOTAL_PWR_INTERCEPT
TARGET_TYPE_MCS
VDDR+VPP Power intercept value for dimm
creator: mss_eff_config
consumer: mss_bulk_pwr_throttles
uint16
2 2
total_pwr_intercept
ATTR_MSS_DIMM_MAXBANDWIDTH_GBS
TARGET_TYPE_MCS
DIMM Max Bandwidth in GBs output from thermal procedures
uint32
2 2
dimm_maxbandwidth_gbs
ATTR_MSS_DIMM_MAXBANDWIDTH_MRS
TARGET_TYPE_MCS
DIMM Max Bandwidth in MRs output from thermal procedures
uint32
2 2
dimm_maxbandwidth_mrs
ATTR_MSS_CHANNEL_PAIR_MAXBANDWIDTH_GBS
TARGET_TYPE_MCS
Channel Pair Max Bandwidth in GBs output from thermal procedures
uint32
2
channel_pair_maxbandwidth_gbs
ATTR_MSS_CHANNEL_PAIR_MAXBANDWIDTH_MRS
TARGET_TYPE_MCS
Channel Pair Max Bandwidth MRs output from thermal procedures
uint32
2
channel_pair_maxbandwidth_mrs
ATTR_MSS_DIMM_MAXPOWER
TARGET_TYPE_MCS
DIMM Max Power output from thermal procedures
uint32
2 2
dimm_maxpower
ATTR_MSS_DATABUS_UTIL
TARGET_TYPE_MCS
Databus utilization limit used to calculate memory throttles and power limit
creator: OCC
consumer: mss_utils_to_throttle
uint32
2
databus_util
ATTR_MSS_PORT_MAXPOWER
TARGET_TYPE_MCS
Channel Pair Max Power output from thermal procedures
uint32
2
port_maxpower
ATTR_MSS_RUNTIME_MEM_THROTTLED_N_COMMANDS_PER_PORT
TARGET_TYPE_MCS
Runtime throttled N commands per
M DRAM clocks setting for cfg_nm_n_per_port.
uint32
2
runtime_mem_throttled_n_commands_per_port
ATTR_MSS_RUNTIME_MEM_M_DRAM_CLOCKS
TARGET_TYPE_MCS
Runtime for M DRAM clocks setting for cfg_nm_m
uint32
2
runtime_mem_m_dram_clocks
ATTR_MSS_RUNTIME_MEM_THROTTLED_N_COMMANDS_PER_SLOT
TARGET_TYPE_MCS
Runtime throttle numerator setting for cfg_nm_n_per_slot
uint32
2
runtime_mem_throttled_n_commands_per_slot
ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR
TARGET_TYPE_MCS
A bit vector (per Dean's request) specifying if a DIMM is functional.
DIMM attributes, such as SIZE, are qualified by this bit vector.
The attribute ANDed 0x80 means port 0, DIMM 0 is functional, 0x40 means port 0, DIMM 1 is functional.
0x08 means port 1, DIMM 0 is functional and 0x04 means port 1 DIMM 1 is functional.
A fully populated system would have the value of 0xCC.
Used in various locations and is computed in mss_eff_cnfg.
Each memory channel will have a value. creator: mss_eff_cnfg consumer: various firmware notes: none
This factors in functionality
uint8
2
eff_dimm_functional_vector
ATTR_EFF_DRAM_LPASR
TARGET_TYPE_MCS
Low Power Auto Self-Refresh.
This is for DDR4 MRS2.
Computed in mss_eff_cnfg.
Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
MANUAL_NORMAL =0, MANUAL_REDUCED = 1, MANUAL_EXTENDED = 2, ASR = 3
2
eff_dram_lpasr
ATTR_EFF_MPR_PAGE
TARGET_TYPE_MCS
MPR Page Selection This is for DDR4 MRS3.
Computed in mss_eff_cnfg.
Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
PG0 = 0, PG1 = 1, PG2 = 2, PG3 = 3
2
eff_mpr_page
ATTR_EFF_GEARDOWN_MODE
TARGET_TYPE_MCS
Gear Down Mode.
This is for DDR4 MRS3.
Computed in mss_eff_cnfg.
Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
HALF =0, QUARTER=1
2
eff_geardown_mode
ATTR_EFF_PER_DRAM_ACCESS
TARGET_TYPE_MCS
Per DRAM accessibility.
This is for DDR4 MRS3.
Computed in mss_eff_cnfg.
Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
DISABLE = 0, ENABLE = 1
2
eff_per_dram_access
ATTR_EFF_TEMP_READOUT
TARGET_TYPE_MCS
Temperature sensor readout.
This is for DDR4 MRS3.
Computed in mss_eff_cnfg.
Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
DISABLE = 0, ENABLE = 1
2
eff_temp_readout
ATTR_EFF_CRC_WR_LATENCY
TARGET_TYPE_MCS
write latency for CRC and DM. This is for DDR4 MRS3.
Computed in mss_eff_cnfg.
Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
4NCK = 4, 5NCK = 5, 6NCK = 6
2
eff_crc_wr_latency
ATTR_EFF_MPR_RD_FORMAT
TARGET_TYPE_MCS
MPR READ FORMAT.
This is for DDR4 MRS3.
Computed in mss_eff_cnfg.
Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
SERIAL = 0, PARALLEL = 1, STAGGERED = 2, RESERVED_TEMP= 3
2
eff_mpr_rd_format
ATTR_EFF_MAX_POWERDOWN_MODE
TARGET_TYPE_MCS
Max Power down mode.
This is for DDR4 MRS4.
Computed in mss_eff_cnfg.
Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
DISABLE = 0, ENABLE = 1
2
eff_max_powerdown_mode
ATTR_EFF_TEMP_REFRESH_MODE
TARGET_TYPE_MCS
Temp controlled ref mode. This is for DDR4 MRS4.
Computed in mss_eff_cnfg.
Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
DISABLE = 0, ENABLE = 1
2
eff_temp_refresh_mode
ATTR_EFF_INTERNAL_VREF_MONITOR
TARGET_TYPE_MCS
Internal Vref Monitor.
This is for DDR4 MRS4.
Computed in mss_eff_cnfg.
Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
DISABLE = 0, ENABLE = 1
2
eff_internal_vref_monitor
ATTR_EFF_CS_CMD_LATENCY
TARGET_TYPE_MCS
CS to CMD/ADDR Latency.
This is for DDR4 MRS4.
Computed in mss_eff_cnfg.
Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
DISABLE = 0, 3CYC = 3, 4CYC = 4, 5CYC = 5, 6CYC = 6, 8CYC = 8
2
eff_cs_cmd_latency
ATTR_EFF_SELF_REF_ABORT
TARGET_TYPE_MCS
Self Refresh Abort.
This is for DDR4 MRS4.
Computed in mss_eff_cnfg.
Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
DISABLE = 0, ENABLE = 1
2
eff_self_ref_abort
ATTR_EFF_RD_PREAMBLE_TRAIN
TARGET_TYPE_MCS
Read Pre amble Training Mode. This is for DDR4 MRS4.
Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
DISABLE = 0, ENABLE = 1
2
eff_rd_preamble_train
ATTR_EFF_RD_PREAMBLE
TARGET_TYPE_MCS
Read Pre amble. This is for DDR4 MRS4.
Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
1NCLK = 0, 2NCLK = 1
2
eff_rd_preamble
ATTR_EFF_WR_PREAMBLE
TARGET_TYPE_MCS
Write Pre amble. This is for DDR4 MRS4.
Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
1NCLK = 0, 2NCLK = 1
2
eff_wr_preamble
ATTR_EFF_CA_PARITY_LATENCY
TARGET_TYPE_MCS
C/A Parity Latency Mode. This is for DDR4 MRS5.
Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
DISABLE = 0, PL4 = 4, PL5 = 5, PL6 = 6, PL8 = 8
2
eff_ca_parity_latency
ATTR_EFF_CRC_ERROR_CLEAR
TARGET_TYPE_MCS
CRC Error Clear. This is for DDR4 MRS5.
Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
CLEAR = 0, ERROR = 1
2
eff_crc_error_clear
ATTR_EFF_CA_PARITY_ERROR_STATUS
TARGET_TYPE_MCS
C/A Parity Error Status. This is for DDR4 MRS5.
Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
CLEAR = 0, ERROR = 1
2
eff_ca_parity_error_status
ATTR_EFF_ODT_INPUT_BUFF
TARGET_TYPE_MCS
ODT Input Buffer during power down. This is for DDR4 MRS5.
Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
ACTIVATED = 0, DEACTIVATED = 1
2
eff_odt_input_buff
ATTR_EFF_CA_PARITY
TARGET_TYPE_MCS
CA Parity Persistance Error. This is for DDR4 MRS5.
Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
DISABLE = 0, ENABLE = 1
2
eff_ca_parity
ATTR_EFF_DATA_MASK
TARGET_TYPE_MCS
Data Mask. This is for DDR4 MRS5.
Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
DISABLE = 0, ENABLE = 1
2
eff_data_mask
ATTR_EFF_WRITE_DBI
TARGET_TYPE_MCS
Write DBI. This is for DDR4 MRS5.
Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
DISABLE = 0, ENABLE = 1
2
eff_write_dbi
ATTR_EFF_READ_DBI
TARGET_TYPE_MCS
Read DBI. This is for DDR4 MRS5.
Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
DISABLE = 0, ENABLE = 1
2
eff_read_dbi
ATTR_EFF_VREF_DQ_TRAIN_VALUE
TARGET_TYPE_MCS
vrefdq_train value. This is for DDR4 MRS6.
Computed in mss_eff_cnfg. Each memory channel will have a value.
Creator: mss_eff_cnfg
Consumer:various
Firmware notes: none
uint8
2 2 4
eff_vref_dq_train_value
ATTR_EFF_VREF_DQ_TRAIN_RANGE
TARGET_TYPE_MCS
vrefdq_train range. This is for DDR4 MRS6.
Computed in mss_eff_cnfg. Each memory channel will have a value.
Creator: mss_eff_cnfg
Consumer:various
Firmware notes: none
uint8
RANGE1 = 0, RANGE2 = 1
2 2 4
eff_vref_dq_train_range
ATTR_EFF_VREF_DQ_TRAIN_ENABLE
TARGET_TYPE_MCS
vrefdq_train enable. This is for DDR4 MRS6.
Computed in mss_eff_cnfg. Each memory channel will have a value.
Creator: mss_eff_cnfg
Consumer:various
Firmware notes: none
uint8
DISABLE = 0, ENABLE = 1
2 2 4
eff_vref_dq_train_enable
ATTR_EFF_WRITE_CRC
TARGET_TYPE_MCS
Write CRC control for DDR4 in MRS2.
Set in mss_eff_cnfg.
Each memory channel will have a value.
Creator: mss_eff_cnfg
Consumer:various
Firmware notes: none
uint8
DISABLE = 0, ENABLE = 1
2
eff_write_crc
ATTR_MSS_CAL_STEP_ENABLE
TARGET_TYPE_MCS
A bit vector denoting valid cal steps to run (0 is left most bit)
[0] EXT_ZQCAL
[1] WR_LEVEL
[2] DQS_ALIGN
[3] RDCLK_ALIGN
[4] READ_CTR
[5] READ_CTR_2D_VREF
[6] WRITE_CTR
[7] WRITE_CTR_2D_VREF
[8] COARSE_WR
[9] COARSE_RD
[10]:[15] Reserved for future use
COARSE_WR and COARSE_RD will be consumed together to form COARSE_LVL.
uint16
2
cal_step_enable
ATTR_MSS_CAL_ABORT_ON_ERROR
TARGET_TYPE_SYSTEM
Whether or not to abort on the first DDR PHY calibration error.
Firmware should always have this set to NO. YES can be used in the
lab for troubleshooting, screening, etc.
uint8
NO = 0, YES = 1
cal_abort_on_error
ATTR_MSS_SLEW_RATE_DATA
TARGET_TYPE_MCS
The 4 bit result of running the slew calibration algorithm at various rates and impedances.
The first dimension is port, the second is the impedance of 24,30,34, and 40 Ohms.
The 3rd dimension is the rate: 3,4,5 or 6 V/ns.
Computed and sent to the correct data blocks in phy_reset.
Also used in advanced training
uint8
2 4 4
slew_rate_data
ATTR_MSS_SLEW_RATE_ADR
TARGET_TYPE_MCS
The 4 bit result of running the slew calibration algorithm at various rates and impedances.
The first dimension is the port. The second is the impedance of 15, 20, 30 and 40 Ohms.
The 3rd dimension is the rate:3, 4,5 or 6 V/ns.
Computed and sent to the correct data blocks in phy_reset.
Also used in advanced training
uint8
2 4 4
slew_rate_adr
ATTR_SCHMOO_MULTIPLE_SETUP_CALL
TARGET_TYPE_MCS
MCBIST for multiple setup
uint8
2
schmoo_multiple_setup_call
ATTR_EFF_BUFFER_LATENCY
TARGET_TYPE_MCS
Additional buffer latency in the case of RDIMMs and LRDIMMs.
It is expected that this value will come from the VPD
uint8
2
eff_buffer_latency
ATTR_EFF_LRDIMM_WORD_X
TARGET_TYPE_MCS
Additional buffer control word for LRDIMM building of the BCW
uint64
2 2
eff_lrdimm_word_x
ATTR_LRDIMM_MR12_REG
TARGET_TYPE_MCS
LRDIMM MR1,2 register.
DRAM Rtt_WR for all ranks, DRAM Rtt_Nom for ranks 0 and 1, DRAM driver impedance for all ranks.
Eff config should set this up.
uint8
2 2
lrdimm_mr12_reg
ATTR_LRDIMM_ADDITIONAL_CNTL_WORDS
TARGET_TYPE_MCS
LRDIMM additional RCD control words as set by DIMM SPD:
F[3,4]RC10, F[3,4]RC11, F[5,6]RC10, F[5,6]RC11, F[7,8]RC10, F[7,8]RC11, F[9,10]RC10, F[9,10]RC11,
F[1]RC8, F[3]RC9, F[3]RC8, F[1]RC11, F[1]RC12, F[1]RC13, F[1]RC14, F[1]RC15.
Eff config should set this up
uint64
2 2
lrdimm_additional_cntl_words
ATTR_LRDIMM_RANK_MULT_MODE
TARGET_TYPE_MCS
LRDIMM rank multiplication mode.
uint8
NORMAL = 0, 2X_MULT = 2, 4X_MULT = 4
2
lrdimm_rank_mult_mode
ATTR_MSS_EFF_VPD_VERSION
TARGET_TYPE_MCS
The lowest VPD Version of the DIMMs attached to the MBA. Comes directly (in ASCII) of the VINI VZ keyword
uint32
2
eff_vpd_version
ATTR_MSS_VOLT_OVERRIDE
TARGET_TYPE_MCBIST
Possible DRAM voltage override.
Firmware notes: Default should be NONE (0x00).
uint8
NONE = 0x00, VOLT_120 = 0x02
volt_override
ATTR_MSS_VDDR_OVERIDE_SPD
TARGET_TYPE_SYSTEM
Possible VDDR voltage override.
uint8
NONE = 0x00, VOLT_1350 = 0x01, VOLT_1200 = 0x02
vddr_overide_spd
ATTR_MSS_VMEM_REGULATOR_MAX_DIMM_COUNT
TARGET_TYPE_SYSTEM
Maximum number of installed DIMMs per VMEM regulator for all VMEM regulators in the system.
uint8
vmem_regulator_max_dimm_count
ATTR_EFF_DRAM_MAC
TARGET_TYPE_MCS
Maximum Activate Count. Used in various locations and is computed in mss_eff_cnfg.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint16
UNTESTED = 0, 700K = 700, 600K = 600, 500K = 500, 400K = 400, 300K = 300, 200K = 200, UNLIMITED = 8
2 2
eff_dram_mac
ATTR_EFF_DRAM_MODULE_BUS_WIDTH
TARGET_TYPE_MCS
Module Memory Bus Width.
Used in various locations and is evaluated in mss_eff_cnfg.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
bits
uint8
2 2
eff_dram_module_bus_width
ATTR_EFF_DIMM_DDR4_BC00
TARGET_TYPE_MCS
F0BCW00 Host Interface DQ RTT_NOM Control
uint8
2 2
eff_dimm_ddr4_bc00
ATTR_EFF_DIMM_DDR4_BC01
TARGET_TYPE_MCS
F0BCW01 Host Interface DQ RTT_WR Control
uint8
2 2
eff_dimm_ddr4_bc01
ATTR_EFF_DIMM_DDR4_BC02
TARGET_TYPE_MCS
F0BCW02 Host Interface DQ RTT_PARK Control
uint8
2 2
eff_dimm_ddr4_bc02
ATTR_EFF_DIMM_DDR4_BC03
TARGET_TYPE_MCS
F0BCW03 Host Interface DQ Driver Control Word
uint8
2 2
eff_dimm_ddr4_bc03
ATTR_EFF_DIMM_DDR4_BC04
TARGET_TYPE_MCS
F0BCW04 DRAM Interface MDQ RTT Control Word
uint8
2 2
eff_dimm_ddr4_bc04
ATTR_EFF_DIMM_DDR4_BC05
TARGET_TYPE_MCS
F0BCW05 DRAM Interface MDQ Driver Control Word
uint8
2 2
eff_dimm_ddr4_bc05
ATTR_EFF_DIMM_DDR4_BC06
TARGET_TYPE_MCS
F0BCW06 Command Space Control Word
uint8
2 2
eff_dimm_ddr4_bc06
ATTR_EFF_DIMM_DDR4_BC07
TARGET_TYPE_MCS
F0BCW07 Rank Presence Control Word
uint8
2 2
eff_dimm_ddr4_bc07
ATTR_EFF_DIMM_DDR4_BC08
TARGET_TYPE_MCS
F0BCW08 RankSelection Control Word
uint8
2 2
eff_dimm_ddr4_bc08
ATTR_EFF_DIMM_DDR4_BC09
TARGET_TYPE_MCS
F0BCW09 Power Saving Settings Control Word
uint8
2 2
eff_dimm_ddr4_bc09
ATTR_EFF_DIMM_DDR4_BC0A
TARGET_TYPE_MCS
F0BCW0A LRDIMM Operating Speed
uint8
2 2
eff_dimm_ddr4_bc0a
ATTR_EFF_DIMM_DDR4_BC0B
TARGET_TYPE_MCS
F0BCW0B Operating Voltage Control Word
uint8
2 2
eff_dimm_ddr4_bc0b
ATTR_EFF_DIMM_DDR4_BC0C
TARGET_TYPE_MCS
F0BCW0C Buffer Training Mode Control Word
uint8
2 2
eff_dimm_ddr4_bc0c
ATTR_EFF_DIMM_DDR4_BC0D
TARGET_TYPE_MCS
F0BCW0D Reserved for future use
uint8
2 2
eff_dimm_ddr4_bc0d
ATTR_EFF_DIMM_DDR4_BC0E
TARGET_TYPE_MCS
F0BCW0E Parity Control Word
uint8
2 2
eff_dimm_ddr4_bc0e
ATTR_EFF_DIMM_DDR4_BC0F
TARGET_TYPE_MCS
F0BCW0F Error Status Word
uint8
2 2
eff_dimm_ddr4_bc0f
ATTR_EFF_DIMM_DDR4_F0BC1x
TARGET_TYPE_MCS
F0BCW1x Buffer Configuration Control Word
uint8
2 2
eff_dimm_ddr4_f0bc1x
ATTR_EFF_DIMM_DDR4_F30BC2x
TARGET_TYPE_MCS
F30BCW2x Lower Nibble DRAM Interface Receive Enable Training Control Word for ranks 0 to 3
uint8
2 2
eff_dimm_ddr4_f30bc2x
ATTR_EFF_DIMM_DDR4_F30BC3x
TARGET_TYPE_MCS
F30BCW3x Lower Nibble DRAM Interface Receive Enable Training Control Word for ranks 0 to 3
uint8
2 2
eff_dimm_ddr4_f30bc3x
ATTR_EFF_DIMM_DDR4_F30BC4x
TARGET_TYPE_MCS
F30BCW4x Lower Nibble MDQS Read Delay Control Word for ranks 0 to 3
uint8
2 2
eff_dimm_ddr4_f30bc4x
ATTR_EFF_DIMM_DDR4_F30BC5x
TARGET_TYPE_MCS
F30BCW5x Upper Nibble MDQS Read Delay Control Word for ranks 0 to 3
uint8
2 2
eff_dimm_ddr4_f30bc5x
ATTR_EFF_DIMM_DDR4_F0BC6x
TARGET_TYPE_MCS
F0BCW6x Fine Granularity Frequency Operating Speed Control Word
uint8
2 2
eff_dimm_ddr4_f0bc6x
ATTR_EFF_DIMM_DDR4_F70BC7x
TARGET_TYPE_MCS
F70BCW7x Function Space Selector Control Word
uint8
2 2
eff_dimm_ddr4_f70bc7x
ATTR_EFF_DIMM_DDR4_F30BC8x
TARGET_TYPE_MCS
F30BCW8x Lower Nibble MDQ-MDQS Write Delay Control Word for ranks 0 to 3
uint8
2 2
eff_dimm_ddr4_f30bc8x
ATTR_EFF_DIMM_DDR4_F30BC9x
TARGET_TYPE_MCS
F30BCW9x Upper Nibble MDQ-MDQS Write Delay Control Word for ranks 0 to 3
uint8
2 2
eff_dimm_ddr4_f30bc9x
ATTR_EFF_DIMM_DDR4_F30BCAx
TARGET_TYPE_MCS
F30BCWAx Lower Nibble DRAM Interface Write Leveling Control Word for ranks 0 to 3
uint8
2 2
eff_dimm_ddr4_f30bcax
ATTR_EFF_DIMM_DDR4_F30BCBx
TARGET_TYPE_MCS
F30BCWBx Upper Nibble DRAM Interface Write Leveling Control Word for ranks 0 to 3
uint8
2 2
eff_dimm_ddr4_f30bcbx
ATTR_EFF_DIMM_DDR4_F0BCCx
TARGET_TYPE_MCS
F0BCWCx Lower/Upper Nibble Additional Cycles of DRAM Interface Receive Enable Control Word for rank 0
uint8
2 2
eff_dimm_ddr4_f0bccx
ATTR_EFF_DIMM_DDR4_F0BCDx
TARGET_TYPE_MCS
F0BCWDx Lower/Upper Nibble Additional Cycles of DRAM Interface Write Leveling Control Word for rank 0
uint8
2 2
eff_dimm_ddr4_f0bcdx
ATTR_EFF_DIMM_DDR4_F0BCEx
TARGET_TYPE_MCS
F0BCWEx Lower/Upper Nibble Additional Cycles of DRAM Interface Write Leveling Control Word for rank 0
uint8
2 2
eff_dimm_ddr4_f0bcex
ATTR_EFF_DIMM_DDR4_F0BCFx
TARGET_TYPE_MCS
F0BCWFx Lower/Upper Nibble Additional Cycles of DRAM Interface Write Leveling Control Word for rank 2
uint8
2 2
eff_dimm_ddr4_f0bcfx
ATTR_EFF_DIMM_DDR4_F1BCCx
TARGET_TYPE_MCS
F1BCWCx Lower/Upper Nibble Additional Cycles of DRAM Interface Receive Enable Control Word for rank 1
uint8
2 2
eff_dimm_ddr4_f1bccx
ATTR_EFF_DIMM_DDR4_F1BCDx
TARGET_TYPE_MCS
F1BCWDx Lower/Upper Nibble Additional Cycles of DRAM Interface Write Leveling Control Word for rank 1
uint8
2 2
eff_dimm_ddr4_f1bcdx
ATTR_EFF_DIMM_DDR4_F1BCEx
TARGET_TYPE_MCS
F1BCWEx Lower/Upper Nibble Additional Cycles of DRAM Interface Receive Enable Control Word for rank 3
uint8
2 2
eff_dimm_ddr4_f1bcex
ATTR_EFF_DIMM_DDR4_F1BCFx
TARGET_TYPE_MCS
F1BCWFx Lower/Upper Nibble Additional Cycles of DRAM Interface Write Leveling Control Word for rank 3
uint8
2 2
eff_dimm_ddr4_f1bcfx
ATTR_EFF_DIMM_DDR4_F4BC0x
TARGET_TYPE_MCS
F4BCW0x MRS0 snooped settings
uint8
2 2
eff_dimm_ddr4_f4bc0x
ATTR_EFF_DIMM_DDR4_F4BC1x
TARGET_TYPE_MCS
F4BCW1x MRS1 snooped settings
uint8
2 2
eff_dimm_ddr4_f4bc1x
ATTR_EFF_DIMM_DDR4_F4BC2x
TARGET_TYPE_MCS
F4BCW2x MRS2 snooped settings
uint8
2 2
eff_dimm_ddr4_f4bc2x
ATTR_EFF_DIMM_DDR4_F4BC3x
TARGET_TYPE_MCS
F4BCW3x MRS3 snooped settings
uint8
2 2
eff_dimm_ddr4_f4bc3x
ATTR_EFF_DIMM_DDR4_F4BC4x
TARGET_TYPE_MCS
F4BCW4x MRS4 snooped settings
uint8
2 2
eff_dimm_ddr4_f4bc4x
ATTR_EFF_DIMM_DDR4_F4BC5x
TARGET_TYPE_MCS
F4BCW5x MRS5 snooped settings
uint8
2 2
eff_dimm_ddr4_f4bc5x
ATTR_EFF_DIMM_DDR4_F4BC6x
TARGET_TYPE_MCS
F4BCW6x MRS6 snooped settings
uint8
2 2
eff_dimm_ddr4_f4bc6x
ATTR_EFF_DIMM_DDR4_F5BC0x
TARGET_TYPE_MCS
F5BCW0x Upper and Lower MPR bits[7:0] for U0
uint8
2 2
eff_dimm_ddr4_f5bc0x
ATTR_EFF_DIMM_DDR4_F5BC1x
TARGET_TYPE_MCS
F5BCW1x Upper and Lower MPR bits[15:8] for U1
uint8
2 2
eff_dimm_ddr4_f5bc1x
ATTR_EFF_DIMM_DDR4_F5BC2x
TARGET_TYPE_MCS
F5BCW2x Upper and Lower MPR bits[23:16] for U2
uint8
2 2
eff_dimm_ddr4_f5bc2x
ATTR_EFF_DIMM_DDR4_F5BC3x
TARGET_TYPE_MCS
F5BCW3x Upper and Lower MPR bits[31:24] for U3
uint8
2 2
eff_dimm_ddr4_f5bc3x
ATTR_EFF_DIMM_DDR4_F5BC5x
TARGET_TYPE_MCS
F5BCW5x Host Interface Vref Control Word
uint8
2 2
eff_dimm_ddr4_f5bc5x
ATTR_EFF_DIMM_DDR4_F5BC6x
TARGET_TYPE_MCS
F5BCW6x DRAM Interface Vref Control Word
uint8
2 2
eff_dimm_ddr4_f5bc6x
ATTR_EFF_DIMM_DDR4_F6BC0x
TARGET_TYPE_MCS
F6BCW0x Upper and Lower MPR bits[39:32] for U4
uint8
2 2
eff_dimm_ddr4_f6bc0x
ATTR_EFF_DIMM_DDR4_F6BC1x
TARGET_TYPE_MCS
F6BCW1x Upper and Lower MPR bits[47:40] for U5
uint8
2 2
eff_dimm_ddr4_f6bc1x
ATTR_EFF_DIMM_DDR4_F6BC2x
TARGET_TYPE_MCS
F6BCW2x Upper and Lower MPR bits[55:48] for U6
uint8
2 2
eff_dimm_ddr4_f6bc2x
ATTR_EFF_DIMM_DDR4_F6BC3x
TARGET_TYPE_MCS
F6BCW3x Upper and Lower MPR bits[63:56] for U7
uint8
2 2
eff_dimm_ddr4_f6bc3x
ATTR_EFF_DIMM_DDR4_F6BC4x
TARGET_TYPE_MCS
F6BCW4x Buffer Training Configuration Control Word
uint8
2 2
eff_dimm_ddr4_f6bc4x
ATTR_EFF_DIMM_DDR4_F6BC5x
TARGET_TYPE_MCS
F6BCW5x Buffer Training Status Word
uint8
2 2
eff_dimm_ddr4_f6bc5x
ATTR_EFF_DIMM_DDR4_F74BC8x
TARGET_TYPE_MCS
F74BCW8x MDQ0/4 -Read Delay Control Word for ranks 0 to 3
uint8
2 2
eff_dimm_ddr4_f74bc8x
ATTR_EFF_DIMM_DDR4_F74BC9x
TARGET_TYPE_MCS
F74BCW9x MDQ1/5 -Read Delay Control Word for ranks 0 to 3
uint8
2 2
eff_dimm_ddr4_f74bc9x
ATTR_EFF_DIMM_DDR4_F74BCAx
TARGET_TYPE_MCS
F74BCWAx MDQ2/6 -Read Delay Control Word for ranks 0 to 3
uint8
2 2
eff_dimm_ddr4_f74bcax
ATTR_EFF_DIMM_DDR4_F74BCBx
TARGET_TYPE_MCS
F74BCWBx MDQ3/7 -Read Delay Control Word for ranks 0 to 3
uint8
2 2
eff_dimm_ddr4_f74bcbx
ATTR_EFF_DIMM_DDR4_F74BCCx
TARGET_TYPE_MCS
F74BCWCx MDQ0/4-MDQS Write Delay Control Word for ranks 0 to 3
uint8
2 2
eff_dimm_ddr4_f74bccx
ATTR_EFF_DIMM_DDR4_F74BCDx
TARGET_TYPE_MCS
F74BCWDx MDQ1/5-MDQS Write Delay Control Word for ranks 0 to 3
uint8
2 2
eff_dimm_ddr4_f74bcdx
ATTR_EFF_DIMM_DDR4_F74BCEx
TARGET_TYPE_MCS
F74BCWEx MDQ2/6-MDQS Write Delay Control Word for ranks 0 to 3
uint8
2 2
eff_dimm_ddr4_f74bcex
ATTR_EFF_DIMM_DDR4_F74BCFx
TARGET_TYPE_MCS
F74BCWFx MDQ3/7-MDQS Write Delay Control Word for ranks 0 to 3
uint8
2 2
eff_dimm_ddr4_f74bcfx
ATTR_EFF_DRAM_RON
TARGET_TYPE_MCS
DRAM Ron.
Used in various locations and comes from the MT keyword of the VPD
OHM48 is for DDR4.
uint8
INVALID = 0, OHM34 = 34, OHM40 = 40, OHM48 = 48
2 2
eff_dram_ron
ATTR_EFF_DRAM_TDQS
TARGET_TYPE_MCS
TDQS.
Used in various locations and is computed in mss_eff_cnfg.
Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
DISABLE = 0, ENABLE = 1
2
eff_dram_tdqs
ATTR_EFF_DRAM_TREFI
TARGET_TYPE_MCS
Average Refresh Interval (tREFI) in nck (number of clock cycles).
creator: mss_eff_config
consumer: various
firmware notes: none
uint16
2
nck
eff_dram_trefi
ATTR_EFF_DRAM_TRTP
TARGET_TYPE_MCS
Internal Read to Precharge Delay.
Each memory channel will have a value.
creator: mss_eff_cnfg_timing
consumer: various
firmware notes: none
uint8
2
eff_dram_trtp
ATTR_EFF_DRAM_TRFC_DLR
TARGET_TYPE_MCS
Minimum Refresh Recovery Delay Time
in nck (number of clock cyles).
Selected tRFC value (tRFC_dl1, tRFC_dl2, or tRFC_dl4)
depends on MRW attribute that selects fine refresh mode (x1, x2, x4).
For 3DS, The tRFC time to different logical ranks are defined as tRFC_dlr
creator: eff_config
consumer: various
firmware notes: none
uint8
2
nck
eff_dram_trfc_dlr
ATTR_EFF_DRAM_TFAW_DLR
TARGET_TYPE_MCS
Minimum Four Activate Window Delay Time
in nck (number of clock cycles).
For 3DS, the tFAW time to different logical ranks are defined as tFAW_dlr
Each memory channel will have a value.
creator: eff_cnfg
consumer: various
firmware notes: none
uint8
2
nck
eff_dram_tfaw_dlr
ATTR_EFF_DRAM_TXS
TARGET_TYPE_MCS
Exit Self-Refresh to commands not requiring a locked DLL.
In nck (number of clock cycles).
Each memory channel will have a value.
creator: eff_config
consumer: various
firmware notes: none
uint8
2
nck
eff_dram_txs
ATTR_MSS_IGNORE_PLUG_RULES
TARGET_TYPE_MCS
Set to IGNORE if you want to ignore the plug rules. Sometimes
this is needed in a partial-good configuration
uint8
NO = 0, YES = 1
bool
ignore_plug_rules