/* IBM_PROLOG_BEGIN_TAG                                                   */
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/* $Source: src/import/chips/p9/procedures/hwp/pm/p9_setup_evid.H $       */
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/* OpenPOWER HostBoot Project                                             */
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///
/// @file  p9_setup_evid.H
/// @brief Setup External Voltage IDs
///
// *HWP HW Owner        : Greg Still <stillgs@us.ibm.com>
// *HWP FW Owner        : Prasad Bg Ranganath <prasadbgr@in.ibm.com>
// *Team                : PM
// *Consumed by         : HB
// *Level               : 3
///

#ifndef __P9_SETUP_EVID_H__
#define __P9_SETUP_EVID_H__

#include <fapi2.H>
#include <p9_pstate_parameter_block.H>

enum P9_SETUP_EVID_CONSTANTS
{
// By convention, the Pstate GPE will use bridge 0.  Other entities
// will use bridge 1
    BRIDGE_NUMBER = 1,

// Default voltages if mailbox -> attributes are not setup
    AVSBUS_RETRY_COUNT = 5,
    VDD_SETUP = 6,
    VDN_SETUP = 7,
    VCS_SETUP = 8,

};



extern "C"
{

/// @typedef VoltageConfigActions_t
/// enum of the two actions this hwp can perform
/// it can either compute default voltage settings
/// otherwise it can apply voltage setting to the system
/// @typedef p9_setup_evid_FP_t
/// function pointer typedef definition for HWP call support
    typedef fapi2::ReturnCode (*p9_setup_evid_FP_t) (
        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&,
        const VoltageConfigActions_t);

/// @brief Set safe mode values to DPLL fmult,fmin and fmax
/// @param [in]  i_target TARGET_TYPE_PROC_CHIP
/// @param [in]  i_freq_proc_refclock_khz proc clock frequency
/// @param [in]  i_proc_dpll_divider proc dpll divider value
//@return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
    fapi2::ReturnCode
    p9_setup_dpll_values (const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
                          const uint32_t  i_freq_proc_refclock_khz,
                          const uint32_t i_proc_dpll_divider);


/// @brief Read attributes containing part's boot voltages(VDD,VCS and VDN)
/// and set these voltage using the AVSBUS interface (VDD, VDN and VCS).
///
/// @param [in] i_target TARGET_TYPE_PROC_CHIP
/// @param [in] i_action Describes whether you wish to COMPUTE voltage settings
///                      during the step or if you would like to APPLY them.
/// @attr
/// @attritem  ATTR_VCS_BOOT_VOLTAGE  - 1mV grandularity setting for VCS rail
/// @attritem  ATTR_VDD_BOOT_VOLTAGE  - 1mV grandularity setting for VDD rail
/// @attritem  ATTR_VDN_BOOT_VOLTAGE  - 1mV grandularity setting for VDN rail
/// @attritem  ATTR_VDD_AVSBUS_BUSNUM - AVSBus Number having the VDD VRM
/// @attritem  ATTR_VDD_AVSBUS_RAIL   - AVSBus Rail number for VDD VRM
/// @attritem  ATTR_VDN_AVSBUS_BUSNUM - AVSBus Number having the VDN VRM
/// @attritem  ATTR_VDN_AVSBUS_RAIL   - AVSBus Rail number for VDN VRM
/// @attritem  ATTR_VCS_AVSBUS_BUSNUM - AVSBus Number having the VCS VRM
/// @attritem  ATTR_VCS_AVSBUS_RAIL   - AVSBus Rail number for VCS VRM
///
///@return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
    fapi2::ReturnCode
    p9_setup_evid(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
                  const VoltageConfigActions_t i_action);

/// @brief update VDD,VDN and VCS voltage values
/// @param [in]  i_target TARGET_TYPE_PROC_CHIP
/// @param [in]  i_bus_num AVS BUS number
/// @param [in]  i_rail_select AVS bus rail select
/// @param [in]  i_voltage_mv voltage value in mv
/// @param [in]  i_evid_value EVID setup mode
/// @param [in]  i_ext_vrm_step_size_mv Maximum VRM step size in mv
//@return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
    fapi2::ReturnCode
    p9_setup_evid_voltageWrite(
        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
        const uint8_t i_bus_num,
        const uint8_t i_rail_select,
        const uint32_t i_voltage_mv,
        const uint32_t i_ext_vrm_step_size_mv,
        const P9_SETUP_EVID_CONSTANTS i_evid_value);

} // extern C

#endif  // __P9_SETUP_EVID_H__