/* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ /* $Source: chips/p9/procedures/hwp/perv/p9_mem_startclocks.H $ */ /* */ /* IBM CONFIDENTIAL */ /* */ /* EKB Project */ /* */ /* COPYRIGHT 2015,2016 */ /* [+] International Business Machines Corp. */ /* */ /* */ /* The source code for this program is not published or otherwise */ /* divested of its trade secrets, irrespective of what has been */ /* deposited with the U.S. Copyright Office. */ /* */ /* IBM_PROLOG_END_TAG */ //------------------------------------------------------------------------------ /// @file p9_mem_startclocks.H /// /// @brief Start clocks on MBA/MCAs //------------------------------------------------------------------------------ // *HWP HW Owner : Abhishek Agarwal // *HWP HW Backup Owner : Srinivas V Naga // *HWP FW Owner : Sunil kumar // *HWP Team : Perv // *HWP Level : 2 // *HWP Consumed by : HB //------------------------------------------------------------------------------ #ifndef _P9_MEM_STARTCLOCKS_H_ #define _P9_MEM_STARTCLOCKS_H_ #include typedef fapi2::ReturnCode (*p9_mem_startclocks_FP_t)( const fapi2::Target&); /// @brief --drop vital fence /// --reset abstclk muxsel and syncclk muxsel /// --Module align chiplets /// --Module clock start stop /// --Check clock stat SL, NSL , ARY /// --drop chiplet fence /// --check checkstop register /// --clear flush inhibit to go into flush mode /// /// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target /// @return FAPI2_RC_SUCCESS if success, else error code. extern "C" { fapi2::ReturnCode p9_mem_startclocks(const fapi2::Target& i_target_chip); } #endif