/* IBM_PROLOG_BEGIN_TAG                                                   */
/* This is an automatically generated prolog.                             */
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/* $Source: src/import/chips/p9/procedures/hwp/nest/p9_pcie_config.H $    */
/*                                                                        */
/* OpenPOWER HostBoot Project                                             */
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/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
/* [+] International Business Machines Corp.                              */
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/* IBM_PROLOG_END_TAG                                                     */
///
/// @file p9_pcie_config.H
/// @brief Perform PCIE Phase2 init sequence (FAPI2)
///

// *HWP HWP Owner: Joe McGill jmcgill@us.ibm.com
// *HWP FW Owner: Thi Tran thi@us.ibm.com
// *HWP Team: Nest
// *HWP Level: 3
// *HWP Consumed by: HB

#ifndef _P9_PCIE_CONFIG_H_
#define _P9_PCIE_CONFIG_H_

//------------------------------------------------------------------------------
// Includes
//------------------------------------------------------------------------------
#include <fapi2.H>

//------------------------------------------------------------------------------
// Structure definitions
//------------------------------------------------------------------------------

//function pointer typedef definition for HWP call support
typedef fapi2::ReturnCode (*p9_pcie_config_FP_t) (
    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);

//-----------------------------------------------------------------------------------
// Constant definitions
//-----------------------------------------------------------------------------------

// PBCQ Hardware Configuration Register Cache Inject Rate enablement
const uint8_t PEC_PBCQHWCFG_REG_PE_WR_CACHE_INJECT_RATE = 46;
const uint8_t PEC_PBCQHWCFG_REG_PE_WR_CACHE_INJECT_RATE_LEN = 3;

//------------------------------------------------------------------------------
// Function prototype
//------------------------------------------------------------------------------

extern "C" {

/// @brief Perform PCIE Phase2 init sequence
/// @param[in] i_target P9 chip target
/// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
//
    fapi2::ReturnCode p9_pcie_config(
        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target);
} //extern"C"

#endif //_P9_PCIE_CONFIG_H_