/* IBM_PROLOG_BEGIN_TAG                                                   */
/* This is an automatically generated prolog.                             */
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/* $Source: src/import/chips/p9/procedures/hwp/nest/p9_npu_scominit.C $   */
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/* OpenPOWER HostBoot Project                                             */
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/* Contributors Listed Below - COPYRIGHT 2015,2019                        */
/* [+] International Business Machines Corp.                              */
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/* IBM_PROLOG_END_TAG                                                     */
///
/// @file p9_npu_scominit.C
/// @brief Apply SCOM overrides for the NPU, enable NVLINK refclocks
///
// *HWP HWP Owner: Joe McGill <jmcgill@us.ibm.com>
// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
// *HWP Team: Nest
// *HWP Level: 3
// *HWP Consumed by: HB

//------------------------------------------------------------------------------
// Includes
//------------------------------------------------------------------------------
#include <p9_npu_scominit.H>
#include <p9_npu_scom.H>
#include <p9_nv_ref_clk_enable.H>
#include <p9_misc_scom_addresses.H>
#include <p9_misc_scom_addresses_fld.H>
#include <p9a_misc_scom_addresses.H>
#include <p9a_misc_scom_addresses_fld.H>
#include <p9_fbc_ioo_dl_npu_scom.H>

//------------------------------------------------------------------------------
// Constant definitions
//------------------------------------------------------------------------------
const uint64_t PU_NPU_SM2_XTS_ATRMISS_POST_P9NDD1 = 0x501164AULL;


//------------------------------------------------------------------------------
// Function definitions
//------------------------------------------------------------------------------

/// NOTE: description in header
fapi2::ReturnCode p9_npu_scominit(
    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
{
    FAPI_DBG("Entering ...");

    uint8_t l_npu_enabled;

    // check to see if NPU region in N3 chiplet is enabled
    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NPU_REGION_ENABLED,
                           i_target,
                           l_npu_enabled),
             "Error from FAPI_ATTR_GET (ATTR_PROC_NPU_REGION_ENABLED)");

    if (l_npu_enabled)
    {
        fapi2::ReturnCode l_rc;
        fapi2::buffer<uint64_t> l_atrmiss = 0;
        fapi2::ATTR_CHIP_EC_FEATURE_SETUP_BARS_NPU_DD1_ADDR_Type l_npu_p9n_dd1;
        fapi2::ATTR_CHIP_EC_FEATURE_SETUP_BARS_NPU_AXONE_ADDR_Type l_axone;

        // read attribute to determine if P9N DD1 NPU addresses should be used
        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_SETUP_BARS_NPU_DD1_ADDR,
                               i_target,
                               l_npu_p9n_dd1),
                 "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_SETUP_BARS_NPU_DD1_ADDR)");

        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_SETUP_BARS_NPU_AXONE_ADDR,
                               i_target,
                               l_axone),
                 "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_SETUP_BARS_NPU_AXONE_ADDR)");

        // apply NPU SCOM inits from initfile
        FAPI_DBG("Invoking p9.npu.scom.initfile...");
        FAPI_EXEC_HWP(l_rc,
                      p9_npu_scom,
                      i_target,
                      fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>());

        if (l_rc)
        {
            FAPI_ERR("Error from p9.npu.scom.initfile");
            fapi2::current_err = l_rc;
            goto fapi_try_exit;
        }

        // Enable obus for NPU for Axone
        if (l_axone)
        {
            auto l_obus_targets = i_target.getChildren<fapi2::TARGET_TYPE_OBUS>();

            for (auto l_obus_target : l_obus_targets)
            {
                FAPI_DBG("Invoking p9.fbc.ioo_dl.npu.scom.initfile...");
                FAPI_EXEC_HWP(l_rc,
                              p9_fbc_ioo_dl_npu_scom,
                              l_obus_target,
                              i_target,
                              fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>());

                if (l_rc)
                {
                    FAPI_ERR("Error from p9.fbc.ioo_dl.npu.scom.initfile");
                    fapi2::current_err = l_rc;
                    goto fapi_try_exit;
                }

            }
        }

        // apply additional SCOM inits
        l_atrmiss.setBit<PU_NPU_SM2_XTS_ATRMISS_FLAG_MAP>()
        .setBit<PU_NPU_SM2_XTS_ATRMISS_ENA>();

        if (!l_axone)
        {
            FAPI_TRY(fapi2::putScomUnderMask(i_target,
                                             ((l_npu_p9n_dd1) ?
                                              (PU_NPU_SM2_XTS_ATRMISS) :
                                              (PU_NPU_SM2_XTS_ATRMISS_POST_P9NDD1)),
                                             l_atrmiss,
                                             l_atrmiss),
                     "Error from putScomUnderMask (0x%08X)",
                     ((l_npu_p9n_dd1) ?
                      (PU_NPU_SM2_XTS_ATRMISS) :
                      (PU_NPU_SM2_XTS_ATRMISS_POST_P9NDD1)));
        }
        else
        {
            // Axone
            // P9A_PU_NPU2_NTL1_XTS_ATRMISS = 0x050112FA
            FAPI_TRY(fapi2::putScomUnderMask(i_target, P9A_PU_NPU2_NTL1_XTS_ATRMISS, l_atrmiss, l_atrmiss),
                     "Error from putScomUnderMask (0x%08X)",
                     P9A_PU_NPU2_NTL1_XTS_ATRMISS);
            // P9A__NTL1_XTS_ATRMISS = 0x050116FA
            FAPI_TRY(fapi2::putScomUnderMask(i_target, P9A__NTL1_XTS_ATRMISS, l_atrmiss, l_atrmiss),
                     "Error from putScomUnderMask (0x%08X)",
                     P9A__NTL1_XTS_ATRMISS);
        }

        // enable NVLINK refclocks
        FAPI_DBG("Invoking p9_nv_ref_clk_enable...");
        FAPI_EXEC_HWP(l_rc, p9_nv_ref_clk_enable, i_target);

        if (l_rc)
        {
            FAPI_ERR("Error from p9_nv_ref_clk_enable");
            fapi2::current_err = l_rc;
            goto fapi_try_exit;
        }
    }
    else
    {
        FAPI_DBG("Skipping NPU initialization");
    }

fapi_try_exit:
    FAPI_DBG("Exiting ...");
    return fapi2::current_err;
}