/* IBM_PROLOG_BEGIN_TAG                                                   */
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/* $Source: src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.H $ */
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/* OpenPOWER HostBoot Project                                             */
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/* IBM_PROLOG_END_TAG                                                     */

///
/// @file p9_mss_ddr_phy_reset.H
/// @brief  Reset and initialize the DDR PHY
///
// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com>
// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com>
// *HWP Team: Memory
// *HWP Level: 3
// *HWP Consumed by: FSP:HB

#ifndef P9_MSS_DDR_PHY_RESET_H_
#define P9_MSS_DDR_PHY_RESET_H_

#include <fapi2.H>

typedef fapi2::ReturnCode (*p9_mss_ddr_phy_reset_FP_t)(const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target);

extern "C"
{

///
/// @brief Reset the DDR PHY
/// @param[in] i_target, the McBIST of the ports of the dram you're training
/// @return FAPI2_RC_SUCCESS iff ok
///
    fapi2::ReturnCode p9_mss_ddr_phy_reset( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target );
}

#endif