/* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ /* $Source: src/import/chips/p9/procedures/hwp/memory/lib/workarounds/seq_workarounds.H $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ /* Contributors Listed Below - COPYRIGHT 2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ /* You may obtain a copy of the License at */ /* */ /* http://www.apache.org/licenses/LICENSE-2.0 */ /* */ /* Unless required by applicable law or agreed to in writing, software */ /* distributed under the License is distributed on an "AS IS" BASIS, */ /* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ /* implied. See the License for the specific language governing */ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ /// /// @file workarounds/seq_workarounds.H /// @brief Workarounds for the SEQ logic blocks /// Workarounds are very deivce specific, so there is no attempt to generalize /// this code in any way. /// // *HWP HWP Owner: Louis Stermole // *HWP HWP Backup: Stephen Glancy // *HWP Team: Memory // *HWP Level: 2 // *HWP Consumed by: FSP:HB #ifndef _MSS_WORKAROUNDS_SEQ_H_ #define _MSS_WORKAROUNDS_SEQ_H_ #include #include #include namespace mss { namespace workarounds { namespace seq { /// /// @brief ODT Config workaround /// For Nimbus DD1, ODT2 and ODT3 bits are swapped in each of the PHY config registers /// @param[in] i_target the fapi2 target of the port /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok /// @note This function is called during the phy scom init procedure, after the initfile is /// processed. /// fapi2::ReturnCode odt_config( const fapi2::Target& i_target ); } // close namespace seq } // close namespace workarounds } // close namespace mss #endif