SyntaxVersion = 3

target_type 0 TARGET_TYPE_PROC_CHIP;


##########################
# DD1 WORKAROUNDS
##########################

# FOR DD1 Prefetch Limit needs to be scan init to 0 because SCOM is broken (HW366248)
#      Always OR-ed with previous value. Essentially we can only set bits, not clear. So we want to scan init to 0.
#      these are n1 n3
ispy  MC01.PORT0.ATCL.CL.CLSCOM.MCPERF0_PREFETCH_LIMIT [when=L && ATTR_CHIP_EC_FEATURE_HW366248] {
  spyv;
  0b111111;
}
ispy  MC01.PORT1.ATCL.CL.CLSCOM.MCPERF0_PREFETCH_LIMIT [when=L && ATTR_CHIP_EC_FEATURE_HW366248] {
  spyv;
  0b111111;
}
ispy  MC01.PORT2.ATCL.CL.CLSCOM.MCPERF0_PREFETCH_LIMIT [when=L && ATTR_CHIP_EC_FEATURE_HW366248] {
  spyv;
  0b111111;
}
ispy  MC01.PORT3.ATCL.CL.CLSCOM.MCPERF0_PREFETCH_LIMIT [when=L && ATTR_CHIP_EC_FEATURE_HW366248] {
  spyv;
  0b111111;
}
ispy  MC23.PORT0.ATCL.CL.CLSCOM.MCPERF0_PREFETCH_LIMIT [when=L && ATTR_CHIP_EC_FEATURE_HW366248] {
  spyv;
  0b111111;
}
ispy  MC23.PORT1.ATCL.CL.CLSCOM.MCPERF0_PREFETCH_LIMIT [when=L && ATTR_CHIP_EC_FEATURE_HW366248] {
  spyv;
  0b111111;
}
ispy  MC23.PORT2.ATCL.CL.CLSCOM.MCPERF0_PREFETCH_LIMIT [when=L && ATTR_CHIP_EC_FEATURE_HW366248] {
  spyv;
  0b111111;
}
ispy  MC23.PORT3.ATCL.CL.CLSCOM.MCPERF0_PREFETCH_LIMIT [when=L && ATTR_CHIP_EC_FEATURE_HW366248] {
  spyv;
  0b111111;
}

# Static hpc_wr/ig_wr CL reservation
# Complicated order dependent sequence to do with SCOMs, easier with scans
# these are n1 n3
ispy  MC01.PORT0.ATCL.CL.CLSCOM.MCPERF0_WR_RSVD_LOWER_OR_STATIC_LIMIT [when=L] {
  spyv;
  8;
}
ispy  MC01.PORT1.ATCL.CL.CLSCOM.MCPERF0_WR_RSVD_LOWER_OR_STATIC_LIMIT [when=L] {
  spyv;
  8;
}
ispy  MC01.PORT2.ATCL.CL.CLSCOM.MCPERF0_WR_RSVD_LOWER_OR_STATIC_LIMIT [when=L] {
  spyv;
  8;
}
ispy  MC01.PORT3.ATCL.CL.CLSCOM.MCPERF0_WR_RSVD_LOWER_OR_STATIC_LIMIT [when=L] {
  spyv;
  8;
}
ispy  MC23.PORT0.ATCL.CL.CLSCOM.MCPERF0_WR_RSVD_LOWER_OR_STATIC_LIMIT [when=L] {
  spyv;
  8;
}
ispy  MC23.PORT1.ATCL.CL.CLSCOM.MCPERF0_WR_RSVD_LOWER_OR_STATIC_LIMIT [when=L] {
  spyv;
  8;
}
ispy  MC23.PORT2.ATCL.CL.CLSCOM.MCPERF0_WR_RSVD_LOWER_OR_STATIC_LIMIT [when=L] {
  spyv;
  8;
}
ispy  MC23.PORT3.ATCL.CL.CLSCOM.MCPERF0_WR_RSVD_LOWER_OR_STATIC_LIMIT [when=L] {
  spyv;
  8;
}


# WORKAROUND FOR HW375544 / HW392781 

ispy  MC01.PORT0.READ.RDATA_ARY(0,1,2,3).SFT_MAC.SFT.LCBCNTL_BLK_RF.CLOCKGATE_DISABLE [when=L && ATTR_CHIP_EC_FEATURE_MSS_HW392781_RDARRAY_CLKGATE] {
  spyv;
  0b1;
}
ispy  MC01.PORT1.READ.RDATA_ARY(0,1,2,3).SFT_MAC.SFT.LCBCNTL_BLK_RF.CLOCKGATE_DISABLE [when=L && ATTR_CHIP_EC_FEATURE_MSS_HW392781_RDARRAY_CLKGATE] {
  spyv;
  0b1;
}
ispy  MC01.PORT2.READ.RDATA_ARY(0,1,2,3).SFT_MAC.SFT.LCBCNTL_BLK_RF.CLOCKGATE_DISABLE [when=L && ATTR_CHIP_EC_FEATURE_MSS_HW392781_RDARRAY_CLKGATE] {
  spyv;
  0b1;
}
ispy  MC01.PORT3.READ.RDATA_ARY(0,1,2,3).SFT_MAC.SFT.LCBCNTL_BLK_RF.CLOCKGATE_DISABLE [when=L && ATTR_CHIP_EC_FEATURE_MSS_HW392781_RDARRAY_CLKGATE] {
  spyv;
  0b1;
}
ispy  MC23.PORT0.READ.RDATA_ARY(0,1,2,3).SFT_MAC.SFT.LCBCNTL_BLK_RF.CLOCKGATE_DISABLE [when=L && ATTR_CHIP_EC_FEATURE_MSS_HW392781_RDARRAY_CLKGATE] {
  spyv;
  0b1;
}
ispy  MC23.PORT1.READ.RDATA_ARY(0,1,2,3).SFT_MAC.SFT.LCBCNTL_BLK_RF.CLOCKGATE_DISABLE [when=L && ATTR_CHIP_EC_FEATURE_MSS_HW392781_RDARRAY_CLKGATE] {
  spyv;
  0b1;
}
ispy  MC23.PORT2.READ.RDATA_ARY(0,1,2,3).SFT_MAC.SFT.LCBCNTL_BLK_RF.CLOCKGATE_DISABLE [when=L && ATTR_CHIP_EC_FEATURE_MSS_HW392781_RDARRAY_CLKGATE] {
  spyv;
  0b1;
}
ispy  MC23.PORT3.READ.RDATA_ARY(0,1,2,3).SFT_MAC.SFT.LCBCNTL_BLK_RF.CLOCKGATE_DISABLE [when=L && ATTR_CHIP_EC_FEATURE_MSS_HW392781_RDARRAY_CLKGATE] {
  spyv;
  0b1;
}

# HW400932 
ispy  MC01.PBI01.LCBCNTL_BLK1.CLOCKGATE_DISABLE [when=L && ATTR_CHIP_EC_FEATURE_HW400932] {
  spyv;
  1;
}
ispy  MC01.PBI23.LCBCNTL_BLK1.CLOCKGATE_DISABLE [when=L && ATTR_CHIP_EC_FEATURE_HW400932] {
  spyv;
  1;
}
ispy  MC23.PBI01.LCBCNTL_BLK1.CLOCKGATE_DISABLE [when=L && ATTR_CHIP_EC_FEATURE_HW400932] {
  spyv;
  1;
}
ispy  MC23.PBI23.LCBCNTL_BLK1.CLOCKGATE_DISABLE [when=L && ATTR_CHIP_EC_FEATURE_HW400932] {
  spyv;
  1;
}