/* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ /* $Source: src/import/chips/p9/common/include/p9n2_mc_scom_addresses_fld.H $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ /* Contributors Listed Below - COPYRIGHT 2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ /* You may obtain a copy of the License at */ /* */ /* http://www.apache.org/licenses/LICENSE-2.0 */ /* */ /* Unless required by applicable law or agreed to in writing, software */ /* distributed under the License is distributed on an "AS IS" BASIS, */ /* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ /* implied. See the License for the specific language governing */ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ /// /// @file p9_mc_scom_addresses_fld.H /// @brief Defines constants for scom addresses /// // *HWP HWP Owner: Ben Gass // *HWP FW Owner: Thi Tran // *HWP Team: SOA // *HWP Level: 3 // *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE #ifndef __P9N2_MC_SCOM_ADDRESSES_FLD_H #define __P9N2_MC_SCOM_ADDRESSES_FLD_H #include static const uint8_t P9N2_MCS_PORT02_AACR_BUFFER = 0 ; static const uint8_t P9N2_MCS_PORT02_AACR_ADDRESS = 1 ; static const uint8_t P9N2_MCS_PORT02_AACR_ADDRESS_LEN = 9 ; static const uint8_t P9N2_MCS_PORT02_AACR_AUTOINC = 10 ; static const uint8_t P9N2_MCA_WREITE_AACR_BUFFER = 0 ; static const uint8_t P9N2_MCA_WREITE_AACR_ADDRESS = 1 ; static const uint8_t P9N2_MCA_WREITE_AACR_ADDRESS_LEN = 9 ; static const uint8_t P9N2_MCA_WREITE_AACR_AUTOINC = 10 ; static const uint8_t P9N2_MCA_WREITE_AACR_ECCGEN = 11 ; static const uint8_t P9N2_MCS_PORT02_AADR_DATA = 0 ; static const uint8_t P9N2_MCS_PORT02_AADR_DATA_LEN = 64 ; static const uint8_t P9N2_MCA_AADR_DATA = 0 ; static const uint8_t P9N2_MCA_AADR_DATA_LEN = 64 ; static const uint8_t P9N2_MCS_PORT02_AAER_TAG_ECC = 0 ; static const uint8_t P9N2_MCS_PORT02_AAER_TAG_ECC_LEN = 9 ; static const uint8_t P9N2_MCA_AAER_TAG_ECC = 0 ; static const uint8_t P9N2_MCA_AAER_TAG_ECC_LEN = 9 ; static const uint8_t P9N2_MCA_ACTION0_FIR = 0 ; static const uint8_t P9N2_MCA_ACTION0_FIR_LEN = 64 ; static const uint8_t P9N2_MCA_ACTION1_FIR = 0 ; static const uint8_t P9N2_MCA_ACTION1_FIR_LEN = 64 ; static const uint8_t P9N2_MCA_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR = 0 ; static const uint8_t P9N2_MCA_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN = 16 ; static const uint8_t P9N2_MCA_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR = 16 ; static const uint8_t P9N2_MCA_ADDR_TRAP_REG_RESERVED_LAST_LT = 17 ; static const uint8_t P9N2_MCA_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR = 18 ; static const uint8_t P9N2_MCA_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN = 13 ; static const uint8_t P9N2_MCA_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY = 31 ; static const uint8_t P9N2_MCA_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR = 32 ; static const uint8_t P9N2_MCA_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION = 33 ; static const uint8_t P9N2_MCA_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER = 34 ; static const uint8_t P9N2_MCA_ATOMIC_LOCK_MASK_LATCH_REG_MASK = 0 ; static const uint8_t P9N2_MCA_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCSARRERRINJQ_CCS_ARRAY_CE_ERR_INJ_MODE = 0 ; static const uint8_t P9N2_MCBIST_CCSARRERRINJQ_CCS_ARRAY_CE_ERR_INJ = 1 ; static const uint8_t P9N2_MCBIST_CCSARRERRINJQ_CCS_ARRAY_UE_ERR_INJ_MODE = 2 ; static const uint8_t P9N2_MCBIST_CCSARRERRINJQ_CCS_ARRAY_UE_ERR_INJ = 3 ; static const uint8_t P9N2_MCBIST_CCSARRERRINJQ_RESERVED_4 = 4 ; static const uint8_t P9N2_MCBIST_CCSARRERRINJQ_DISABLE_2N_MODE = 5 ; static const uint8_t P9N2_MCBIST_CCSARRERRINJQ_RESERVED_6_14 = 6 ; static const uint8_t P9N2_MCBIST_CCSARRERRINJQ_RESERVED_6_14_LEN = 9 ; static const uint8_t P9N2_MCBIST_CCSARRERRINJQ_READ_RESPONSE_DELAY_ENABLE = 15 ; static const uint8_t P9N2_MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE0 = 16 ; static const uint8_t P9N2_MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE0_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE1 = 32 ; static const uint8_t P9N2_MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE1_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE2 = 48 ; static const uint8_t P9N2_MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE2_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_CNTLQ_START = 0 ; static const uint8_t P9N2_MCBIST_CCS_CNTLQ_STOP = 1 ; static const uint8_t P9N2_MCBIST_CCS_FIXED_DATA0Q_DATA_0_63 = 0 ; static const uint8_t P9N2_MCBIST_CCS_FIXED_DATA0Q_DATA_0_63_LEN = 64 ; static const uint8_t P9N2_MCBIST_CCS_FIXED_DATA1Q_DATA_64_79 = 0 ; static const uint8_t P9N2_MCBIST_CCS_FIXED_DATA1Q_DATA_64_79_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_0_13 = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_0_13_LEN = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_17 = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_BANK_GROUP_1 = 15 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_RESETN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_BANK_0_1 = 17 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_BANK_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_BANK_GROUP_0 = 19 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_ACTN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_16 = 21 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_15 = 22 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_14 = 23 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_CKE = 24 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_CKE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_RESERVED_28_31 = 28 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_RESERVED_28_31_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_CSN_0_1 = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_CSN_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_CID_0_1 = 34 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_CID_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_CSN_2_3 = 36 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_CSN_2_3_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_CID_2 = 38 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_RESERVED_39_47 = 39 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_RESERVED_39_47_LEN = 9 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_ODT = 48 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_ODT_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_RESERVED_52_55 = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_RESERVED_52_55_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_CAL_TYPE = 56 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_CAL_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_PARITY = 60 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_DDR_BANK_2 = 61 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_LOOP_BREAK_MODE = 62 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_00_LOOP_BREAK_MODE_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_0_13 = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_0_13_LEN = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_17 = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_BANK_GROUP_1 = 15 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_RESETN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_BANK_0_1 = 17 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_BANK_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_BANK_GROUP_0 = 19 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_ACTN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_16 = 21 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_15 = 22 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_14 = 23 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_CKE = 24 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_CKE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_RESERVED_28_31 = 28 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_RESERVED_28_31_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_CSN_0_1 = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_CSN_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_CID_0_1 = 34 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_CID_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_CSN_2_3 = 36 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_CSN_2_3_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_CID_2 = 38 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_RESERVED_39_47 = 39 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_RESERVED_39_47_LEN = 9 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_ODT = 48 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_ODT_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_RESERVED_52_55 = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_RESERVED_52_55_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_CAL_TYPE = 56 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_CAL_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_PARITY = 60 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_DDR_BANK_2 = 61 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_LOOP_BREAK_MODE = 62 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_01_LOOP_BREAK_MODE_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_0_13 = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_0_13_LEN = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_17 = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_BANK_GROUP_1 = 15 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_RESETN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_BANK_0_1 = 17 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_BANK_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_BANK_GROUP_0 = 19 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_ACTN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_16 = 21 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_15 = 22 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_14 = 23 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_CKE = 24 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_CKE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_RESERVED_28_31 = 28 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_RESERVED_28_31_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_CSN_0_1 = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_CSN_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_CID_0_1 = 34 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_CID_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_CSN_2_3 = 36 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_CSN_2_3_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_CID_2 = 38 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_RESERVED_39_47 = 39 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_RESERVED_39_47_LEN = 9 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_ODT = 48 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_ODT_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_RESERVED_52_55 = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_RESERVED_52_55_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_CAL_TYPE = 56 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_CAL_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_PARITY = 60 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_DDR_BANK_2 = 61 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_LOOP_BREAK_MODE = 62 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_02_LOOP_BREAK_MODE_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_0_13 = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_0_13_LEN = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_17 = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_BANK_GROUP_1 = 15 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_RESETN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_BANK_0_1 = 17 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_BANK_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_BANK_GROUP_0 = 19 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_ACTN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_16 = 21 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_15 = 22 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_14 = 23 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_CKE = 24 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_CKE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_RESERVED_28_31 = 28 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_RESERVED_28_31_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_CSN_0_1 = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_CSN_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_CID_0_1 = 34 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_CID_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_CSN_2_3 = 36 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_CSN_2_3_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_CID_2 = 38 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_RESERVED_39_47 = 39 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_RESERVED_39_47_LEN = 9 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_ODT = 48 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_ODT_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_RESERVED_52_55 = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_RESERVED_52_55_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_CAL_TYPE = 56 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_CAL_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_PARITY = 60 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_DDR_BANK_2 = 61 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_LOOP_BREAK_MODE = 62 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_03_LOOP_BREAK_MODE_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_0_13 = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_0_13_LEN = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_17 = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_BANK_GROUP_1 = 15 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_RESETN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_BANK_0_1 = 17 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_BANK_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_BANK_GROUP_0 = 19 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_ACTN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_16 = 21 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_15 = 22 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_14 = 23 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_CKE = 24 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_CKE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_RESERVED_28_31 = 28 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_RESERVED_28_31_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_CSN_0_1 = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_CSN_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_CID_0_1 = 34 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_CID_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_CSN_2_3 = 36 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_CSN_2_3_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_CID_2 = 38 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_RESERVED_39_47 = 39 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_RESERVED_39_47_LEN = 9 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_ODT = 48 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_ODT_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_RESERVED_52_55 = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_RESERVED_52_55_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_CAL_TYPE = 56 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_CAL_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_PARITY = 60 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_DDR_BANK_2 = 61 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_LOOP_BREAK_MODE = 62 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_04_LOOP_BREAK_MODE_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_0_13 = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_0_13_LEN = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_17 = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_BANK_GROUP_1 = 15 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_RESETN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_BANK_0_1 = 17 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_BANK_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_BANK_GROUP_0 = 19 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_ACTN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_16 = 21 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_15 = 22 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_14 = 23 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_CKE = 24 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_CKE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_RESERVED_28_31 = 28 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_RESERVED_28_31_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_CSN_0_1 = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_CSN_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_CID_0_1 = 34 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_CID_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_CSN_2_3 = 36 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_CSN_2_3_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_CID_2 = 38 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_RESERVED_39_47 = 39 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_RESERVED_39_47_LEN = 9 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_ODT = 48 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_ODT_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_RESERVED_52_55 = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_RESERVED_52_55_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_CAL_TYPE = 56 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_CAL_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_PARITY = 60 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_DDR_BANK_2 = 61 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_LOOP_BREAK_MODE = 62 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_05_LOOP_BREAK_MODE_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_0_13 = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_0_13_LEN = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_17 = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_BANK_GROUP_1 = 15 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_RESETN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_BANK_0_1 = 17 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_BANK_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_BANK_GROUP_0 = 19 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_ACTN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_16 = 21 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_15 = 22 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_14 = 23 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_CKE = 24 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_CKE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_RESERVED_28_31 = 28 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_RESERVED_28_31_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_CSN_0_1 = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_CSN_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_CID_0_1 = 34 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_CID_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_CSN_2_3 = 36 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_CSN_2_3_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_CID_2 = 38 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_RESERVED_39_47 = 39 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_RESERVED_39_47_LEN = 9 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_ODT = 48 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_ODT_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_RESERVED_52_55 = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_RESERVED_52_55_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_CAL_TYPE = 56 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_CAL_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_PARITY = 60 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_DDR_BANK_2 = 61 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_LOOP_BREAK_MODE = 62 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_06_LOOP_BREAK_MODE_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_0_13 = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_0_13_LEN = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_17 = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_BANK_GROUP_1 = 15 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_RESETN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_BANK_0_1 = 17 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_BANK_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_BANK_GROUP_0 = 19 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_ACTN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_16 = 21 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_15 = 22 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_14 = 23 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_CKE = 24 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_CKE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_RESERVED_28_31 = 28 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_RESERVED_28_31_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_CSN_0_1 = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_CSN_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_CID_0_1 = 34 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_CID_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_CSN_2_3 = 36 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_CSN_2_3_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_CID_2 = 38 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_RESERVED_39_47 = 39 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_RESERVED_39_47_LEN = 9 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_ODT = 48 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_ODT_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_RESERVED_52_55 = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_RESERVED_52_55_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_CAL_TYPE = 56 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_CAL_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_PARITY = 60 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_DDR_BANK_2 = 61 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_LOOP_BREAK_MODE = 62 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_07_LOOP_BREAK_MODE_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_0_13 = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_0_13_LEN = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_17 = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_BANK_GROUP_1 = 15 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_RESETN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_BANK_0_1 = 17 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_BANK_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_BANK_GROUP_0 = 19 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_ACTN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_16 = 21 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_15 = 22 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_14 = 23 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_CKE = 24 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_CKE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_RESERVED_28_31 = 28 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_RESERVED_28_31_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_CSN_0_1 = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_CSN_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_CID_0_1 = 34 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_CID_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_CSN_2_3 = 36 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_CSN_2_3_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_CID_2 = 38 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_RESERVED_39_47 = 39 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_RESERVED_39_47_LEN = 9 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_ODT = 48 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_ODT_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_RESERVED_52_55 = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_RESERVED_52_55_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_CAL_TYPE = 56 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_CAL_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_PARITY = 60 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_DDR_BANK_2 = 61 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_LOOP_BREAK_MODE = 62 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_08_LOOP_BREAK_MODE_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_0_13 = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_0_13_LEN = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_17 = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_BANK_GROUP_1 = 15 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_RESETN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_BANK_0_1 = 17 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_BANK_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_BANK_GROUP_0 = 19 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_ACTN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_16 = 21 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_15 = 22 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_14 = 23 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_CKE = 24 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_CKE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_RESERVED_28_31 = 28 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_RESERVED_28_31_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_CSN_0_1 = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_CSN_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_CID_0_1 = 34 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_CID_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_CSN_2_3 = 36 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_CSN_2_3_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_CID_2 = 38 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_RESERVED_39_47 = 39 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_RESERVED_39_47_LEN = 9 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_ODT = 48 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_ODT_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_RESERVED_52_55 = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_RESERVED_52_55_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_CAL_TYPE = 56 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_CAL_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_PARITY = 60 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_DDR_BANK_2 = 61 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_LOOP_BREAK_MODE = 62 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_09_LOOP_BREAK_MODE_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_0_13 = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_0_13_LEN = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_17 = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_BANK_GROUP_1 = 15 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_RESETN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_BANK_0_1 = 17 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_BANK_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_BANK_GROUP_0 = 19 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_ACTN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_16 = 21 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_15 = 22 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_14 = 23 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_CKE = 24 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_CKE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_RESERVED_28_31 = 28 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_RESERVED_28_31_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_CSN_0_1 = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_CSN_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_CID_0_1 = 34 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_CID_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_CSN_2_3 = 36 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_CSN_2_3_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_CID_2 = 38 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_RESERVED_39_47 = 39 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_RESERVED_39_47_LEN = 9 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_ODT = 48 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_ODT_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_RESERVED_52_55 = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_RESERVED_52_55_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_CAL_TYPE = 56 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_CAL_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_PARITY = 60 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_DDR_BANK_2 = 61 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_LOOP_BREAK_MODE = 62 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_10_LOOP_BREAK_MODE_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_0_13 = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_0_13_LEN = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_17 = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_BANK_GROUP_1 = 15 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_RESETN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_BANK_0_1 = 17 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_BANK_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_BANK_GROUP_0 = 19 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_ACTN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_16 = 21 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_15 = 22 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_14 = 23 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_CKE = 24 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_CKE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_RESERVED_28_31 = 28 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_RESERVED_28_31_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_CSN_0_1 = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_CSN_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_CID_0_1 = 34 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_CID_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_CSN_2_3 = 36 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_CSN_2_3_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_CID_2 = 38 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_RESERVED_39_47 = 39 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_RESERVED_39_47_LEN = 9 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_ODT = 48 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_ODT_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_RESERVED_52_55 = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_RESERVED_52_55_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_CAL_TYPE = 56 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_CAL_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_PARITY = 60 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_DDR_BANK_2 = 61 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_LOOP_BREAK_MODE = 62 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_11_LOOP_BREAK_MODE_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_0_13 = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_0_13_LEN = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_17 = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_BANK_GROUP_1 = 15 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_RESETN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_BANK_0_1 = 17 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_BANK_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_BANK_GROUP_0 = 19 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_ACTN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_16 = 21 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_15 = 22 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_14 = 23 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_CKE = 24 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_CKE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_RESERVED_28_31 = 28 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_RESERVED_28_31_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_CSN_0_1 = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_CSN_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_CID_0_1 = 34 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_CID_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_CSN_2_3 = 36 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_CSN_2_3_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_CID_2 = 38 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_RESERVED_39_47 = 39 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_RESERVED_39_47_LEN = 9 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_ODT = 48 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_ODT_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_RESERVED_52_55 = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_RESERVED_52_55_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_CAL_TYPE = 56 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_CAL_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_PARITY = 60 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_DDR_BANK_2 = 61 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_LOOP_BREAK_MODE = 62 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_12_LOOP_BREAK_MODE_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_0 = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_0_LEN = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_17 = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_BANK_GROUP_1 = 15 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_RESETN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_BANK_0_1 = 17 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_BANK_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_BANK_GROUP_0 = 19 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_ACTN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_16 = 21 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_15 = 22 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_14 = 23 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_CKE = 24 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_CKE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_RESERVED_28_31 = 28 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_RESERVED_28_31_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_CSN_0_1 = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_CSN_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_CID_0_1 = 34 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_CID_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_CSN_2_3 = 36 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_CSN_2_3_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_CID_2 = 38 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_RESERVED_39_47 = 39 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_RESERVED_39_47_LEN = 9 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_ODT = 48 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_ODT_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_RESERVED_52_55 = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_RESERVED_52_55_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_CAL_TYPE = 56 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_CAL_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_PARITY = 60 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_DDR_BANK_2 = 61 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_LOOP_BREAK_MODE = 62 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_13_LOOP_BREAK_MODE_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS_0_13 = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS_0_13_LEN = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS_17 = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_BANK_GROUP_1 = 15 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_RESETN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_BANK_0_1 = 17 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_BANK_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_BANK_GROUP_0 = 19 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_ACTN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS_16 = 21 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS_15 = 22 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS = 23 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_CKE = 24 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_CKE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_RESERVED_28_31 = 28 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_RESERVED_28_31_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_CSN_0_1 = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_CSN_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_CID_0_1 = 34 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_CID_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_CSN_2_3 = 36 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_CSN_2_3_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_CID_2 = 38 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_RESERVED_39_47 = 39 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_RESERVED_39_47_LEN = 9 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_ODT = 48 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_ODT_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_RESERVED_52_55 = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_RESERVED_52_55_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_CAL_TYPE = 56 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_CAL_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_PARITY = 60 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_DDR_BANK_2 = 61 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_LOOP_BREAK_MODE = 62 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_14_LOOP_BREAK_MODE_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS_0_13 = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS_0_13_LEN = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS_17 = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_BANK_GROUP_1 = 15 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_RESETN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_BANK_0_1 = 17 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_BANK_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_BANK_GROUP_0 = 19 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_ACTN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS_16 = 21 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS = 22 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS_14 = 23 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_CKE = 24 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_CKE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_RESERVED_28_31 = 28 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_RESERVED_28_31_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_CSN_0_1 = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_CSN_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_CID_0_1 = 34 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_CID_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_CSN_2_3 = 36 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_CSN_2_3_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_CID_2 = 38 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_RESERVED_39_47 = 39 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_RESERVED_39_47_LEN = 9 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_ODT = 48 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_ODT_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_RESERVED_52_55 = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_RESERVED_52_55_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_CAL_TYPE = 56 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_CAL_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_PARITY = 60 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_DDR_BANK_2 = 61 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_LOOP_BREAK_MODE = 62 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_15_LOOP_BREAK_MODE_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS_0_13 = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS_0_13_LEN = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS_17 = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_BANK_GROUP_1 = 15 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_RESETN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_BANK_0_1 = 17 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_BANK_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_BANK_GROUP_0 = 19 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_ACTN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS = 21 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS_15 = 22 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS_14 = 23 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_CKE = 24 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_CKE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_RESERVED_28_31 = 28 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_RESERVED_28_31_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_CSN_0_1 = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_CSN_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_CID_0_1 = 34 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_CID_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_CSN_2_3 = 36 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_CSN_2_3_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_CID_2 = 38 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_RESERVED_39_47 = 39 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_RESERVED_39_47_LEN = 9 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_ODT = 48 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_ODT_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_RESERVED_52_55 = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_RESERVED_52_55_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_CAL_TYPE = 56 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_CAL_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_PARITY = 60 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_DDR_BANK_2 = 61 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_LOOP_BREAK_MODE = 62 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_16_LOOP_BREAK_MODE_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS_0_13 = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS_0_13_LEN = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_BANK_GROUP_1 = 15 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_RESETN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_BANK_0_1 = 17 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_BANK_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_BANK_GROUP_0 = 19 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_ACTN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS_16 = 21 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS_15 = 22 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS_14 = 23 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_CKE = 24 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_CKE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_RESERVED_28_31 = 28 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_RESERVED_28_31_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_CSN_0_1 = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_CSN_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_CID_0_1 = 34 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_CID_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_CSN_2_3 = 36 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_CSN_2_3_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_CID_2 = 38 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_RESERVED_39_47 = 39 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_RESERVED_39_47_LEN = 9 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_ODT = 48 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_ODT_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_RESERVED_52_55 = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_RESERVED_52_55_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_CAL_TYPE = 56 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_CAL_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_PARITY = 60 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_DDR_BANK_2 = 61 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_LOOP_BREAK_MODE = 62 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_17_LOOP_BREAK_MODE_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_0_13 = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_0_13_LEN = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_17 = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_BANK_GROUP_1 = 15 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_RESETN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_BANK_0_1 = 17 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_BANK_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_BANK_GROUP_0 = 19 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_ACTN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_16 = 21 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_15 = 22 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_14 = 23 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_CKE = 24 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_CKE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_RESERVED_28_31 = 28 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_RESERVED_28_31_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_CSN_0_1 = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_CSN_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_CID_0_1 = 34 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_CID_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_CSN_2_3 = 36 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_CSN_2_3_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_CID_2 = 38 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_RESERVED_39_47 = 39 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_RESERVED_39_47_LEN = 9 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_ODT = 48 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_ODT_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_RESERVED_52_55 = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_RESERVED_52_55_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_CAL_TYPE = 56 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_CAL_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_PARITY = 60 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_DDR_BANK_2 = 61 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_LOOP_BREAK_MODE = 62 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_18_LOOP_BREAK_MODE_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_0_13 = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_0_13_LEN = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_17 = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_BANK_GROUP_1 = 15 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_RESETN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_BANK_0_1 = 17 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_BANK_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_BANK_GROUP_0 = 19 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_ACTN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_16 = 21 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_15 = 22 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_14 = 23 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_CKE = 24 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_CKE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_RESERVED_28_31 = 28 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_RESERVED_28_31_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_CSN_0_1 = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_CSN_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_CID_0_1 = 34 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_CID_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_CSN_2_3 = 36 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_CSN_2_3_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_CID_2 = 38 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_RESERVED_39_47 = 39 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_RESERVED_39_47_LEN = 9 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_ODT = 48 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_ODT_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_RESERVED_52_55 = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_RESERVED_52_55_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_CAL_TYPE = 56 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_CAL_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_PARITY = 60 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_DDR_BANK_2 = 61 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_LOOP_BREAK_MODE = 62 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_19_LOOP_BREAK_MODE_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_0_13 = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_0_13_LEN = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_17 = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_BANK_GROUP_1 = 15 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_RESETN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_BANK_0_1 = 17 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_BANK_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_BANK_GROUP_0 = 19 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_ACTN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_16 = 21 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_15 = 22 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_14 = 23 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_CKE = 24 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_CKE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_RESERVED_28_31 = 28 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_RESERVED_28_31_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_CSN_0_1 = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_CSN_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_CID_0_1 = 34 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_CID_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_CSN_2_3 = 36 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_CSN_2_3_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_CID_2 = 38 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_RESERVED_39_47 = 39 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_RESERVED_39_47_LEN = 9 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_ODT = 48 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_ODT_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_RESERVED_52_55 = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_RESERVED_52_55_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_CAL_TYPE = 56 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_CAL_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_PARITY = 60 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_DDR_BANK_2 = 61 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_LOOP_BREAK_MODE = 62 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_20_LOOP_BREAK_MODE_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_0_13 = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_0_13_LEN = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_17 = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_BANK_GROUP_1 = 15 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_RESETN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_BANK_0_1 = 17 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_BANK_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_BANK_GROUP_0 = 19 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_ACTN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_16 = 21 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_15 = 22 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_14 = 23 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_CKE = 24 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_CKE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_RESERVED_28_31 = 28 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_RESERVED_28_31_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_CSN_0_1 = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_CSN_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_CID_0_1 = 34 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_CID_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_CSN_2_3 = 36 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_CSN_2_3_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_CID_2 = 38 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_RESERVED_39_47 = 39 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_RESERVED_39_47_LEN = 9 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_ODT = 48 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_ODT_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_RESERVED_52_55 = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_RESERVED_52_55_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_CAL_TYPE = 56 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_CAL_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_PARITY = 60 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_DDR_BANK_2 = 61 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_LOOP_BREAK_MODE = 62 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_21_LOOP_BREAK_MODE_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_0_13 = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_0_13_LEN = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_17 = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_BANK_GROUP_1 = 15 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_RESETN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_BANK_0_1 = 17 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_BANK_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_BANK_GROUP_0 = 19 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_ACTN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_16 = 21 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_15 = 22 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_14 = 23 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_CKE = 24 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_CKE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_RESERVED_28_31 = 28 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_RESERVED_28_31_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_CSN_0_1 = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_CSN_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_CID_0_1 = 34 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_CID_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_CSN_2_3 = 36 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_CSN_2_3_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_CID_2 = 38 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_RESERVED_39_47 = 39 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_RESERVED_39_47_LEN = 9 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_ODT = 48 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_ODT_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_RESERVED_52_55 = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_RESERVED_52_55_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_CAL_TYPE = 56 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_CAL_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_PARITY = 60 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_DDR_BANK_2 = 61 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_LOOP_BREAK_MODE = 62 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_22_LOOP_BREAK_MODE_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_0_13 = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_0_13_LEN = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_17 = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_BANK_GROUP_1 = 15 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_RESETN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_BANK_0_1 = 17 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_BANK_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_BANK_GROUP_0 = 19 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_ACTN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_16 = 21 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_15 = 22 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_14 = 23 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_CKE = 24 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_CKE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_RESERVED_28_31 = 28 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_RESERVED_28_31_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_CSN_0_1 = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_CSN_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_CID_0_1 = 34 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_CID_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_CSN_2_3 = 36 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_CSN_2_3_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_CID_2 = 38 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_RESERVED_39_47 = 39 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_RESERVED_39_47_LEN = 9 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_ODT = 48 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_ODT_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_RESERVED_52_55 = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_RESERVED_52_55_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_CAL_TYPE = 56 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_CAL_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_PARITY = 60 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_DDR_BANK_2 = 61 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_LOOP_BREAK_MODE = 62 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_23_LOOP_BREAK_MODE_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_0_13 = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_0_13_LEN = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_17 = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_BANK_GROUP_1 = 15 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_RESETN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_BANK_0_1 = 17 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_BANK_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_BANK_GROUP_0 = 19 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_ACTN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_16 = 21 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_15 = 22 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_14 = 23 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_CKE = 24 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_CKE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_RESERVED_28_31 = 28 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_RESERVED_28_31_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_CSN_0_1 = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_CSN_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_CID_0_1 = 34 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_CID_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_CSN_2_3 = 36 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_CSN_2_3_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_CID_2 = 38 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_RESERVED_39_47 = 39 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_RESERVED_39_47_LEN = 9 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_ODT = 48 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_ODT_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_RESERVED_52_55 = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_RESERVED_52_55_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_CAL_TYPE = 56 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_CAL_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_PARITY = 60 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_DDR_BANK_2 = 61 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_LOOP_BREAK_MODE = 62 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_24_LOOP_BREAK_MODE_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_0_13 = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_0_13_LEN = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_17 = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_BANK_GROUP_1 = 15 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_RESETN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_BANK_0_1 = 17 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_BANK_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_BANK_GROUP_0 = 19 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_ACTN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_16 = 21 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_15 = 22 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_14 = 23 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_CKE = 24 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_CKE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_RESERVED_28_31 = 28 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_RESERVED_28_31_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_CSN_0_1 = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_CSN_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_CID_0_1 = 34 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_CID_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_CSN_2_3 = 36 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_CSN_2_3_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_CID_2 = 38 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_RESERVED_39_47 = 39 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_RESERVED_39_47_LEN = 9 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_ODT = 48 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_ODT_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_RESERVED_52_55 = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_RESERVED_52_55_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_CAL_TYPE = 56 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_CAL_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_PARITY = 60 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_DDR_BANK_2 = 61 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_LOOP_BREAK_MODE = 62 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_25_LOOP_BREAK_MODE_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_0_13 = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_0_13_LEN = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_17 = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_BANK_GROUP_1 = 15 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_RESETN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_BANK_0_1 = 17 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_BANK_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_BANK_GROUP_0 = 19 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_ACTN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_16 = 21 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_15 = 22 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_14 = 23 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_CKE = 24 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_CKE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_RESERVED_28_31 = 28 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_RESERVED_28_31_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_CSN_0_1 = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_CSN_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_CID_0_1 = 34 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_CID_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_CSN_2_3 = 36 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_CSN_2_3_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_CID_2 = 38 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_RESERVED_39_47 = 39 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_RESERVED_39_47_LEN = 9 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_ODT = 48 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_ODT_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_RESERVED_52_55 = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_RESERVED_52_55_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_CAL_TYPE = 56 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_CAL_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_PARITY = 60 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_DDR_BANK_2 = 61 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_LOOP_BREAK_MODE = 62 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_26_LOOP_BREAK_MODE_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_0_13 = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_0_13_LEN = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_17 = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_BANK_GROUP_1 = 15 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_RESETN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_BANK_0_1 = 17 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_BANK_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_BANK_GROUP_0 = 19 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_ACTN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_16 = 21 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_15 = 22 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_14 = 23 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_CKE = 24 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_CKE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_RESERVED_28_31 = 28 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_RESERVED_28_31_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_CSN_0_1 = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_CSN_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_CID_0_1 = 34 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_CID_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_CSN_2_3 = 36 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_CSN_2_3_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_CID_2 = 38 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_RESERVED_39_47 = 39 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_RESERVED_39_47_LEN = 9 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_ODT = 48 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_ODT_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_RESERVED_52_55 = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_RESERVED_52_55_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_CAL_TYPE = 56 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_CAL_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_PARITY = 60 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_DDR_BANK_2 = 61 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_LOOP_BREAK_MODE = 62 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_27_LOOP_BREAK_MODE_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_0_13 = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_0_13_LEN = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_17 = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_BANK_GROUP_1 = 15 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_RESETN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_BANK_0_1 = 17 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_BANK_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_BANK_GROUP_0 = 19 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_ACTN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_16 = 21 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_15 = 22 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_14 = 23 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_CKE = 24 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_CKE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_RESERVED_31 = 28 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_RESERVED_31_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_CSN_0_1 = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_CSN_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_CID_0_1 = 34 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_CID_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_CSN_2_3 = 36 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_CSN_2_3_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_CID_2 = 38 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_RESERVED_39_47 = 39 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_RESERVED_39_47_LEN = 9 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_ODT = 48 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_ODT_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_RESERVED_52_55 = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_RESERVED_52_55_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_CAL_TYPE = 56 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_CAL_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_PARITY = 60 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_DDR_BANK_2 = 61 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_LOOP_BREAK_MODE = 62 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_28_LOOP_BREAK_MODE_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_0_13 = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_0_13_LEN = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_17 = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_BANK_GROUP_1 = 15 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_RESETN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_BANK_0_1 = 17 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_BANK_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_BANK_GROUP_0 = 19 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_ACTN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_16 = 21 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_15 = 22 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_14 = 23 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_CKE = 24 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_CKE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_RESERVED_28_31 = 28 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_RESERVED_28_31_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_CSN_0_1 = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_CSN_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_CID_0_1 = 34 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_CID_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_CSN_2_3 = 36 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_CSN_2_3_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_CID_2 = 38 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_RESERVED_39_47 = 39 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_RESERVED_39_47_LEN = 9 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_ODT = 48 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_ODT_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_RESERVED_52_55 = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_RESERVED_52_55_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_CAL_TYPE = 56 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_CAL_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_PARITY = 60 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_DDR_BANK_2 = 61 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_LOOP_BREAK_MODE = 62 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_29_LOOP_BREAK_MODE_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_0_13 = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_0_13_LEN = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_17 = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_BANK_GROUP_1 = 15 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_RESETN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_BANK_0_1 = 17 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_BANK_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_BANK_GROUP_0 = 19 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_ACTN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_16 = 21 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_15 = 22 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_14 = 23 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_CKE = 24 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_CKE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_RESERVED_28_31 = 28 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_RESERVED_28_31_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_CSN_0_1 = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_CSN_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_CID_0_1 = 34 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_CID_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_CSN_2_3 = 36 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_CSN_2_3_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_CID_2 = 38 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_RESERVED_39_47 = 39 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_RESERVED_39_47_LEN = 9 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_ODT = 48 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_ODT_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_RESERVED_52_55 = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_RESERVED_52_55_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_CAL_TYPE = 56 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_CAL_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_PARITY = 60 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_DDR_BANK_2 = 61 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_LOOP_BREAK_MODE = 62 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_30_LOOP_BREAK_MODE_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_0_13 = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_0_13_LEN = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_17 = 14 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_BANK_GROUP_1 = 15 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_RESETN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_BANK_0_1 = 17 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_BANK_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_BANK_GROUP_0 = 19 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_ACTN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_16 = 21 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_15 = 22 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_14 = 23 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_CKE = 24 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_CKE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_RESERVED_28 = 28 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_RESERVED_28_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_CSN_0_1 = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_CSN_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_CID_0_1 = 34 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_CID_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_CSN_2_3 = 36 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_CSN_2_3_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_CID_2 = 38 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_RESERVED_39_47 = 39 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_RESERVED_39_47_LEN = 9 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_ODT = 48 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_ODT_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_RESERVED_52_55 = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_RESERVED_52_55_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_CAL_TYPE = 56 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_CAL_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_PARITY = 60 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_DDR_BANK_2 = 61 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_LOOP_BREAK_MODE = 62 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR0_31_LOOP_BREAK_MODE_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_00_IDLES = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_00_IDLES_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_00_REPEAT_CMD_CNT = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_00_REPEAT_CMD_CNT_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_00_READ_OR_WRITE_DATA = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_00_READ_OR_WRITE_DATA_LEN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_00_READ_COMPARE_REQUIRED = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_00_DDR_CAL_RANK = 53 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_00_DDR_CAL_RANK_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_00_DDR_CALIBRATION_ENABLE = 57 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_00_END = 58 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_00_GOTO_CMD = 59 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_00_GOTO_CMD_LEN = 5 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_01_IDLES = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_01_IDLES_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_01_REPEAT_CMD_CNT = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_01_REPEAT_CMD_CNT_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_01_READ_OR_WRITE_DATA = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_01_READ_OR_WRITE_DATA_LEN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_01_READ_COMPARE_REQUIRED = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_01_DDR_CAL_RANK = 53 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_01_DDR_CAL_RANK_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_01_DDR_CALIBRATION_ENABLE = 57 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_01_END = 58 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_01_GOTO_CMD = 59 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_01_GOTO_CMD_LEN = 5 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_02_IDLES = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_02_IDLES_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_02_REPEAT_CMD_CNT = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_02_REPEAT_CMD_CNT_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_02_READ_OR_WRITE_DATA = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_02_READ_OR_WRITE_DATA_LEN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_02_READ_COMPARE_REQUIRED = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_02_DDR_CAL_RANK = 53 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_02_DDR_CAL_RANK_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_02_DDR_CALIBRATION_ENABLE = 57 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_02_END = 58 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_02_GOTO_CMD = 59 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_02_GOTO_CMD_LEN = 5 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_03_IDLES = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_03_IDLES_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_03_REPEAT_CMD_CNT = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_03_REPEAT_CMD_CNT_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_03_READ_OR_WRITE_DATA = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_03_READ_OR_WRITE_DATA_LEN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_03_READ_COMPARE_REQUIRED = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_03_DDR_CAL_RANK = 53 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_03_DDR_CAL_RANK_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_03_DDR_CALIBRATION_ENABLE = 57 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_03_END = 58 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_03_GOTO_CMD = 59 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_03_GOTO_CMD_LEN = 5 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_04_IDLES = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_04_IDLES_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_04_REPEAT_CMD_CNT = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_04_REPEAT_CMD_CNT_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_04_READ_OR_WRITE_DATA = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_04_READ_OR_WRITE_DATA_LEN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_04_READ_COMPARE_REQUIRED = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_04_DDR_CAL_RANK = 53 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_04_DDR_CAL_RANK_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_04_DDR_CALIBRATION_ENABLE = 57 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_04_END = 58 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_04_GOTO_CMD = 59 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_04_GOTO_CMD_LEN = 5 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_05_IDLES = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_05_IDLES_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_05_REPEAT_CMD_CNT = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_05_REPEAT_CMD_CNT_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_05_READ_OR_WRITE_DATA = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_05_READ_OR_WRITE_DATA_LEN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_05_READ_COMPARE_REQUIRED = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_05_DDR_CAL_RANK = 53 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_05_DDR_CAL_RANK_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_05_DDR_CALIBRATION_ENABLE = 57 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_05_END = 58 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_05_GOTO_CMD = 59 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_05_GOTO_CMD_LEN = 5 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_06_IDLES = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_06_IDLES_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_06_REPEAT_CMD_CNT = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_06_REPEAT_CMD_CNT_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_06_READ_OR_WRITE_DATA = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_06_READ_OR_WRITE_DATA_LEN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_06_READ_COMPARE_REQUIRED = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_06_DDR_CAL_RANK = 53 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_06_DDR_CAL_RANK_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_06_DDR_CALIBRATION_ENABLE = 57 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_06_END = 58 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_06_GOTO_CMD = 59 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_06_GOTO_CMD_LEN = 5 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_07_IDLES = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_07_IDLES_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_07_REPEAT_CMD_CNT = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_07_REPEAT_CMD_CNT_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_07_READ_OR_WRITE_DATA = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_07_READ_OR_WRITE_DATA_LEN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_07_READ_COMPARE_REQUIRED = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_07_DDR_CAL_RANK = 53 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_07_DDR_CAL_RANK_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_07_DDR_CALIBRATION_ENABLE = 57 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_07_END = 58 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_07_GOTO_CMD = 59 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_07_GOTO_CMD_LEN = 5 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_08_IDLES = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_08_IDLES_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_08_REPEAT_CMD_CNT = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_08_REPEAT_CMD_CNT_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_08_READ_OR_WRITE_DATA = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_08_READ_OR_WRITE_DATA_LEN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_08_READ_COMPARE_REQUIRED = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_08_DDR_CAL_RANK = 53 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_08_DDR_CAL_RANK_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_08_DDR_CALIBRATION_ENABLE = 57 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_08_END = 58 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_08_GOTO_CMD = 59 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_08_GOTO_CMD_LEN = 5 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_09_IDLES = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_09_IDLES_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_09_REPEAT_CMD_CNT = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_09_REPEAT_CMD_CNT_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_09_READ_OR_WRITE_DATA = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_09_READ_OR_WRITE_DATA_LEN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_09_READ_COMPARE_REQUIRED = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_09_DDR_CAL_RANK = 53 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_09_DDR_CAL_RANK_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_09_DDR_CALIBRATION_ENABLE = 57 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_09_END = 58 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_09_GOTO_CMD = 59 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_09_GOTO_CMD_LEN = 5 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_10_IDLES = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_10_IDLES_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_10_REPEAT_CMD_CNT = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_10_REPEAT_CMD_CNT_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_10_READ_OR_WRITE_DATA = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_10_READ_OR_WRITE_DATA_LEN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_10_READ_COMPARE_REQUIRED = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_10_DDR_CAL_RANK = 53 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_10_DDR_CAL_RANK_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_10_DDR_CALIBRATION_ENABLE = 57 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_10_END = 58 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_10_GOTO_CMD = 59 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_10_GOTO_CMD_LEN = 5 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_11_IDLES = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_11_IDLES_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_11_REPEAT_CMD_CNT = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_11_REPEAT_CMD_CNT_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_11_READ_OR_WRITE_DATA = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_11_READ_OR_WRITE_DATA_LEN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_11_READ_COMPARE_REQUIRED = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_11_DDR_CAL_RANK = 53 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_11_DDR_CAL_RANK_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_11_DDR_CALIBRATION_ENABLE = 57 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_11_END = 58 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_11_GOTO_CMD = 59 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_11_GOTO_CMD_LEN = 5 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_12_IDLES = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_12_IDLES_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_12_REPEAT_CMD_CNT = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_12_REPEAT_CMD_CNT_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_12_READ_OR_WRITE_DATA = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_12_READ_OR_WRITE_DATA_LEN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_12_READ_COMPARE_REQUIRED = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_12_DDR_CAL_RANK = 53 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_12_DDR_CAL_RANK_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_12_DDR_CALIBRATION_ENABLE = 57 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_12_END = 58 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_12_GOTO_CMD = 59 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_12_GOTO_CMD_LEN = 5 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_13_IDLES = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_13_IDLES_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_13_REPEAT_CMD_CNT = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_13_REPEAT_CMD_CNT_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_13_READ_OR_WRITE_DATA = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_13_READ_OR_WRITE_DATA_LEN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_13_READ_COMPARE_REQUIRED = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_13_DDR_CAL_RANK = 53 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_13_DDR_CAL_RANK_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_13_DDR_CALIBRATION_ENABLE = 57 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_13_END = 58 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_13_GOTO_CMD = 59 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_13_GOTO_CMD_LEN = 5 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_14_IDLES = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_14_IDLES_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_14_REPEAT_CMD_CNT = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_14_REPEAT_CMD_CNT_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_14_READ_OR_WRITE_DATA = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_14_READ_OR_WRITE_DATA_LEN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_14_READ_COMPARE_REQUIRED = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_14_DDR_CAL_RANK = 53 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_14_DDR_CAL_RANK_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_14_DDR_CALIBRATION_ENABLE = 57 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_14_END = 58 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_14_GOTO_CMD = 59 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_14_GOTO_CMD_LEN = 5 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_15_IDLES = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_15_IDLES_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_15_REPEAT_CMD_CNT = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_15_REPEAT_CMD_CNT_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_15_READ_OR_WRITE_DATA = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_15_READ_OR_WRITE_DATA_LEN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_15_READ_COMPARE_REQUIRED = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_15_DDR_CAL_RANK = 53 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_15_DDR_CAL_RANK_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_15_DDR_CALIBRATION_ENABLE = 57 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_15_END = 58 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_15_GOTO_CMD = 59 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_15_GOTO_CMD_LEN = 5 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_16_IDLES = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_16_IDLES_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_16_REPEAT_CMD_CNT = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_16_REPEAT_CMD_CNT_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_16_READ_OR_WRITE_DATA = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_16_READ_OR_WRITE_DATA_LEN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_16_READ_COMPARE_REQUIRED = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_16_DDR_CAL_RANK = 53 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_16_DDR_CAL_RANK_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_16_DDR_CALIBRATION_ENABLE = 57 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_16_END = 58 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_16_GOTO_CMD = 59 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_16_GOTO_CMD_LEN = 5 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_17_IDLES = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_17_IDLES_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_17_REPEAT_CMD_CNT = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_17_REPEAT_CMD_CNT_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_17_READ_OR_WRITE_DATA = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_17_READ_OR_WRITE_DATA_LEN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_17_READ_COMPARE_REQUIRED = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_17_DDR_CAL_RANK = 53 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_17_DDR_CAL_RANK_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_17_DDR_CALIBRATION_ENABLE = 57 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_17_END = 58 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_17_GOTO_CMD = 59 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_17_GOTO_CMD_LEN = 5 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_18_IDLES = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_18_IDLES_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_18_REPEAT_CMD_CNT = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_18_REPEAT_CMD_CNT_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_18_READ_OR_WRITE_DATA = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_18_READ_OR_WRITE_DATA_LEN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_18_READ_COMPARE_REQUIRED = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_18_DDR_CAL_RANK = 53 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_18_DDR_CAL_RANK_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_18_DDR_CALIBRATION_ENABLE = 57 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_18_END = 58 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_18_GOTO_CMD = 59 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_18_GOTO_CMD_LEN = 5 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_19_IDLES = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_19_IDLES_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_19_REPEAT_CMD_CNT = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_19_REPEAT_CMD_CNT_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_19_READ_OR_WRITE_DATA = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_19_READ_OR_WRITE_DATA_LEN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_19_READ_COMPARE_REQUIRED = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_19_DDR_CAL_RANK = 53 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_19_DDR_CAL_RANK_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_19_DDR_CALIBRATION_ENABLE = 57 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_19_END = 58 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_19_GOTO_CMD = 59 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_19_GOTO_CMD_LEN = 5 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_20_IDLES = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_20_IDLES_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_20_REPEAT_CMD_CNT = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_20_REPEAT_CMD_CNT_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_20_READ_OR_WRITE_DATA = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_20_READ_OR_WRITE_DATA_LEN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_20_READ_COMPARE_REQUIRED = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_20_DDR_CAL_RANK = 53 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_20_DDR_CAL_RANK_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_20_DDR_CALIBRATION_ENABLE = 57 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_20_END = 58 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_20_GOTO_CMD = 59 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_20_GOTO_CMD_LEN = 5 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_21_IDLES = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_21_IDLES_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_21_REPEAT_CMD_CNT = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_21_REPEAT_CMD_CNT_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_21_READ_OR_WRITE_DATA = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_21_READ_OR_WRITE_DATA_LEN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_21_READ_COMPARE_REQUIRED = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_21_DDR_CAL_RANK = 53 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_21_DDR_CAL_RANK_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_21_DDR_CALIBRATION_ENABLE = 57 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_21_END = 58 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_21_GOTO_CMD = 59 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_21_GOTO_CMD_LEN = 5 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_22_IDLES = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_22_IDLES_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_22_REPEAT_CMD_CNT = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_22_REPEAT_CMD_CNT_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_22_READ_OR_WRITE_DATA = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_22_READ_OR_WRITE_DATA_LEN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_22_READ_COMPARE_REQUIRED = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_22_DDR_CAL_RANK = 53 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_22_DDR_CAL_RANK_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_22_DDR_CALIBRATION_ENABLE = 57 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_22_END = 58 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_22_GOTO_CMD = 59 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_22_GOTO_CMD_LEN = 5 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_23_IDLES = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_23_IDLES_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_23_REPEAT_CMD_CNT = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_23_REPEAT_CMD_CNT_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_23_READ_OR_WRITE_DATA = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_23_READ_OR_WRITE_DATA_LEN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_23_READ_COMPARE_REQUIRED = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_23_DDR_CAL_RANK = 53 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_23_DDR_CAL_RANK_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_23_DDR_CALIBRATION_ENABLE = 57 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_23_END = 58 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_23_GOTO_CMD = 59 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_23_GOTO_CMD_LEN = 5 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_24_IDLES = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_24_IDLES_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_24_REPEAT_CMD_CNT = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_24_REPEAT_CMD_CNT_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_24_READ_OR_WRITE_DATA = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_24_READ_OR_WRITE_DATA_LEN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_24_READ_COMPARE_REQUIRED = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_24_DDR_CAL_RANK = 53 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_24_DDR_CAL_RANK_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_24_DDR_CALIBRATION_ENABLE = 57 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_24_END = 58 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_24_GOTO_CMD = 59 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_24_GOTO_CMD_LEN = 5 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_25_IDLES = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_25_IDLES_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_25_REPEAT_CMD_CNT = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_25_REPEAT_CMD_CNT_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_25_READ_OR_WRITE_DATA = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_25_READ_OR_WRITE_DATA_LEN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_25_READ_COMPARE_REQUIRED = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_25_DDR_CAL_RANK = 53 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_25_DDR_CAL_RANK_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_25_DDR_CALIBRATION_ENABLE = 57 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_25_END = 58 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_25_GOTO_CMD = 59 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_25_GOTO_CMD_LEN = 5 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_26_IDLES = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_26_IDLES_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_26_REPEAT_CMD_CNT = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_26_REPEAT_CMD_CNT_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_26_READ_OR_WRITE_DATA = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_26_READ_OR_WRITE_DATA_LEN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_26_READ_COMPARE_REQUIRED = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_26_DDR_CAL_RANK = 53 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_26_DDR_CAL_RANK_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_26_DDR_CALIBRATION_ENABLE = 57 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_26_END = 58 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_26_GOTO_CMD = 59 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_26_GOTO_CMD_LEN = 5 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_27_IDLES = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_27_IDLES_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_27_REPEAT_CMD_CNT = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_27_REPEAT_CMD_CNT_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_27_READ_OR_WRITE_DATA = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_27_READ_OR_WRITE_DATA_LEN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_27_READ_COMPARE_REQUIRED = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_27_DDR_CAL_RANK = 53 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_27_DDR_CAL_RANK_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_27_DDR_CALIBRATION_ENABLE = 57 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_27_END = 58 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_27_GOTO_CMD = 59 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_27_GOTO_CMD_LEN = 5 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_28_IDLES = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_28_IDLES_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_28_REPEAT_CMD_CNT = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_28_REPEAT_CMD_CNT_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_28_READ_OR_WRITE_DATA = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_28_READ_OR_WRITE_DATA_LEN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_28_READ_COMPARE_REQUIRED = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_28_DDR_CAL_RANK = 53 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_28_DDR_CAL_RANK_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_28_DDR_CALIBRATION_ENABLE = 57 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_28_END = 58 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_28_GOTO_CMD = 59 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_28_GOTO_CMD_LEN = 5 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_29_IDLES = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_29_IDLES_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_29_REPEAT_CMD_CNT = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_29_REPEAT_CMD_CNT_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_29_READ_OR_WRITE_DATA = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_29_READ_OR_WRITE_DATA_LEN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_29_READ_COMPARE_REQUIRED = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_29_DDR_CAL_RANK = 53 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_29_DDR_CAL_RANK_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_29_DDR_CALIBRATION_ENABLE = 57 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_29_END = 58 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_29_GOTO_CMD = 59 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_29_GOTO_CMD_LEN = 5 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_30_IDLES = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_30_IDLES_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_30_REPEAT_CMD_CNT = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_30_REPEAT_CMD_CNT_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_30_READ_OR_WRITE_DATA = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_30_READ_OR_WRITE_DATA_LEN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_30_READ_COMPARE_REQUIRED = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_30_DDR_CAL_RANK = 53 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_30_DDR_CAL_RANK_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_30_DDR_CALIBRATION_ENABLE = 57 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_30_END = 58 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_30_GOTO_CMD = 59 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_30_GOTO_CMD_LEN = 5 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_31_IDLES = 0 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_31_IDLES_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_31_REPEAT_CMD_CNT = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_31_REPEAT_CMD_CNT_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_31_READ_OR_WRITE_DATA = 32 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_31_READ_OR_WRITE_DATA_LEN = 20 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_31_READ_COMPARE_REQUIRED = 52 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_31_DDR_CAL_RANK = 53 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_31_DDR_CAL_RANK_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_31_DDR_CALIBRATION_ENABLE = 57 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_31_END = 58 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_31_GOTO_CMD = 59 ; static const uint8_t P9N2_MCBIST_CCS_INST_ARR1_31_GOTO_CMD_LEN = 5 ; static const uint8_t P9N2_MCBIST_CCS_MODEQ_STOP_ON_ERR = 0 ; static const uint8_t P9N2_MCBIST_CCS_MODEQ_UE_DISABLE = 1 ; static const uint8_t P9N2_MCBIST_CCS_MODEQ_DATA_COMPARE_BURST_SEL = 2 ; static const uint8_t P9N2_MCBIST_CCS_MODEQ_DATA_COMPARE_BURST_SEL_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_MODEQ_RESERVED_4_7 = 4 ; static const uint8_t P9N2_MCBIST_CCS_MODEQ_RESERVED_4_7_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT = 8 ; static const uint8_t P9N2_MCBIST_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT_LEN = 16 ; static const uint8_t P9N2_MCBIST_CCS_MODEQ_CFG_PARITY_AFTER_CMD = 24 ; static const uint8_t P9N2_MCBIST_CCS_MODEQ_RESERVED_25 = 25 ; static const uint8_t P9N2_MCBIST_CCS_MODEQ_COPY_CKE_TO_SPARE_CKE = 26 ; static const uint8_t P9N2_MCBIST_CCS_MODEQ_DISABLE_ECC_ARRAY_CHK = 27 ; static const uint8_t P9N2_MCBIST_CCS_MODEQ_DISABLE_ECC_ARRAY_CORRECTION = 28 ; static const uint8_t P9N2_MCBIST_CCS_MODEQ_CFG_DGEN_FIXED_MODE = 29 ; static const uint8_t P9N2_MCBIST_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT_MULT = 30 ; static const uint8_t P9N2_MCBIST_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT_MULT_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_0_13 = 32 ; static const uint8_t P9N2_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_0_13_LEN = 14 ; static const uint8_t P9N2_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_17 = 46 ; static const uint8_t P9N2_MCBIST_CCS_MODEQ_IDLE_PAT_BANK_GROUP_1 = 47 ; static const uint8_t P9N2_MCBIST_CCS_MODEQ_IDLE_PAT_BANK_0_1 = 48 ; static const uint8_t P9N2_MCBIST_CCS_MODEQ_IDLE_PAT_BANK_0_1_LEN = 2 ; static const uint8_t P9N2_MCBIST_CCS_MODEQ_IDLE_PAT_BANK_GROUP_0 = 50 ; static const uint8_t P9N2_MCBIST_CCS_MODEQ_IDLE_PAT_ACTN = 51 ; static const uint8_t P9N2_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_16 = 52 ; static const uint8_t P9N2_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_15 = 53 ; static const uint8_t P9N2_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_14 = 54 ; static const uint8_t P9N2_MCBIST_CCS_MODEQ_NTTM_MODE = 55 ; static const uint8_t P9N2_MCBIST_CCS_MODEQ_NTTM_RW_DATA_DLY = 56 ; static const uint8_t P9N2_MCBIST_CCS_MODEQ_NTTM_RW_DATA_DLY_LEN = 4 ; static const uint8_t P9N2_MCBIST_CCS_MODEQ_IDLE_PAT_BANK_2 = 60 ; static const uint8_t P9N2_MCBIST_CCS_MODEQ_DDR_PARITY_ENABLE = 61 ; static const uint8_t P9N2_MCBIST_CCS_MODEQ_IDLE_PAT_PARITY = 62 ; static const uint8_t P9N2_MCBIST_CCS_MODEQ_RESERVED_63 = 63 ; static const uint8_t P9N2_MCBIST_CCS_STATQ_IP = 0 ; static const uint8_t P9N2_MCBIST_CCS_STATQ_DONE = 1 ; static const uint8_t P9N2_MCBIST_CCS_STATQ_FAIL = 2 ; static const uint8_t P9N2_MCBIST_CCS_STATQ_FAIL_TYPE = 3 ; static const uint8_t P9N2_MCBIST_CCS_STATQ_FAIL_TYPE_LEN = 3 ; static const uint8_t P9N2_MCBIST_CCS_STATQ_MCBIST_SUBTEST_IP = 6 ; static const uint8_t P9N2_MCBIST_CCS_STATQ_FAIL_RCD = 7 ; static const uint8_t P9N2_MCA_CERR0_RECR_PE = 10 ; static const uint8_t P9N2_MCA_CERR0_DBGR_PE = 11 ; static const uint8_t P9N2_MCA_CERR0_MSR_PE = 12 ; static const uint8_t P9N2_MCA_CERR0_EICR_PE = 13 ; static const uint8_t P9N2_MCA_CERR0_HWMSX_PE = 16 ; static const uint8_t P9N2_MCA_CERR0_HWMSX_PE_LEN = 8 ; static const uint8_t P9N2_MCA_CERR0_FWMSX_PE = 24 ; static const uint8_t P9N2_MCA_CERR0_FWMSX_PE_LEN = 8 ; static const uint8_t P9N2_MCA_CERR0_WECR_PE = 40 ; static const uint8_t P9N2_MCA_CERR0_AACR_PE = 41 ; static const uint8_t P9N2_MCA_CERR0_AADR_PE = 42 ; static const uint8_t P9N2_MCA_CERR0_AAER_PE = 43 ; static const uint8_t P9N2_MCA_CERR0_MCBCM_PE = 44 ; static const uint8_t P9N2_MCA_CERR0_MBMDI_PE = 45 ; static const uint8_t P9N2_MCA_CERR0_WDFCFG_PE = 48 ; static const uint8_t P9N2_MCA_CERR0_WRTCFG_PE = 56 ; static const uint8_t P9N2_MCA_CERR0_DQS0R_PE = 60 ; static const uint8_t P9N2_MCA_CERR0_DQS1R_PE = 61 ; static const uint8_t P9N2_MCA_CERR1_ECC_CTL_AF_PERR = 0 ; static const uint8_t P9N2_MCA_CERR1_ECC_CTL_RPTR_PERR = 1 ; static const uint8_t P9N2_MCA_CERR1_ECC_CTL_TCHN_PERR = 2 ; static const uint8_t P9N2_MCA_CERR1_ECC_CTL_CMPMODE_ERR = 3 ; static const uint8_t P9N2_MCA_CERR1_ECC_CTL_SCHCTL_PERR = 4 ; static const uint8_t P9N2_MCA_CERR1_ECC_CTL_PCTL_PERR = 5 ; static const uint8_t P9N2_MCA_CERR1_ECC_CTL_TGST_PERR = 6 ; static const uint8_t P9N2_MCA_CERR1_ECC_CTL_SCHTAB_PERR = 7 ; static const uint8_t P9N2_MCA_CERR1_ECC_PIPE_PCX_PERR = 8 ; static const uint8_t P9N2_MCA_CERR1_ECC_PIPE_SYND_PERR = 9 ; static const uint8_t P9N2_MCA_CERR1_ECC_PIPE_2SYM_PERR = 10 ; static const uint8_t P9N2_MCA_CERR1_ECC_PIPE_CPLX_PERR = 11 ; static const uint8_t P9N2_MCA_CERR1_ECC_PIPE_EP2_PERR = 12 ; static const uint8_t P9N2_MCA_CERR1_READ_ECC_DATAPATH_PARITY_ERROR = 13 ; static const uint8_t P9N2_MCA_CERR1_PHY_RPTR_PARITY_ERROR = 14 ; static const uint8_t P9N2_MCA_CERR1_ECC_CTL_RPD_PERR = 15 ; static const uint8_t P9N2_MCA_CERR1_WDF_ASYNC_ERROR = 16 ; static const uint8_t P9N2_MCA_CERR1_WDF_BUFFER_CE = 17 ; static const uint8_t P9N2_MCA_CERR1_WDF_BUFFER_UE = 18 ; static const uint8_t P9N2_MCA_CERR1_WDF_BUFFER_SUE = 19 ; static const uint8_t P9N2_MCA_CERR1_WRT_BUFFER_CE = 25 ; static const uint8_t P9N2_MCA_CERR1_WRT_BUFFER_UE = 26 ; static const uint8_t P9N2_MCA_CERR1_WRT_BUFFER_SUE = 27 ; static const uint8_t P9N2_MCA_CERR1_READ_CONTROL_OVERFLOW_ERROR = 32 ; static const uint8_t P9N2_MCA_CERR1_WRITE_ECC_DATAPATH_ERROR = 40 ; static const uint8_t P9N2_MCBIST_CLKRATIO_RATIO = 0 ; static const uint8_t P9N2_MCBIST_CLKRATIO_RATIO_LEN = 12 ; static const uint8_t P9N2_MCBIST_CLKRATIO_CFG0_SYNC_MODE = 12 ; static const uint8_t P9N2_MCBIST_CLKRATIO_CFG1_SYNC_MODE = 13 ; static const uint8_t P9N2_MCBIST_DBGCFG0Q_CFG_DBG_ENABLE = 0 ; static const uint8_t P9N2_MCBIST_DBGCFG0Q_CFG_DBG_PICK_ASYNC_PORT01 = 1 ; static const uint8_t P9N2_MCBIST_DBGCFG0Q_CFG_DBG_PICK_ASYNC_PORT01_LEN = 11 ; static const uint8_t P9N2_MCBIST_DBGCFG0Q_CFG_DBG_PICK_ASYNC_PORT23 = 12 ; static const uint8_t P9N2_MCBIST_DBGCFG0Q_CFG_DBG_PICK_ASYNC_PORT23_LEN = 11 ; static const uint8_t P9N2_MCBIST_DBGCFG0Q_CFG_DBG_PICK_MCBIST01 = 23 ; static const uint8_t P9N2_MCBIST_DBGCFG0Q_CFG_DBG_PICK_MCBIST01_LEN = 11 ; static const uint8_t P9N2_MCBIST_DBGCFG0Q_CFG_DBG_PICK_MCBIST23 = 34 ; static const uint8_t P9N2_MCBIST_DBGCFG0Q_CFG_DBG_PICK_MCBIST23_LEN = 11 ; static const uint8_t P9N2_MCBIST_DBGCFG0Q_SCOM_SET_WAT_EXT_TRIGGER = 45 ; static const uint8_t P9N2_MCBIST_DBGCFG0Q_SCOM_SET_WAT_EXT_RESET = 46 ; static const uint8_t P9N2_MCBIST_DBGCFG0Q_SCOM_SET_WAT_EXT_ARM = 47 ; static const uint8_t P9N2_MCBIST_DBGCFG1Q_CFG_WAT_ENABLE = 0 ; static const uint8_t P9N2_MCBIST_DBGCFG1Q_CFG_WAT_EXT_EVENT_TO_INT = 1 ; static const uint8_t P9N2_MCBIST_DBGCFG1Q_CFG_WAT_EXT_EVENT_TO_INT_LEN = 2 ; static const uint8_t P9N2_MCBIST_DBGCFG1Q_CFG_WAT_EXT_TRIGGER_SEL = 3 ; static const uint8_t P9N2_MCBIST_DBGCFG1Q_CFG_WAT_EXT_TRIGGER_SEL_LEN = 20 ; static const uint8_t P9N2_MCBIST_DBGCFG1Q_CFG_WAT_EXT_RESET_SEL = 23 ; static const uint8_t P9N2_MCBIST_DBGCFG1Q_CFG_WAT_EXT_RESET_SEL_LEN = 20 ; static const uint8_t P9N2_MCBIST_DBGCFG1Q_CFG_WAT_EXT_ARM_SEL = 43 ; static const uint8_t P9N2_MCBIST_DBGCFG1Q_CFG_WAT_EXT_ARM_SEL_LEN = 20 ; static const uint8_t P9N2_MCBIST_DBGCFG1Q_RESERVED_63 = 63 ; static const uint8_t P9N2_MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT0_SEL = 0 ; static const uint8_t P9N2_MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT0_SEL_LEN = 20 ; static const uint8_t P9N2_MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT1_SEL = 20 ; static const uint8_t P9N2_MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT1_SEL_LEN = 20 ; static const uint8_t P9N2_MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT2_SEL = 40 ; static const uint8_t P9N2_MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT2_SEL_LEN = 20 ; static const uint8_t P9N2_MCBIST_DBGCFG2Q_RESERVED_60_63 = 60 ; static const uint8_t P9N2_MCBIST_DBGCFG2Q_RESERVED_60_63_LEN = 4 ; static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_LOC_EVENT3_SEL = 0 ; static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_LOC_EVENT3_SEL_LEN = 20 ; static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT0_SEL = 20 ; static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT0_SEL_LEN = 3 ; static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT1_SEL = 23 ; static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT1_SEL_LEN = 3 ; static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT2_SEL = 26 ; static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT2_SEL_LEN = 3 ; static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT3_SEL = 29 ; static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT3_SEL_LEN = 3 ; static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_OUTPUT_PULSE = 32 ; static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_ACT_MNT_GO_IDLE_PULSE = 33 ; static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_ACT_MNT_GO_IDLE_PULSE_LEN = 4 ; static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_ACT_SET_SPATTN_PULSE = 37 ; static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_ACT_SET_SPATTN_PULSE_LEN = 4 ; static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_ACT_FRC_TB_PULSE_PULSE = 41 ; static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_ACT_FRC_TB_PULSE_PULSE_LEN = 4 ; static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_CNT_VALUE = 45 ; static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_CNT_VALUE_LEN = 6 ; static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_TMR_VALUE = 51 ; static const uint8_t P9N2_MCBIST_DBGCFG3Q_CFG_WAT_TMR_VALUE_LEN = 8 ; static const uint8_t P9N2_MCA_DBGR_ECC_DEBUG_ENABLE = 0 ; static const uint8_t P9N2_MCA_DBGR_ECC_DEBUG_CHUNK_SELECT = 1 ; static const uint8_t P9N2_MCA_DBGR_ECC_DEBUG_CHUNK_SELECT_LEN = 2 ; static const uint8_t P9N2_MCA_DBGR_ECC_DEBUG_PRIMARY_SELECT = 3 ; static const uint8_t P9N2_MCA_DBGR_ECC_DEBUG_PRIMARY_SELECT_LEN = 3 ; static const uint8_t P9N2_MCA_DBGR_ECC_DEBUG_SECONDARY_SELECT = 6 ; static const uint8_t P9N2_MCA_DBGR_ECC_DEBUG_SECONDARY_SELECT_LEN = 2 ; static const uint8_t P9N2_MCA_DBGR_ECC_WAT_ENABLE = 8 ; static const uint8_t P9N2_MCA_DBGR_ECC_WAT_ACTION_SELECT = 9 ; static const uint8_t P9N2_MCA_DBGR_ECC_WAT_SOURCE = 10 ; static const uint8_t P9N2_MCA_DBGR_ECC_WAT_SOURCE_LEN = 2 ; static const uint8_t P9N2_MCA_DBGR_READ_DEBUG_SELECT = 12 ; static const uint8_t P9N2_MCA_DBGR_READ_DEBUG_SELECT_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR0_01_0_11 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR0_01_0_11_LEN = 12 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR1_01_0_11 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR1_01_0_11_LEN = 12 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR2_23_0_11 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR2_23_0_11_LEN = 12 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR3_23_0_11 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR3_23_0_11_LEN = 12 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_ADJUST = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_ADJUST_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_CORRECT_EN = 56 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_ITER_A = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_CAL_ENABLE = 58 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_POWERDOWN = 60 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_CAL_DONE = 61 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_CAL_ERROR = 62 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_COMPARE_OUT = 63 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1_ADR1_DLL_ADJUST = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1_ADR1_DLL_ADJUST_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1_ADR1_DLL_CORRECT_EN = 56 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1_ADR1_DLL_ITER_A = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1_ADR1_DLL_CAL_ENABLE = 58 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1_ADR1_DLL_POWERDOWN = 60 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1_ADR1_DLL_CAL_DONE = 61 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1_ADR1_DLL_CAL_ERROR = 62 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1_ADR1_DLL_COMPARE_OUT = 63 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY0_P0_ADR0_01 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY0_P0_ADR0_01_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY0_P0_ADR0_01_DELAY1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY0_P0_ADR0_01_DELAY1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY0_P0_ADR1_01 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY0_P0_ADR1_01_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY0_P0_ADR1_01_DELAY1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY0_P0_ADR1_01_DELAY1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY0_P0_ADR2_23 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY0_P0_ADR2_23_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY0_P0_ADR2_23_DELAY1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY0_P0_ADR2_23_DELAY1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY0_P0_ADR3_23 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY0_P0_ADR3_23_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY0_P0_ADR3_23_DELAY1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY0_P0_ADR3_23_DELAY1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY1_P0_ADR0_01_DELAY2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY1_P0_ADR0_01_DELAY2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY1_P0_ADR0_01_DELAY3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY1_P0_ADR0_01_DELAY3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY1_P0_ADR1_01_DELAY2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY1_P0_ADR1_01_DELAY2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY1_P0_ADR1_01_DELAY3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY1_P0_ADR1_01_DELAY3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY1_P0_ADR2_23_DELAY2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY1_P0_ADR2_23_DELAY2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY1_P0_ADR2_23_DELAY3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY1_P0_ADR2_23_DELAY3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY1_P0_ADR3_23_DELAY2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY1_P0_ADR3_23_DELAY2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY1_P0_ADR3_23_DELAY3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY1_P0_ADR3_23_DELAY3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY2_P0_ADR0_01_DELAY4 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY2_P0_ADR0_01_DELAY4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY2_P0_ADR0_01_DELAY5 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY2_P0_ADR0_01_DELAY5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY2_P0_ADR1_01_DELAY4 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY2_P0_ADR1_01_DELAY4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY2_P0_ADR1_01_DELAY5 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY2_P0_ADR1_01_DELAY5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY2_P0_ADR2_23_DELAY4 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY2_P0_ADR2_23_DELAY4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY2_P0_ADR2_23_DELAY5 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY2_P0_ADR2_23_DELAY5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY2_P0_ADR3_23_DELAY4 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY2_P0_ADR3_23_DELAY4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY2_P0_ADR3_23_DELAY5 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY2_P0_ADR3_23_DELAY5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY3_P0_ADR0_01_DELAY6 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY3_P0_ADR0_01_DELAY6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY3_P0_ADR0_01_DELAY7 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY3_P0_ADR0_01_DELAY7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY3_P0_ADR1_01_DELAY6 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY3_P0_ADR1_01_DELAY6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY3_P0_ADR1_01_DELAY7 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY3_P0_ADR1_01_DELAY7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY3_P0_ADR2_23_DELAY6 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY3_P0_ADR2_23_DELAY6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY3_P0_ADR2_23_DELAY7 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY3_P0_ADR2_23_DELAY7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY3_P0_ADR3_23_DELAY6 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY3_P0_ADR3_23_DELAY6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY3_P0_ADR3_23_DELAY7 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY3_P0_ADR3_23_DELAY7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY4_P0_ADR0_01_DELAY8 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY4_P0_ADR0_01_DELAY8_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY4_P0_ADR0_01_DELAY9 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY4_P0_ADR0_01_DELAY9_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY4_P0_ADR1_01_DELAY8 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY4_P0_ADR1_01_DELAY8_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY4_P0_ADR1_01_DELAY9 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY4_P0_ADR1_01_DELAY9_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY4_P0_ADR2_23_DELAY8 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY4_P0_ADR2_23_DELAY8_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY4_P0_ADR2_23_DELAY9 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY4_P0_ADR2_23_DELAY9_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY4_P0_ADR3_23_DELAY8 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY4_P0_ADR3_23_DELAY8_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY4_P0_ADR3_23_DELAY9 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY4_P0_ADR3_23_DELAY9_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY5_P0_ADR0_01_DELAY10 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY5_P0_ADR0_01_DELAY10_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY5_P0_ADR0_01_DELAY11 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY5_P0_ADR0_01_DELAY11_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY5_P0_ADR1_01_DELAY10 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY5_P0_ADR1_01_DELAY10_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY5_P0_ADR1_01_DELAY11 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY5_P0_ADR1_01_DELAY11_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY5_P0_ADR2_23_DELAY10 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY5_P0_ADR2_23_DELAY10_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY5_P0_ADR2_23_DELAY11 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY5_P0_ADR2_23_DELAY11_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY5_P0_ADR3_23_DELAY10 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY5_P0_ADR3_23_DELAY10_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY5_P0_ADR3_23_DELAY11 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY5_P0_ADR3_23_DELAY11_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY6_P0_ADR0_01_DELAY12 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY6_P0_ADR0_01_DELAY12_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY6_P0_ADR0_01_DELAY13 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY6_P0_ADR0_01_DELAY13_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY6_P0_ADR1_01_DELAY12 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY6_P0_ADR1_01_DELAY12_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY6_P0_ADR1_01_DELAY13 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY6_P0_ADR1_01_DELAY13_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY6_P0_ADR2_23_DELAY12 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY6_P0_ADR2_23_DELAY12_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY6_P0_ADR2_23_DELAY13 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY6_P0_ADR2_23_DELAY13_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY6_P0_ADR3_23_DELAY12 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY6_P0_ADR3_23_DELAY12_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY6_P0_ADR3_23_DELAY13 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY6_P0_ADR3_23_DELAY13_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY7_P0_ADR0_01_DELAY14 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY7_P0_ADR0_01_DELAY14_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY7_P0_ADR0_01_DELAY15 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY7_P0_ADR0_01_DELAY15_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY7_P0_ADR1_01_DELAY14 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY7_P0_ADR1_01_DELAY14_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY7_P0_ADR1_01_DELAY15 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY7_P0_ADR1_01_DELAY15_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY7_P0_ADR2_23_DELAY14 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY7_P0_ADR2_23_DELAY14_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY7_P0_ADR2_23_DELAY15 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY7_P0_ADR2_23_DELAY15_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY7_P0_ADR3_23_DELAY14 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY7_P0_ADR3_23_DELAY14_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY7_P0_ADR3_23_DELAY15 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DELAY7_P0_ADR3_23_DELAY15_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_LANE_PAIR_FAIL = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_LANE_PAIR_FAIL_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_RESERVED_54_55 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_RESERVED_54_55_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_DATA_EN = 56 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_MODE = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_MODE_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_4TO1_MODE = 59 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_RESET = 60 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_GEN_EN = 61 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_CLEAR_ERROR = 62 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_CHECK_EN = 63 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_LANE_PAIR_FAIL = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_LANE_PAIR_FAIL_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_RESERVED_54_55 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_RESERVED_54_55_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_DATA_EN = 56 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_MODE = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_MODE_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_4TO1_MODE = 59 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_RESET = 60 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_GEN_EN = 61 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_CLEAR_ERROR = 62 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_CHECK_EN = 63 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_LANE_PAIR_FAIL = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_LANE_PAIR_FAIL_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_RESERVED_54_55 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_RESERVED_54_55_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_DATA_EN = 56 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_MODE = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_MODE_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_4TO1_MODE = 59 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_RESET = 60 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_GEN_EN = 61 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_CLEAR_ERROR = 62 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_CHECK_EN = 63 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_LANE_PAIR_FAIL = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_LANE_PAIR_FAIL_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_RESERVED_54_55 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_RESERVED_54_55_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_DATA_EN = 56 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_MODE = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_MODE_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_4TO1_MODE = 59 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_RESET = 60 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_GEN_EN = 61 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_CLEAR_ERROR = 62 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_CHECK_EN = 63 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0_01_DI_ADR1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0_01_DI_ADR2_ADR3 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0_01_DI_ADR4_ADR5 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0_01_DI_ADR6_ADR7 = 51 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0_01_DI_ADR8_ADR9 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0_01_DI_ADR10_ADR11 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1_01_DI_ADR0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1_01_DI_ADR2_ADR3 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1_01_DI_ADR4_ADR5 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1_01_DI_ADR6_ADR7 = 51 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1_01_DI_ADR8_ADR9 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1_01_DI_ADR10_ADR11 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2_23_DI_ADR0_ADR1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2_23_DI_ADR3 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2_23_DI_ADR4_ADR5 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2_23_DI_ADR6_ADR7 = 51 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2_23_DI_ADR8_ADR9 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2_23_DI_ADR10_ADR11 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3_23_DI_ADR0_ADR1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3_23_DI_ADR2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3_23_DI_ADR4_ADR5 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3_23_DI_ADR6_ADR7 = 51 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3_23_DI_ADR8_ADR9 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3_23_DI_ADR10_ADR11 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_INIT_RXDLL_CAL_RESET = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_INIT_RXDLL_CAL_UPDATE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_REGS_RXDLL_CAL_SKIP = 50 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_REGS_RXDLL_CAL_SKIP_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_REGS_RXDLL_COARSE_ADJ_BY2 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_RXREG_FILTER_LENGTH_DC = 53 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_RXREG_FILTER_LENGTH_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_RXREG_LEAD_LAG_SEPARATION_DC = 56 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_EN_DRIVER_INVFB_DC = 59 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_CAL_GOOD = 61 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_CAL_ERROR = 62 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_CAL_ERROR_FINE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_INIT_RXDLL_CAL_RESET = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_INIT_RXDLL_CAL_UPDATE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_REGS_RXDLL_CAL_SKIP = 50 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_REGS_RXDLL_CAL_SKIP_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_REGS_RXDLL_COARSE_ADJ_BY2 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_RXREG_FILTER_LENGTH_DC = 53 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_RXREG_FILTER_LENGTH_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_RXREG_LEAD_LAG_SEPARATION_DC = 56 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_EN_DRIVER_INVFB_DC = 59 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_CAL_GOOD = 61 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_CAL_ERROR = 62 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_CAL_ERROR_FINE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_DAC_LOWER_P0_ADR32S0_ADR0_REGS_RXDLL_VREG = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_DAC_LOWER_P0_ADR32S0_ADR0_REGS_RXDLL_VREG_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_DAC_LOWER_P0_ADR32S1_ADR1_REGS_RXDLL_VREG = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_DAC_LOWER_P0_ADR32S1_ADR1_REGS_RXDLL_VREG_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_DAC_UPPER_P0_ADR32S0_ADR0_REGS_RXDLL_VREG = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_DAC_UPPER_P0_ADR32S0_ADR0_REGS_RXDLL_VREG_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_DAC_UPPER_P0_ADR32S1_ADR1_REGS_RXDLL_VREG = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_DAC_UPPER_P0_ADR32S1_ADR1_REGS_RXDLL_VREG_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P0_ADR32S0_ADR0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P0_ADR32S0_ADR0_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P0_ADR32S1_ADR1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P0_ADR32S1_ADR1_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P0_ADR32S0_ADR0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P0_ADR32S0_ADR0_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P0_ADR32S1_ADR1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P0_ADR32S1_ADR1_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S0_ADR0_OVERRIDE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S0_ADR0_CAL_PD_ENABLE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S0_ADR0_MAIN_PD_ENABLE = 50 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S0_ADR0_DETECT_REQ = 51 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S0_ADR0_SLAVE_CAL_CKT_POWERDOWN = 52 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S0_ADR0_VREG_RXCAL_COMP_OUT_META = 56 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S0_ADR0_RXCAL_DETECT_DONE_META = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S0_ADR0_RXCAL_PD_CAL_LAG_META = 58 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S0_ADR0_RXCAL_PD_MAIN_LEAD_META = 59 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S0_ADR0_RXCAL_PD_MAIN_LAG_META = 60 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S0_ADR0_VREG_SLAVE1_COMP_OUT = 61 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S0_ADR0_VREG_SLAVE2_COMP_OUT = 62 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S1_ADR1_OVERRIDE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S1_ADR1_CAL_PD_ENABLE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S1_ADR1_MAIN_PD_ENABLE = 50 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S1_ADR1_DETECT_REQ = 51 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S1_ADR1_SLAVE_CAL_CKT_POWERDOWN = 52 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S1_ADR1_VREG_RXCAL_COMP_OUT_META = 56 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S1_ADR1_RXCAL_DETECT_DONE_META = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S1_ADR1_RXCAL_PD_CAL_LAG_META = 58 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S1_ADR1_RXCAL_PD_MAIN_LEAD_META = 59 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S1_ADR1_RXCAL_PD_MAIN_LAG_META = 60 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S1_ADR1_VREG_SLAVE1_COMP_OUT = 61 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_0_P0_ADR32S1_ADR1_VREG_SLAVE2_COMP_OUT = 62 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_1_P0_ADR32S0_ADR0_SLAVE_VREG_OVERRIDE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_1_P0_ADR32S0_ADR0_SLAVE_VREG_REF_SEL_DC = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_1_P0_ADR32S0_ADR0_SLAVE_VREG_REF_SEL_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_1_P0_ADR32S0_ADR0_SLAVE_VREG_DAC_COARSE = 52 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_1_P0_ADR32S0_ADR0_SLAVE_VREG_DAC_COARSE_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_1_P0_ADR32S0_ADR0_DD2_IE_FIX_DISABLE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_1_P0_ADR32S1_ADR1_SLAVE_VREG_OVERRIDE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_1_P0_ADR32S1_ADR1_SLAVE_VREG_REF_SEL_DC = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_1_P0_ADR32S1_ADR1_SLAVE_VREG_REF_SEL_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_1_P0_ADR32S1_ADR1_SLAVE_VREG_DAC_COARSE = 52 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_1_P0_ADR32S1_ADR1_SLAVE_VREG_DAC_COARSE_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_SW_CONTROL_1_P0_ADR32S1_ADR1_DD2_IE_FIX_DISABLE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S0_ADR0_REGS_RXDLL_EN = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S0_ADR0_REGS_RXDLL_EN_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S0_ADR0_REGS_RXDLL_DAC = 56 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S0_ADR0_REGS_RXDLL_DAC_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S1_ADR1_REGS_RXDLL_EN = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S1_ADR1_REGS_RXDLL_EN_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S1_ADR1_REGS_RXDLL_DAC = 56 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S1_ADR1_REGS_RXDLL_DAC_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_HS_DLLMUX_SEL_0_3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_HS_DLLMUX_SEL_0_3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_STRENGTH = 59 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_STRENGTH_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_ANALOG_WRAPON = 63 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_HS_DLLMUX_SEL_0_3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_HS_DLLMUX_SEL_0_3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_STRENGTH = 59 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_STRENGTH_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_ANALOG_WRAPON = 63 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_RXREG_COMPCON_DC = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_RXREG_COMPCON_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_RXREG_DAC_PULLUP_DC = 52 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_RXREG_DRVCON_DC = 53 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_RXREG_DRVCON_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_RXREG_REF_SEL_DC = 56 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_RXREG_REF_SEL_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_REGS_RXDLL_COARSE_ADJ_BY0 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_CAL_CKTS_ACTIVE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_RXREG_COMPCON_DC = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_RXREG_COMPCON_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_RXREG_DAC_PULLUP_DC = 52 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_RXREG_DRVCON_DC = 53 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_RXREG_DRVCON_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_RXREG_REF_SEL_DC = 56 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_RXREG_REF_SEL_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_REGS_RXDLL_COARSE_ADJ_BY0 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_CAL_CKTS_ACTIVE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL1 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL2 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL3 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL4 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL6 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL7 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL1 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL2 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL3 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL4 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL6 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL7 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL1 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL2 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL3 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL4 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL6 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL7 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL1 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL2 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL3 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL4 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL6 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL7 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL8 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL9 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL10 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL11 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL12 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL13 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL14 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL15 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL8 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL9 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL10 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL11 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL12 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL13 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL14 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL15 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL8 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL9 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL10 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL11 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL12 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL13 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL14 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL15 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL8 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL9 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL10 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL11 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL12 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL13 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL14 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL15 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S0_ADR0_TSYS = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S0_ADR0_TSYS_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S1_ADR1_TSYS = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S1_ADR1_TSYS_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P0_ADR32S0_ADR0_VALUE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P0_ADR32S0_ADR0_VALUE_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P0_ADR32S1_ADR1_VALUE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P0_ADR32S1_ADR1_VALUE_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P0_ADR32S0_ADR0_VALUE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P0_ADR32S0_ADR0_VALUE_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P0_ADR32S1_ADR1_VALUE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P0_ADR32S1_ADR1_VALUE_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_FLUSH = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_EN = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_INIT_IO = 50 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_HS_PROBE_A_SEL_0_3 = 51 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_HS_PROBE_A_SEL_0_3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_HS_PROBE_B_SEL_0_3 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_HS_PROBE_B_SEL_0_3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_ATESTSEL_0_2 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_ATESTSEL_0_2_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_FLUSH = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_EN = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_INIT_IO = 50 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_HS_PROBE_A_SEL_0_3 = 51 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_HS_PROBE_A_SEL_0_3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_HS_PROBE_B_SEL_0_3 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_HS_PROBE_B_SEL_0_3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_ATESTSEL_0_2 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_ATESTSEL_0_2_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR0_01_LANE__0_7_PD = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR0_01_LANE__0_7_PD_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR0_01_LANE__8_11_PD = 56 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR0_01_LANE__8_11_PD_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR0_01_LANE__12_15_PD = 60 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR0_01_LANE__12_15_PD_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR1_01_LANE__0_7_PD = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR1_01_LANE__0_7_PD_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR1_01_LANE__8_11_PD = 56 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR1_01_LANE__8_11_PD_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR1_01_LANE__12_15_PD = 60 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR1_01_LANE__12_15_PD_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR2_23_LANE__0_7_PD = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR2_23_LANE__0_7_PD_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR2_23_LANE__8_11_PD = 56 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR2_23_LANE__8_11_PD_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR2_23_LANE__12_15_PD = 60 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR2_23_LANE__12_15_PD_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR3_23_LANE__0_7_PD = 48 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR3_23_LANE__0_7_PD_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR3_23_LANE__8_11_PD = 56 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR3_23_LANE__8_11_PD_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR3_23_LANE__12_15_PD = 60 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR3_23_LANE__12_15_PD_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_ROT_OVERRIDE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_ROT_OVERRIDE_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_ROT_OVERRIDE_EN = 56 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_PHASE_ALIGN_RESET = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_PHASE_EN = 58 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_PHASE_DEFAULT_EN = 59 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_POS_EDGE_ALIGN = 60 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_CONTINUOUS_UPDATE = 61 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_DD2_CG_DISABLE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_ROT_OVERRIDE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_ROT_OVERRIDE_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_ROT_OVERRIDE_EN = 56 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_PHASE_ALIGN_RESET = 57 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_PHASE_EN = 58 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_PHASE_DEFAULT_EN = 59 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_POS_EDGE_ALIGN = 60 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_CONTINUOUS_UPDATE = 61 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_DD2_CG_DISABLE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_ADR0_ROT = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_ADR0_ROT_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_ADR0_BB_LOCK = 56 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1_ADR1_ROT = 49 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1_ADR1_ROT_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1_ADR1_BB_LOCK = 56 ; static const uint8_t P9N2_MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_CNTL = 48 ; static const uint8_t P9N2_MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_CNTL_LEN = 5 ; static const uint8_t P9N2_MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_INJECT_FIR_ERR0_4 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_INJECT_FIR_ERR1_5 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_INJECT_FIR_ERR2_6 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_INJECT_FIR_ERR3_7 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_INJECT_FIR_ERR = 58 ; static const uint8_t P9N2_MCA_DDRPHY_APB_CONFIG0_P0_DISABLE_PARITY_CHECKER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_APB_CONFIG0_P0_RESET_ERR_RPT = 49 ; static const uint8_t P9N2_MCA_DDRPHY_APB_CONFIG0_P0_FORCE_ON_CLK_GATE = 50 ; static const uint8_t P9N2_MCA_DDRPHY_APB_CONFIG0_P0_DEBUG_BUS_SEL = 51 ; static const uint8_t P9N2_MCA_DDRPHY_APB_CONFIG0_P0_DEBUG_BUS_SEL_LEN = 5 ; static const uint8_t P9N2_MCA_DDRPHY_APB_CONFIG0_P0_ADR_SLAVE_SEL = 56 ; static const uint8_t P9N2_MCA_DDRPHY_APB_CONFIG0_P0_DEBUG_BUS_SEL2 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_APB_CONFIG0_P0_DEBUG_BUS_SEL2_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_APB_CONFIG0_P0_LOW_PROBE_TRACE_GATE = 61 ; static const uint8_t P9N2_MCA_DDRPHY_APB_CONFIG0_P0_HS_PROBE_TOP_SEL = 62 ; static const uint8_t P9N2_MCA_DDRPHY_APB_ERROR_MASK0_P0_INVALID_ADDRESS_MASK = 48 ; static const uint8_t P9N2_MCA_DDRPHY_APB_ERROR_MASK0_P0_WR_PAR_ERR_MASK = 49 ; static const uint8_t P9N2_MCA_DDRPHY_APB_ERROR_STATUS0_P0_INVALID_ADDRESS = 48 ; static const uint8_t P9N2_MCA_DDRPHY_APB_ERROR_STATUS0_P0_WR_PAR_ERR = 49 ; static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_SET0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_SET1 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_SET2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_SET3 = 51 ; static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_SET4 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_SET5 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_FSM_DP16 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_FSM_DP16_LEN = 5 ; static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR0_P0_PC_ERR_STATUS0 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR0_P0_PC_ERR_STATUS0_LEN = 5 ; static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR1_P0_PC_INIT_CAL_ERR = 48 ; static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR1_P0_PC_INIT_CAL_ERR_LEN = 12 ; static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR1_P0_DP_DLL_CAL_ERROR = 60 ; static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR1_P0_DP_DLL_CAL_ERROR_FINE = 61 ; static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR1_P0_ADR_DLL_CAL_ERROR = 62 ; static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR1_P0_ADR_DLL_CAL_ERROR_FINE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR2_P0_ERR0_REG_DP16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR2_P0_ERR0_REG_DP16_LEN = 5 ; static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR2_P0_ERR1_REG_DP16 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR2_P0_ERR1_REG_DP16_LEN = 5 ; static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR2_P0_REG_DP16 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR2_P0_REG_DP16_LEN = 5 ; static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR3_P0_REG_DP16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR3_P0_REG_DP16_LEN = 5 ; static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR3_P0_ERR4_REG_DP16 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR3_P0_ERR4_REG_DP16_LEN = 5 ; static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR3_P0_ERR5_REG_DP16 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_APB_FIR_ERR3_P0_ERR5_REG_DP16_LEN = 5 ; static const uint8_t P9N2_MCA_DDRPHY_APB_LO_PROBE_SEL_P0_RESET_0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_APB_LO_PROBE_SEL_P0_HOLD_0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_APB_LO_PROBE_SEL_P0_0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_APB_LO_PROBE_SEL_P0_0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_APB_LO_PROBE_SEL_P0_RESET_1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_APB_LO_PROBE_SEL_P0_HOLD_1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_APB_LO_PROBE_SEL_P0_1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_APB_LO_PROBE_SEL_P0_1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICENDRV_DC = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICENDRV_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICEPDRV_DC = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICEPDRV_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICEPTERM_DC = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICEPTERM_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1_01_S0ACENSLICENDRV_DC = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1_01_S0ACENSLICENDRV_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1_01_S0ACENSLICEPDRV_DC = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1_01_S0ACENSLICEPDRV_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1_01_S0ACENSLICEPTERM_DC = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1_01_S0ACENSLICEPTERM_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2_23_S0ACENSLICENDRV_DC = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2_23_S0ACENSLICENDRV_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2_23_S0ACENSLICEPDRV_DC = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2_23_S0ACENSLICEPDRV_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2_23_S0ACENSLICEPTERM_DC = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2_23_S0ACENSLICEPTERM_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3_23_S0ACENSLICENDRV_DC = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3_23_S0ACENSLICENDRV_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3_23_S0ACENSLICEPDRV_DC = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3_23_S0ACENSLICEPDRV_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3_23_S0ACENSLICEPTERM_DC = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3_23_S0ACENSLICEPTERM_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4_4_S0ACENSLICENDRV_DC = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4_4_S0ACENSLICENDRV_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4_4_S0ACENSLICEPDRV_DC = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4_4_S0ACENSLICEPDRV_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4_4_S0ACENSLICEPTERM_DC = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4_4_S0ACENSLICEPTERM_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0_01_S1ACENSLICENDRV_DC = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0_01_S1ACENSLICENDRV_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0_01_S1ACENSLICEPDRV_DC = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0_01_S1ACENSLICEPDRV_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0_01_S1ACENSLICEPTERM_DC = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0_01_S1ACENSLICEPTERM_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1_01_S1ACENSLICENDRV_DC = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1_01_S1ACENSLICENDRV_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1_01_S1ACENSLICEPDRV_DC = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1_01_S1ACENSLICEPDRV_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1_01_S1ACENSLICEPTERM_DC = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1_01_S1ACENSLICEPTERM_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2_23_S1ACENSLICENDRV_DC = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2_23_S1ACENSLICENDRV_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2_23_S1ACENSLICEPDRV_DC = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2_23_S1ACENSLICEPDRV_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2_23_S1ACENSLICEPTERM_DC = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2_23_S1ACENSLICEPTERM_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3_23_S1ACENSLICENDRV_DC = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3_23_S1ACENSLICENDRV_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3_23_S1ACENSLICEPDRV_DC = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3_23_S1ACENSLICEPDRV_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3_23_S1ACENSLICEPTERM_DC = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3_23_S1ACENSLICEPTERM_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4_4_S1ACENSLICENDRV_DC = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4_4_S1ACENSLICENDRV_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4_4_S1ACENSLICEPDRV_DC = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4_4_S1ACENSLICEPDRV_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4_4_S1ACENSLICEPTERM_DC = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4_4_S1ACENSLICEPTERM_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_0_01_DD2_COARSE_OF_DISABLE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_0_01_DD2_DBDIS_DQS_DISABLE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_0_01_DD2_SPARE_L2SFF_CG_DISABLE = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_0_01_FLUSH = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_0_01_DQS_FORCE_VALUE = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_0_01_P8_DD2_FIX_DIS = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_0_01_INIT_IO = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_0_01_ADVANCE_PING_PONG = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_0_01_WL_ADVANCE_DISABLE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_0_01_DISABLE_PING_PONG = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_0_01_DELAY_PING_PONG_HALF = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_0_01_ATESTSEL_4 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_0_01_ATESTSEL_4_LEN = 5 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_1_01_DD2_COARSE_OF_DISABLE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_1_01_DD2_DBDIS_DQS_DISABLE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_1_01_DD2_SPARE_L2SFF_CG_DISABLE = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_1_01_FLUSH = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_1_01_DQS_FORCE_VALUE = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_1_01_P8_DD2_FIX_DIS = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_1_01_INIT_IO = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_1_01_ADVANCE_PING_PONG = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_1_01_WL_ADVANCE_DISABLE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_1_01_DISABLE_PING_PONG = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_1_01_DELAY_PING_PONG_HALF = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_1_01_ATESTSEL_0_4 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_1_01_ATESTSEL_0_4_LEN = 5 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_2_23_DD2_COARSE_OF_DISABLE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_2_23_DD2_DBDIS_DQS_DISABLE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_2_23_DD2_SPARE_L2SFF_CG_DISABLE = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_2_23_FLUSH = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_2_23_DQS_FORCE_VALUE = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_2_23_P8_DD2_FIX_DIS = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_2_23_INIT_IO = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_2_23_ADVANCE_PING_PONG = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_2_23_WL_ADVANCE_DISABLE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_2_23_DISABLE_PING_PONG = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_2_23_DELAY_PING_PONG_HALF = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_2_23_ATESTSEL_0_4 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_2_23_ATESTSEL_0_4_LEN = 5 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_3_23_DD2_COARSE_OF_DISABLE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_3_23_DD2_DBDIS_DQS_DISABLE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_3_23_DD2_SPARE_L2SFF_CG_DISABLE = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_3_23_FLUSH = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_3_23_DQS_FORCE_VALUE = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_3_23_P8_DD2_FIX_DIS = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_3_23_INIT_IO = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_3_23_ADVANCE_PING_PONG = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_3_23_WL_ADVANCE_DISABLE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_3_23_DISABLE_PING_PONG = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_3_23_DELAY_PING_PONG_HALF = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_3_23_ATESTSEL_0_4 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_3_23_ATESTSEL_0_4_LEN = 5 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_4_4_DD2_COARSE_OF_DISABLE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_4_4_DD2_DBDIS_DQS_DISABLE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_4_4_DD2_SPARE_L2SFF_CG_DISABLE = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_4_4_FLUSH = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_4_4_DQS_FORCE_VALUE = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_4_4_P8_DD2_FIX_DIS = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_4_4_INIT_IO = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_4_4_ADVANCE_PING_PONG = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_4_4_WL_ADVANCE_DISABLE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_4_4_DISABLE_PING_PONG = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_4_4_DELAY_PING_PONG_HALF = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_4_4_ATESTSEL_0 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CONFIG0_P0_4_4_ATESTSEL_0_LEN = 5 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_2_DQSEL_CAP = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_2_DQSEL_CAP_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_2_BIAS_TRIM = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_2_BIAS_TRIM_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_2_DQSEL_RES = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_2_DQSEL_RES_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_1_3_DQSEL_CAP = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_1_3_DQSEL_CAP_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_1_3_BIAS_TRIM = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_1_3_BIAS_TRIM_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_1_3_DQSEL_RES = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_1_3_DQSEL_RES_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_0_2_DQSEL_CAP = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_0_2_DQSEL_CAP_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_0_2_BIAS_TRIM = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_0_2_BIAS_TRIM_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_0_2_DQSEL_RES = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_0_2_DQSEL_RES_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_3_DQSEL_CAP = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_3_DQSEL_CAP_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_3_BIAS_TRIM = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_3_BIAS_TRIM_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_3_DQSEL_RES = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_3_DQSEL_RES_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_0_DQSEL_CAP = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_0_DQSEL_CAP_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_0_BIAS_TRIM = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_0_BIAS_TRIM_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_0_DQSEL_RES = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_0_DQSEL_RES_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_1_3_DQSEL_CAP = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_1_3_DQSEL_CAP_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_1_3_BIAS_TRIM = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_1_3_BIAS_TRIM_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_1_3_DQSEL_RES = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_1_3_DQSEL_RES_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_0_2_DQSEL_CAP = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_0_2_DQSEL_CAP_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_0_2_BIAS_TRIM = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_0_2_BIAS_TRIM_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_0_2_DQSEL_RES = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_0_2_DQSEL_RES_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_1_DQSEL_CAP = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_1_DQSEL_CAP_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_1_BIAS_TRIM = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_1_BIAS_TRIM_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_1_DQSEL_RES = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_1_DQSEL_RES_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_0_2_DQSEL_CAP = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_0_2_DQSEL_CAP_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_0_2_BIAS_TRIM = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_0_2_BIAS_TRIM_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_0_2_DQSEL_RES = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_0_2_DQSEL_RES_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_1_3_DQSEL_CAP = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_1_3_DQSEL_CAP_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_1_3_BIAS_TRIM = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_1_3_BIAS_TRIM_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_1_3_DQSEL_RES = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_1_3_DQSEL_RES_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_2_DQSEL_CAP = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_2_DQSEL_CAP_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_2_BIAS_TRIM = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_2_BIAS_TRIM_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_2_DQSEL_RES = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_2_DQSEL_RES_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_1_3_DQSEL_CAP = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_1_3_DQSEL_CAP_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_1_3_BIAS_TRIM = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_1_3_BIAS_TRIM_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_1_3_DQSEL_RES = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_1_3_DQSEL_RES_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_0_2_DQSEL_CAP = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_0_2_DQSEL_CAP_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_0_2_BIAS_TRIM = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_0_2_BIAS_TRIM_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_0_2_DQSEL_RES = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_0_2_DQSEL_RES_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_3_DQSEL_CAP = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_3_DQSEL_CAP_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_3_BIAS_TRIM = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_3_BIAS_TRIM_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_3_DQSEL_RES = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_3_DQSEL_RES_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_0_DQSEL_CAP = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_0_DQSEL_CAP_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_0_BIAS_TRIM = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_0_BIAS_TRIM_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_0_DQSEL_RES = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_0_DQSEL_RES_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_1_3_DQSEL_CAP = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_1_3_DQSEL_CAP_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_1_3_BIAS_TRIM = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_1_3_BIAS_TRIM_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_1_3_DQSEL_RES = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_1_3_DQSEL_RES_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_0_2_DQSEL_CAP = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_0_2_DQSEL_CAP_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_0_2_BIAS_TRIM = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_0_2_BIAS_TRIM_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_0_2_DQSEL_RES = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_0_2_DQSEL_RES_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_1_DQSEL_CAP = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_1_DQSEL_CAP_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_1_BIAS_TRIM = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_1_BIAS_TRIM_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_1_DQSEL_RES = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_1_DQSEL_RES_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_0_2_DQSEL_CAP = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_0_2_DQSEL_CAP_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_0_2_BIAS_TRIM = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_0_2_BIAS_TRIM_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_0_2_DQSEL_RES = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_0_2_DQSEL_RES_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_1_3_DQSEL_CAP = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_1_3_DQSEL_CAP_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_1_3_BIAS_TRIM = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_1_3_BIAS_TRIM_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_1_3_DQSEL_RES = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_1_3_DQSEL_RES_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0_01_DLL_ADJUST = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0_01_DLL_ADJUST_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0_01_DLL_CORRECT_EN = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0_01_DLL_ITER_A = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0_01_DLL_CAL_ENABLE = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0_01_DLL_POWERDOWN = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0_01_DLL_CAL_DONE = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0_01_DLL_CAL_ERROR = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0_01_DLL_COMPARE_OUT = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1_01_DLL_ADJUST = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1_01_DLL_ADJUST_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1_01_DLL_CORRECT_EN = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1_01_DLL_ITER_A = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1_01_DLL_CAL_ENABLE = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1_01_DLL_POWERDOWN = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1_01_DLL_CAL_DONE = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1_01_DLL_CAL_ERROR = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1_01_DLL_COMPARE_OUT = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2_23_DLL_ADJUST = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2_23_DLL_ADJUST_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2_23_DLL_CORRECT_EN = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2_23_DLL_ITER_A = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2_23_DLL_CAL_ENABLE = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2_23_DLL_POWERDOWN = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2_23_DLL_CAL_DONE = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2_23_DLL_CAL_ERROR = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2_23_DLL_COMPARE_OUT = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3_23_DLL_ADJUST = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3_23_DLL_ADJUST_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3_23_DLL_CORRECT_EN = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3_23_DLL_ITER_A = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3_23_DLL_CAL_ENABLE = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3_23_DLL_POWERDOWN = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3_23_DLL_CAL_DONE = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3_23_DLL_CAL_ERROR = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3_23_DLL_COMPARE_OUT = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4_4_DLL_ADJUST = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4_4_DLL_ADJUST_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4_4_DLL_CORRECT_EN = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4_4_DLL_ITER_A = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4_4_DLL_CAL_ENABLE = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4_4_DLL_POWERDOWN = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4_4_DLL_CAL_DONE = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4_4_DLL_CAL_ERROR = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4_4_DLL_COMPARE_OUT = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0_01_DLL_ADJUST = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0_01_DLL_ADJUST_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0_01_DLL_CORRECT_EN = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0_01_DLL_ITER_A = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0_01_DLL_CAL_ENABLE = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0_01_DLL_POWERDOWN = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0_01_DLL_CAL_DONE = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0_01_DLL_CAL_ERROR = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0_01_DLL_COMPARE_OUT = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1_01_DLL_ADJUST = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1_01_DLL_ADJUST_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1_01_DLL_CORRECT_EN = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1_01_DLL_ITER_A = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1_01_DLL_CAL_ENABLE = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1_01_DLL_POWERDOWN = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1_01_DLL_CAL_DONE = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1_01_DLL_CAL_ERROR = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1_01_DLL_COMPARE_OUT = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2_23_DLL_ADJUST = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2_23_DLL_ADJUST_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2_23_DLL_CORRECT_EN = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2_23_DLL_ITER_A = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2_23_DLL_CAL_ENABLE = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2_23_DLL_POWERDOWN = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2_23_DLL_CAL_DONE = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2_23_DLL_CAL_ERROR = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2_23_DLL_COMPARE_OUT = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3_23_DLL_ADJUST = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3_23_DLL_ADJUST_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3_23_DLL_CORRECT_EN = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3_23_DLL_ITER_A = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3_23_DLL_CAL_ENABLE = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3_23_DLL_POWERDOWN = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3_23_DLL_CAL_DONE = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3_23_DLL_CAL_ERROR = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3_23_DLL_COMPARE_OUT = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4_4_DLL_ADJUST = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4_4_DLL_ADJUST_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4_4_DLL_CORRECT_EN = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4_4_DLL_ITER_A = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4_4_DLL_CAL_ENABLE = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4_4_DLL_POWERDOWN = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4_4_DLL_CAL_DONE = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4_4_DLL_CAL_ERROR = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4_4_DLL_COMPARE_OUT = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_0_01_HS_PROBE_A = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_0_01_HS_PROBE_A_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_0_01_HS_PROBE_B = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_0_01_HS_PROBE_B_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_0_01_RD = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_0_01_RD_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_1_01_HS_PROBE_A = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_1_01_HS_PROBE_A_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_1_01_HS_PROBE_B = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_1_01_HS_PROBE_B_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_1_01_RD = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_1_01_RD_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_2_23_HS_PROBE_A = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_2_23_HS_PROBE_A_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_2_23_HS_PROBE_B = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_2_23_HS_PROBE_B_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_2_23_RD = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_2_23_RD_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_3_23_HS_PROBE_A = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_3_23_HS_PROBE_A_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_3_23_HS_PROBE_B = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_3_23_HS_PROBE_B_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_3_23_RD = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_3_23_RD_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_4_4_HS_PROBE_A = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_4_4_HS_PROBE_A_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_4_4_HS_PROBE_B = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_4_4_HS_PROBE_B_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_4_4_RD = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DEBUG_SEL_P0_4_4_RD_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0_01_QUAD0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0_01_QUAD0_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0_01_QUAD1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0_01_QUAD1_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0_01_QUAD2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0_01_QUAD2_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0_01_QUAD3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0_01_QUAD3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_1_01_QUAD0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_1_01_QUAD0_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_1_01_QUAD1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_1_01_QUAD1_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_1_01_QUAD2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_1_01_QUAD2_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_1_01_QUAD3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_1_01_QUAD3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_2_23_QUAD0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_2_23_QUAD0_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_2_23_QUAD1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_2_23_QUAD1_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_2_23_QUAD2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_2_23_QUAD2_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_2_23_QUAD3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_2_23_QUAD3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_3_23_QUAD0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_3_23_QUAD0_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_3_23_QUAD1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_3_23_QUAD1_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_3_23_QUAD2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_3_23_QUAD2_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_3_23_QUAD3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_3_23_QUAD3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4_4_QUAD0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4_4_QUAD0_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4_4_QUAD1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4_4_QUAD1_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4_4_QUAD2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4_4_QUAD2_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4_4_QUAD3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4_4_QUAD3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_0_01_DIGITAL_EN = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_0_01_BUMP = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_0_01_TRIG_PERIOD = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_0_01_CNTL_POL = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_0_01_CNTL_SRC = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_1_01_DIGITAL_EN = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_1_01_BUMP = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_1_01_TRIG_PERIOD = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_1_01_CNTL_POL = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_1_01_CNTL_SRC = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_2_23_DIGITAL_EN = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_2_23_BUMP = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_2_23_TRIG_PERIOD = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_2_23_CNTL_POL = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_2_23_CNTL_SRC = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_3_23_DIGITAL_EN = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_3_23_BUMP = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_3_23_TRIG_PERIOD = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_3_23_CNTL_POL = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_3_23_CNTL_SRC = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_4_4_DIGITAL_EN = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_4_4_BUMP = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_4_4_TRIG_PERIOD = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_4_4_CNTL_POL = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_4_4_CNTL_SRC = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_0_01_FORCE_OUTPUTS = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_0_01_PRBS7_GEN_EN = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_0_01_WRAPSEL = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_0_01_MRS_CMD_DATA_N0 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_0_01_MRS_CMD_DATA_N1 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_0_01_MRS_CMD_DATA_N2 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_0_01_MRS_CMD_DATA_N3 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_1_01_FORCE_OUTPUTS = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_1_01_PRBS7_GEN_EN = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_1_01_WRAPSEL = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_1_01_MRS_CMD_DATA_N0 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_1_01_MRS_CMD_DATA_N1 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_1_01_MRS_CMD_DATA_N2 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_1_01_MRS_CMD_DATA_N3 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_2_23_FORCE_OUTPUTS = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_2_23_PRBS7_GEN_EN = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_2_23_WRAPSEL = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_2_23_MRS_CMD_DATA_N0 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_2_23_MRS_CMD_DATA_N1 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_2_23_MRS_CMD_DATA_N2 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_2_23_MRS_CMD_DATA_N3 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_3_23_FORCE_OUTPUTS = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_3_23_PRBS7_GEN_EN = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_3_23_WRAPSEL = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_3_23_MRS_CMD_DATA_N0 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_3_23_MRS_CMD_DATA_N1 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_3_23_MRS_CMD_DATA_N2 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_3_23_MRS_CMD_DATA_N3 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_4_4_FORCE_OUTPUTS = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_4_4_PRBS7_GEN_EN = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_4_4_WRAPSEL = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_4_4_MRS_CMD_DATA_N0 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_4_4_MRS_CMD_DATA_N1 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_4_4_MRS_CMD_DATA_N2 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_PDA_CONTROL_P0_4_4_MRS_CMD_DATA_N3 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_0_01_CHECKER_ENABLE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_0_01_CHECKER_RESET = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_0_01_SYNC = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_0_01_SYNC_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_0_01_ERROR = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_0_01_ERROR_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_1_01_CHECKER_ENABLE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_1_01_CHECKER_RESET = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_1_01_SYNC = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_1_01_SYNC_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_1_01_ERROR = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_1_01_ERROR_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_2_23_CHECKER_ENABLE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_2_23_CHECKER_RESET = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_2_23_SYNC = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_2_23_SYNC_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_2_23_ERROR = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_2_23_ERROR_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_3_23_CHECKER_ENABLE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_3_23_CHECKER_RESET = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_3_23_SYNC = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_3_23_SYNC_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_3_23_ERROR = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_3_23_ERROR_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_4_4_CHECKER_ENABLE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_4_4_CHECKER_RESET = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_4_4_SYNC = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_4_4_SYNC_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_4_4_ERROR = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_4_4_ERROR_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_INIT_RXDLL_CAL_RESET = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_INIT_RXDLL_CAL_UPDATE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_REGS_RXDLL_CAL_SKIP = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_REGS_RXDLL_CAL_SKIP_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_REGS_RXDLL_COARSE_ADJ_BY2 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_RXREG_FILTER_LENGTH_DC = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_RXREG_FILTER_LENGTH_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_RXREG_LEAD_LAG_SEPARATION_DC = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_EN_DRIVER_INVFB_DC = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_CAL_GOOD = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_CAL_ERROR = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_CAL_ERROR_FINE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_INIT_RXDLL_CAL_RESET = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_INIT_RXDLL_CAL_UPDATE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_REGS_RXDLL_CAL_SKIP = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_REGS_RXDLL_CAL_SKIP_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_REGS_RXDLL_COARSE_ADJ_BY2 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_RXREG_FILTER_LENGTH_DC = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_RXREG_FILTER_LENGTH_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_RXREG_LEAD_LAG_SEPARATION_DC = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_EN_DRIVER_INVFB_DC = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_CAL_GOOD = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_CAL_ERROR = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_CAL_ERROR_FINE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_INIT_RXDLL_CAL_RESET = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_INIT_RXDLL_CAL_UPDATE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_REGS_RXDLL_CAL_SKIP = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_REGS_RXDLL_CAL_SKIP_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_REGS_RXDLL_COARSE_ADJ_BY2 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_RXREG_FILTER_LENGTH_DC = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_RXREG_FILTER_LENGTH_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_RXREG_LEAD_LAG_SEPARATION_DC = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_EN_DRIVER_INVFB_DC = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_CAL_GOOD = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_CAL_ERROR = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_CAL_ERROR_FINE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_INIT_RXDLL_CAL_RESET = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_INIT_RXDLL_CAL_UPDATE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_REGS_RXDLL_CAL_SKIP = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_REGS_RXDLL_CAL_SKIP_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_REGS_RXDLL_COARSE_ADJ_BY2 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_RXREG_FILTER_LENGTH_DC = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_RXREG_FILTER_LENGTH_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_RXREG_LEAD_LAG_SEPARATION_DC = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_EN_DRIVER_INVFB_DC = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_CAL_GOOD = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_CAL_ERROR = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_CAL_ERROR_FINE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_INIT_RXDLL_CAL_RESET = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_INIT_RXDLL_CAL_UPDATE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_REGS_RXDLL_CAL_SKIP = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_REGS_RXDLL_CAL_SKIP_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_REGS_RXDLL_COARSE_ADJ_BY2 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_RXREG_FILTER_LENGTH_DC = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_RXREG_FILTER_LENGTH_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_RXREG_LEAD_LAG_SEPARATION_DC = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_EN_DRIVER_INVFB_DC = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_CAL_GOOD = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_CAL_ERROR = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_CAL_ERROR_FINE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_INIT_RXDLL_CAL_RESET = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_INIT_RXDLL_CAL_UPDATE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_REGS_RXDLL_CAL_SKIP = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_REGS_RXDLL_CAL_SKIP_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_REGS_RXDLL_COARSE_ADJ_BY2 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_RXREG_FILTER_LENGTH_DC = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_RXREG_FILTER_LENGTH_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_RXREG_LEAD_LAG_SEPARATION_DC = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_EN_DRIVER_INVFB_DC = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_CAL_GOOD = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_CAL_ERROR = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_CAL_ERROR_FINE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_INIT_RXDLL_CAL_RESET = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_INIT_RXDLL_CAL_UPDATE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_REGS_RXDLL_CAL_SKIP = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_REGS_RXDLL_CAL_SKIP_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_REGS_RXDLL_COARSE_ADJ_BY2 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_RXREG_FILTER_LENGTH_DC = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_RXREG_FILTER_LENGTH_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_RXREG_LEAD_LAG_SEPARATION_DC = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_EN_DRIVER_INVFB_DC = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_CAL_GOOD = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_CAL_ERROR = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_CAL_ERROR_FINE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_INIT_RXDLL_CAL_RESET = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_INIT_RXDLL_CAL_UPDATE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_REGS_RXDLL_CAL_SKIP = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_REGS_RXDLL_CAL_SKIP_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_REGS_RXDLL_COARSE_ADJ_BY2 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_RXREG_FILTER_LENGTH_DC = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_RXREG_FILTER_LENGTH_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_RXREG_LEAD_LAG_SEPARATION_DC = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_EN_DRIVER_INVFB_DC = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_CAL_GOOD = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_CAL_ERROR = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_CAL_ERROR_FINE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_INIT_RXDLL_CAL_RESET = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_INIT_RXDLL_CAL_UPDATE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_REGS_RXDLL_CAL_SKIP = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_REGS_RXDLL_CAL_SKIP_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_REGS_RXDLL_COARSE_ADJ_BY2 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_RXREG_FILTER_LENGTH_DC = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_RXREG_FILTER_LENGTH_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_RXREG_LEAD_LAG_SEPARATION_DC = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_EN_DRIVER_INVFB_DC = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_CAL_GOOD = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_CAL_ERROR = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_CAL_ERROR_FINE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_INIT_RXDLL_CAL_RESET = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_INIT_RXDLL_CAL_UPDATE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_REGS_RXDLL_CAL_SKIP = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_REGS_RXDLL_CAL_SKIP_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_REGS_RXDLL_COARSE_ADJ_BY2 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_RXREG_FILTER_LENGTH_DC = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_RXREG_FILTER_LENGTH_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_RXREG_LEAD_LAG_SEPARATION_DC = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_EN_DRIVER_INVFB_DC = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_CAL_GOOD = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_CAL_ERROR = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_CAL_ERROR_FINE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_HS_DLLMUX_SEL_0_3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_HS_DLLMUX_SEL_0_3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_HS_DLLMUX_SEL_1_3 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_HS_DLLMUX_SEL_1_3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_S0INSDLYTAP = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_S1INSDLYTAP = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_HS_DLLMUX_SEL_0_0_3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_HS_DLLMUX_SEL_0_0_3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_HS_DLLMUX_SEL_0_3 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_HS_DLLMUX_SEL_0_3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_S0INSDLYTAP = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_S1INSDLYTAP = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_HS_DLLMUX_SEL_0_0_3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_HS_DLLMUX_SEL_0_0_3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_HS_DLLMUX_SEL_1_0_3 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_HS_DLLMUX_SEL_1_0_3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_S0INSDLYTAP = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_S1INSDLYTAP = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_HS_DLLMUX_SEL_0_0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_HS_DLLMUX_SEL_0_0_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_HS_DLLMUX_SEL_1_0 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_HS_DLLMUX_SEL_1_0_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_S0INSDLYTAP = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_S1INSDLYTAP = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_HS_DLLMUX_SEL_0_0_3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_HS_DLLMUX_SEL_0_0_3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_HS_DLLMUX_SEL_1_0_3 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_HS_DLLMUX_SEL_1_0_3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_S0INSDLYTAP = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_S1INSDLYTAP = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_0_01_REGS_RXDLL_VREG_LOWER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_0_01_REGS_RXDLL_VREG_LOWER_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_0_01_RESERVED_63 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_1_01_REGS_RXDLL_VREG_LOWER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_1_01_REGS_RXDLL_VREG_LOWER_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_1_01_RESERVED_63 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_2_23_REGS_RXDLL_VREG_LOWER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_2_23_REGS_RXDLL_VREG_LOWER_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_2_23_RESERVED_63 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_3_23_REGS_RXDLL_VREG_LOWER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_3_23_REGS_RXDLL_VREG_LOWER_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_3_23_RESERVED_63 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_4_4_REGS_RXDLL_VREG_LOWER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_4_4_REGS_RXDLL_VREG_LOWER_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_4_4_RESERVED_63 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_0_01_REGS_RXDLL_VREG_LOWER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_0_01_REGS_RXDLL_VREG_LOWER_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_0_01_RESERVED_63 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_1_01_REGS_RXDLL_VREG_LOWER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_1_01_REGS_RXDLL_VREG_LOWER_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_1_01_RESERVED_63 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_2_23_REGS_RXDLL_VREG_LOWER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_2_23_REGS_RXDLL_VREG_LOWER_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_2_23_RESERVED_63 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_3_23_REGS_RXDLL_VREG_LOWER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_3_23_REGS_RXDLL_VREG_LOWER_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_3_23_RESERVED_63 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_4_4_REGS_RXDLL_VREG_LOWER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_4_4_REGS_RXDLL_VREG_LOWER_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_4_4_RESERVED_63 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_0_01_REGS_RXDLL_VREG_UPPER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_0_01_REGS_RXDLL_VREG_UPPER_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_0_01_RESERVED_63 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_1_01_REGS_RXDLL_VREG_UPPER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_1_01_REGS_RXDLL_VREG_UPPER_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_1_01_RESERVED_63 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_2_23_REGS_RXDLL_VREG_UPPER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_2_23_REGS_RXDLL_VREG_UPPER_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_2_23_RESERVED_63 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_3_23_REGS_RXDLL_VREG_UPPER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_3_23_REGS_RXDLL_VREG_UPPER_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_3_23_RESERVED_63 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_4_4_REGS_RXDLL_VREG_UPPER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_4_4_REGS_RXDLL_VREG_UPPER_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_4_4_RESERVED_63 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_0_01_REGS_RXDLL_VREG_UPPER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_0_01_REGS_RXDLL_VREG_UPPER_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_0_01_RESERVED_63 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_1_01_REGS_RXDLL_VREG_UPPER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_1_01_REGS_RXDLL_VREG_UPPER_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_1_01_RESERVED_63 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_2_23_REGS_RXDLL_VREG_UPPER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_2_23_REGS_RXDLL_VREG_UPPER_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_2_23_RESERVED_63 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_3_23_REGS_RXDLL_VREG_UPPER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_3_23_REGS_RXDLL_VREG_UPPER_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_3_23_RESERVED_63 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_4_4_REGS_RXDLL_VREG_UPPER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_4_4_REGS_RXDLL_VREG_UPPER_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_4_4_RESERVED_63 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_0_01_SLAVE_VREG_OVERRIDE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_0_01_SLAVE_VREG_REF_SEL_DC = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_0_01_SLAVE_VREG_REF_SEL_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_0_01_SLAVE_VREG_DAC_COARSE = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_0_01_SLAVE_VREG_DAC_COARSE_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_1_01_SLAVE_VREG_OVERRIDE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_1_01_SLAVE_VREG_REF_SEL_DC = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_1_01_SLAVE_VREG_REF_SEL_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_1_01_SLAVE_VREG_DAC_COARSE = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_1_01_SLAVE_VREG_DAC_COARSE_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_2_23_SLAVE_VREG_OVERRIDE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_2_23_SLAVE_VREG_REF_SEL_DC = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_2_23_SLAVE_VREG_REF_SEL_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_2_23_SLAVE_VREG_DAC_COARSE = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_2_23_SLAVE_VREG_DAC_COARSE_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_3_23_SLAVE_VREG_OVERRIDE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_3_23_SLAVE_VREG_REF_SEL_DC = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_3_23_SLAVE_VREG_REF_SEL_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_3_23_SLAVE_VREG_DAC_COARSE = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_3_23_SLAVE_VREG_DAC_COARSE_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_4_4_SLAVE_VREG_OVERRIDE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_4_4_SLAVE_VREG_REF_SEL_DC = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_4_4_SLAVE_VREG_REF_SEL_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_4_4_SLAVE_VREG_DAC_COARSE = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA0_P0_4_4_SLAVE_VREG_DAC_COARSE_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_0_01_SLAVE_VREG_OVERRIDE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_0_01_SLAVE_VREG_REF_SEL_DC = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_0_01_SLAVE_VREG_REF_SEL_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_0_01_SLAVE_VREG_DAC_COARSE = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_0_01_SLAVE_VREG_DAC_COARSE_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_1_01_SLAVE_VREG_OVERRIDE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_1_01_SLAVE_VREG_REF_SEL_DC = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_1_01_SLAVE_VREG_REF_SEL_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_1_01_SLAVE_VREG_DAC_COARSE = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_1_01_SLAVE_VREG_DAC_COARSE_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_2_23_SLAVE_VREG_OVERRIDE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_2_23_SLAVE_VREG_REF_SEL_DC = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_2_23_SLAVE_VREG_REF_SEL_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_2_23_SLAVE_VREG_DAC_COARSE = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_2_23_SLAVE_VREG_DAC_COARSE_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_3_23_SLAVE_VREG_OVERRIDE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_3_23_SLAVE_VREG_REF_SEL_DC = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_3_23_SLAVE_VREG_REF_SEL_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_3_23_SLAVE_VREG_DAC_COARSE = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_3_23_SLAVE_VREG_DAC_COARSE_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_4_4_SLAVE_VREG_OVERRIDE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_4_4_SLAVE_VREG_REF_SEL_DC = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_4_4_SLAVE_VREG_REF_SEL_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_4_4_SLAVE_VREG_DAC_COARSE = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_EXTRA1_P0_4_4_SLAVE_VREG_DAC_COARSE_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_0_01_LOWER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_0_01_LOWER_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_1_01_LOWER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_1_01_LOWER_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_2_23_LOWER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_2_23_LOWER_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_3_23_LOWER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_3_23_LOWER_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_4_4_LOWER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_4_4_LOWER_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_0_01_LOWER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_0_01_LOWER_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_1_01_LOWER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_1_01_LOWER_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_2_23_LOWER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_2_23_LOWER_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_3_23_LOWER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_3_23_LOWER_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_4_4_LOWER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_4_4_LOWER_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_0_01_UPPER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_0_01_UPPER_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_1_01_UPPER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_1_01_UPPER_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_2_23_UPPER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_2_23_UPPER_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_3_23_UPPER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_3_23_UPPER_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_4_4_UPPER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_4_4_UPPER_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_0_01_UPPER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_0_01_UPPER_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_1_01_UPPER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_1_01_UPPER_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_2_23_UPPER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_2_23_UPPER_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_3_23_UPPER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_3_23_UPPER_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_4_4_UPPER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_4_4_UPPER_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_OVERRIDE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_CAL_PD_ENABLE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_MAIN_PD_ENABLE = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_DETECT_REQ = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_SLAVE_CAL_CKT_POWERDOWN = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_VREG_RXCAL_COMP_OUT_META = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_RXCAL_DETECT_DONE_META = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_RXCAL_PD_CAL_LAG_META = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_RXCAL_PD_MAIN_LEAD_META = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_RXCAL_PD_MAIN_LAG_META = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_VREG_SLAVE_COMP_OUT = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_OVERRIDE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_CAL_PD_ENABLE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_MAIN_PD_ENABLE = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_DETECT_REQ = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_SLAVE_CAL_CKT_POWERDOWN = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_VREG_RXCAL_COMP_OUT_META = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_RXCAL_DETECT_DONE_META = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_RXCAL_PD_CAL_LAG_META = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_RXCAL_PD_MAIN_LEAD_META = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_RXCAL_PD_MAIN_LAG_META = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_VREG_SLAVE_COMP_OUT = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_OVERRIDE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_CAL_PD_ENABLE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_MAIN_PD_ENABLE = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_DETECT_REQ = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_SLAVE_CAL_CKT_POWERDOWN = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_VREG_RXCAL_COMP_OUT_META = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_RXCAL_DETECT_DONE_META = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_RXCAL_PD_CAL_LAG_META = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_RXCAL_PD_MAIN_LEAD_META = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_RXCAL_PD_MAIN_LAG_META = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_VREG_SLAVE_COMP_OUT = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_OVERRIDE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_CAL_PD_ENABLE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_MAIN_PD_ENABLE = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_DETECT_REQ = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_SLAVE_CAL_CKT_POWERDOWN = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_VREG_RXCAL_COMP_OUT_META = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_RXCAL_DETECT_DONE_META = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_RXCAL_PD_CAL_LAG_META = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_RXCAL_PD_MAIN_LEAD_META = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_RXCAL_PD_MAIN_LAG_META = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_VREG_SLAVE_COMP_OUT = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_OVERRIDE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_CAL_PD_ENABLE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_MAIN_PD_ENABLE = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_DETECT_REQ = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_SLAVE_CAL_CKT_POWERDOWN = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_VREG_RXCAL_COMP_OUT_META = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_RXCAL_DETECT_DONE_META = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_RXCAL_PD_CAL_LAG_META = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_RXCAL_PD_MAIN_LEAD_META = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_RXCAL_PD_MAIN_LAG_META = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_VREG_SLAVE_COMP_OUT = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_OVERRIDE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_CAL_PD_ENABLE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_MAIN_PD_ENABLE = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_DETECT_REQ = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_SLAVE_CAL_CKT_POWERDOWN = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_VREG_RXCAL_COMP_OUT_META = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_RXCAL_DETECT_DONE_META = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_RXCAL_PD_CAL_LAG_META = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_RXCAL_PD_MAIN_LEAD_META = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_RXCAL_PD_MAIN_LAG_META = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_VREG_SLAVE_COMP_OUT = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_OVERRIDE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_CAL_PD_ENABLE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_MAIN_PD_ENABLE = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_DETECT_REQ = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_SLAVE_CAL_CKT_POWERDOWN = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_VREG_RXCAL_COMP_OUT_META = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_RXCAL_DETECT_DONE_META = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_RXCAL_PD_CAL_LAG_META = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_RXCAL_PD_MAIN_LEAD_META = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_RXCAL_PD_MAIN_LAG_META = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_VREG_SLAVE_COMP_OUT = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_OVERRIDE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_CAL_PD_ENABLE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_MAIN_PD_ENABLE = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_DETECT_REQ = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_SLAVE_CAL_CKT_POWERDOWN = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_VREG_RXCAL_COMP_OUT_META = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_RXCAL_DETECT_DONE_META = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_RXCAL_PD_CAL_LAG_META = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_RXCAL_PD_MAIN_LEAD_META = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_RXCAL_PD_MAIN_LAG_META = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_VREG_SLAVE_COMP_OUT = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_OVERRIDE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_CAL_PD_ENABLE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_MAIN_PD_ENABLE = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_DETECT_REQ = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_SLAVE_CAL_CKT_POWERDOWN = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_VREG_RXCAL_COMP_OUT_META = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_RXCAL_DETECT_DONE_META = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_RXCAL_PD_CAL_LAG_META = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_RXCAL_PD_MAIN_LEAD_META = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_RXCAL_PD_MAIN_LAG_META = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_VREG_SLAVE_COMP_OUT = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_OVERRIDE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_CAL_PD_ENABLE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_MAIN_PD_ENABLE = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_DETECT_REQ = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_SLAVE_CAL_CKT_POWERDOWN = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_VREG_RXCAL_COMP_OUT_META = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_RXCAL_DETECT_DONE_META = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_RXCAL_PD_CAL_LAG_META = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_RXCAL_PD_MAIN_LEAD_META = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_RXCAL_PD_MAIN_LAG_META = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_VREG_SLAVE_COMP_OUT = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_0_01_REGS_RXDLL_COARSE_EN = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_0_01_REGS_RXDLL_COARSE_EN_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_0_01_REGS_RXDLL_DAC_COARSE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_0_01_REGS_RXDLL_DAC_COARSE_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_1_01_REGS_RXDLL_COARSE_EN = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_1_01_REGS_RXDLL_COARSE_EN_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_1_01_REGS_RXDLL_DAC_COARSE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_1_01_REGS_RXDLL_DAC_COARSE_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_2_23_REGS_RXDLL_COARSE_EN = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_2_23_REGS_RXDLL_COARSE_EN_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_2_23_REGS_RXDLL_DAC_COARSE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_2_23_REGS_RXDLL_DAC_COARSE_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_3_23_REGS_RXDLL_COARSE_EN = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_3_23_REGS_RXDLL_COARSE_EN_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_3_23_REGS_RXDLL_DAC_COARSE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_3_23_REGS_RXDLL_DAC_COARSE_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_4_4_REGS_RXDLL_COARSE_EN = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_4_4_REGS_RXDLL_COARSE_EN_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_4_4_REGS_RXDLL_DAC_COARSE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_4_4_REGS_RXDLL_DAC_COARSE_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_0_01_REGS_RXDLL_COARSE_EN = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_0_01_REGS_RXDLL_COARSE_EN_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_0_01_REGS_RXDLL_DAC_COARSE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_0_01_REGS_RXDLL_DAC_COARSE_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_1_01_REGS_RXDLL_COARSE_EN = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_1_01_REGS_RXDLL_COARSE_EN_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_1_01_REGS_RXDLL_DAC_COARSE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_1_01_REGS_RXDLL_DAC_COARSE_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_2_23_REGS_RXDLL_COARSE_EN = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_2_23_REGS_RXDLL_COARSE_EN_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_2_23_REGS_RXDLL_DAC_COARSE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_2_23_REGS_RXDLL_DAC_COARSE_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_3_23_REGS_RXDLL_COARSE_EN = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_3_23_REGS_RXDLL_COARSE_EN_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_3_23_REGS_RXDLL_DAC_COARSE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_3_23_REGS_RXDLL_DAC_COARSE_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_4_4_REGS_RXDLL_COARSE_EN = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_4_4_REGS_RXDLL_COARSE_EN_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_4_4_REGS_RXDLL_DAC_COARSE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_4_4_REGS_RXDLL_DAC_COARSE_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_RXREG_COMPCON_DC = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_RXREG_COMPCON_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_RXREG_DAC_PULLUP_DC = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_RXREG_DRVCON_DC = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_RXREG_DRVCON_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_RXREG_REF_SEL_DC = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_RXREG_REF_SEL_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_REGS_RXDLL_COARSE_ADJ_BY0 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_DRVREN_MODE = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_CAL_CKTS_ACTIVE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_RXREG_COMPCON_DC = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_RXREG_COMPCON_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_RXREG_DAC_PULLUP_DC = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_RXREG_DRVCON_DC = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_RXREG_DRVCON_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_RXREG_REF_SEL_DC = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_RXREG_REF_SEL_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_REGS_RXDLL_COARSE_ADJ_BY0 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_DRVREN_MODE = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_CAL_CKTS_ACTIVE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_RXREG_COMPCON_DC = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_RXREG_COMPCON_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_RXREG_DAC_PULLUP_DC = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_RXREG_DRVCON_DC = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_RXREG_DRVCON_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_RXREG_REF_SEL_DC = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_RXREG_REF_SEL_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_REGS_RXDLL_COARSE_ADJ_BY0 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_DRVREN_MODE = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_CAL_CKTS_ACTIVE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_RXREG_COMPCON_DC = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_RXREG_COMPCON_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_RXREG_DAC_PULLUP_DC = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_RXREG_DRVCON_DC = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_RXREG_DRVCON_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_RXREG_REF_SEL_DC = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_RXREG_REF_SEL_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_REGS_RXDLL_COARSE_ADJ_BY0 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_DRVREN_MODE = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_CAL_CKTS_ACTIVE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_RXREG_COMPCON_DC = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_RXREG_COMPCON_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_RXREG_DAC_PULLUP_DC = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_RXREG_DRVCON_DC = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_RXREG_DRVCON_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_RXREG_REF_SEL_DC = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_RXREG_REF_SEL_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_REGS_RXDLL_COARSE_ADJ_BY0 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_DRVREN_MODE = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_CAL_CKTS_ACTIVE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_RXREG_COMPCON_DC = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_RXREG_COMPCON_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_RXREG_DAC_PULLUP_DC = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_RXREG_DRVCON_DC = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_RXREG_DRVCON_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_RXREG_REF_SEL_DC = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_RXREG_REF_SEL_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_REGS_RXDLL_COARSE_ADJ_BY0 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_DRVREN_MODE = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_CAL_CKTS_ACTIVE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_RXREG_COMPCON_DC = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_RXREG_COMPCON_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_RXREG_DAC_PULLUP_DC = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_RXREG_DRVCON_DC = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_RXREG_DRVCON_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_RXREG_REF_SEL_DC = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_RXREG_REF_SEL_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_REGS_RXDLL_COARSE_ADJ_BY0 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_DRVREN_MODE = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_CAL_CKTS_ACTIVE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_RXREG_COMPCON_DC = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_RXREG_COMPCON_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_RXREG_DAC_PULLUP_DC = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_RXREG_DRVCON_DC = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_RXREG_DRVCON_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_RXREG_REF_SEL_DC = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_RXREG_REF_SEL_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_REGS_RXDLL_COARSE_ADJ_BY0 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_DRVREN_MODE = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_CAL_CKTS_ACTIVE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_RXREG_COMPCON_DC = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_RXREG_COMPCON_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_RXREG_DAC_PULLUP_DC = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_RXREG_DRVCON_DC = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_RXREG_DRVCON_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_RXREG_REF_SEL_DC = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_RXREG_REF_SEL_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_REGS_RXDLL_COARSE_ADJ_BY0 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_DRVREN_MODE = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_CAL_CKTS_ACTIVE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_RXREG_COMPCON_DC = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_RXREG_COMPCON_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_RXREG_DAC_PULLUP_DC = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_RXREG_DRVCON_DC = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_RXREG_DRVCON_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_RXREG_REF_SEL_DC = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_RXREG_REF_SEL_DC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_REGS_RXDLL_COARSE_ADJ_BY0 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_DRVREN_MODE = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_CAL_CKTS_ACTIVE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_0_01_DQS = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_0_01_DQS_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_1_01_DQS = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_1_01_DQS_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_2_23_DQS = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_2_23_DQS_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_3_23_DQS = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_3_23_DQS_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_4_4_DQS = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_4_4_DQS_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_0_01_ROT_CLK_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_0_01_ROT_CLK_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_0_01_ROT_CLK_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_0_01_ROT_CLK_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_1_01_ROT_CLK_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_1_01_ROT_CLK_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_1_01_ROT_CLK_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_1_01_ROT_CLK_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_2_23_ROT_CLK_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_2_23_ROT_CLK_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_2_23_ROT_CLK_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_2_23_ROT_CLK_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_3_23_ROT_CLK_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_3_23_ROT_CLK_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_3_23_ROT_CLK_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_3_23_ROT_CLK_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_4_4_ROT_CLK_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_4_4_ROT_CLK_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_4_4_ROT_CLK_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_4_4_ROT_CLK_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_0_01_ROT_CLK_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_0_01_ROT_CLK_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_0_01_ROT_CLK_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_0_01_ROT_CLK_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_1_01_ROT_CLK_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_1_01_ROT_CLK_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_1_01_ROT_CLK_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_1_01_ROT_CLK_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_2_23_ROT_CLK_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_2_23_ROT_CLK_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_2_23_ROT_CLK_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_2_23_ROT_CLK_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_3_23_ROT_CLK_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_3_23_ROT_CLK_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_3_23_ROT_CLK_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_3_23_ROT_CLK_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_4_4_ROT_CLK_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_4_4_ROT_CLK_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_4_4_ROT_CLK_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_4_4_ROT_CLK_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_0_01_ROT_CLK_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_0_01_ROT_CLK_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_0_01_ROT_CLK_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_0_01_ROT_CLK_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_1_01_ROT_CLK_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_1_01_ROT_CLK_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_1_01_ROT_CLK_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_1_01_ROT_CLK_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_2_23_ROT_CLK_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_2_23_ROT_CLK_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_2_23_ROT_CLK_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_2_23_ROT_CLK_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_3_23_ROT_CLK_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_3_23_ROT_CLK_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_3_23_ROT_CLK_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_3_23_ROT_CLK_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_4_4_ROT_CLK_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_4_4_ROT_CLK_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_4_4_ROT_CLK_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_4_4_ROT_CLK_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_0_01_ROT_CLK_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_0_01_ROT_CLK_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_0_01_ROT_CLK_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_0_01_ROT_CLK_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_1_01_ROT_CLK_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_1_01_ROT_CLK_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_1_01_ROT_CLK_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_1_01_ROT_CLK_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_2_23_ROT_CLK_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_2_23_ROT_CLK_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_2_23_ROT_CLK_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_2_23_ROT_CLK_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_3_23_ROT_CLK_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_3_23_ROT_CLK_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_3_23_ROT_CLK_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_3_23_ROT_CLK_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_4_4_ROT_CLK_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_4_4_ROT_CLK_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_4_4_ROT_CLK_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_4_4_ROT_CLK_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_0_01_ROT_CLK_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_0_01_ROT_CLK_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_0_01_ROT_CLK_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_0_01_ROT_CLK_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_1_01_ROT_CLK_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_1_01_ROT_CLK_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_1_01_ROT_CLK_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_1_01_ROT_CLK_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_2_23_ROT_CLK_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_2_23_ROT_CLK_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_2_23_ROT_CLK_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_2_23_ROT_CLK_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_3_23_ROT_CLK_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_3_23_ROT_CLK_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_3_23_ROT_CLK_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_3_23_ROT_CLK_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_4_4_ROT_CLK_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_4_4_ROT_CLK_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_4_4_ROT_CLK_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_4_4_ROT_CLK_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_0_01_ROT_CLK_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_0_01_ROT_CLK_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_0_01_ROT_CLK_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_0_01_ROT_CLK_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_1_01_ROT_CLK_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_1_01_ROT_CLK_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_1_01_ROT_CLK_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_1_01_ROT_CLK_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_2_23_ROT_CLK_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_2_23_ROT_CLK_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_2_23_ROT_CLK_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_2_23_ROT_CLK_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_3_23_ROT_CLK_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_3_23_ROT_CLK_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_3_23_ROT_CLK_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_3_23_ROT_CLK_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_4_4_ROT_CLK_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_4_4_ROT_CLK_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_4_4_ROT_CLK_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_4_4_ROT_CLK_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_0_01_ROT_CLK_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_0_01_ROT_CLK_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_0_01_ROT_CLK_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_0_01_ROT_CLK_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_1_01_ROT_CLK_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_1_01_ROT_CLK_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_1_01_ROT_CLK_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_1_01_ROT_CLK_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_2_23_ROT_CLK_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_2_23_ROT_CLK_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_2_23_ROT_CLK_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_2_23_ROT_CLK_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_3_23_ROT_CLK_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_3_23_ROT_CLK_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_3_23_ROT_CLK_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_3_23_ROT_CLK_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_4_4_ROT_CLK_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_4_4_ROT_CLK_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_4_4_ROT_CLK_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_4_4_ROT_CLK_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_0_01_ROT_CLK_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_0_01_ROT_CLK_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_0_01_ROT_CLK_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_0_01_ROT_CLK_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_1_01_ROT_CLK_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_1_01_ROT_CLK_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_1_01_ROT_CLK_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_1_01_ROT_CLK_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_2_23_ROT_CLK_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_2_23_ROT_CLK_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_2_23_ROT_CLK_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_2_23_ROT_CLK_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_3_23_ROT_CLK_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_3_23_ROT_CLK_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_3_23_ROT_CLK_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_3_23_ROT_CLK_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_4_4_ROT_CLK_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_4_4_ROT_CLK_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_4_4_ROT_CLK_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_4_4_ROT_CLK_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P0_0_01_16_23 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P0_0_01_16_23_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P0_1_01_16_23 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P0_1_01_16_23_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P0_2_23_16_23 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P0_2_23_16_23_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P0_3_23_16_23 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P0_3_23_16_23_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P0_4_4_16_23 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP0_P0_4_4_16_23_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P0_0_01_16_23 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P0_0_01_16_23_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P0_1_01_16_23 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P0_1_01_16_23_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P0_2_23_16_23 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P0_2_23_16_23_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P0_3_23_16_23 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P0_3_23_16_23_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P0_4_4_16_23 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP1_P0_4_4_16_23_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P0_0_01_16_23 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P0_0_01_16_23_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P0_1_01_16_23 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P0_1_01_16_23_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P0_2_23_16_23 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P0_2_23_16_23_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P0_3_23_16_23 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P0_3_23_16_23_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P0_4_4_16_23 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP2_P0_4_4_16_23_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P0_0_01_16_23 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P0_0_01_16_23_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P0_1_01_16_23 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P0_1_01_16_23_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P0_2_23_16_23 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P0_2_23_16_23_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P0_3_23_16_23 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P0_3_23_16_23_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P0_4_4_16_23 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_BIT_DISABLE_RP3_P0_4_4_16_23_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_0_01_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_0_01_N0_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_0_01_N1 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_0_01_N1_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_0_01_N2 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_0_01_N2_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_0_01_N3 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_0_01_N3_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_1_01_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_1_01_N0_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_1_01_N1 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_1_01_N1_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_1_01_N2 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_1_01_N2_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_1_01_N3 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_1_01_N3_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_2_23_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_2_23_N0_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_2_23_N1 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_2_23_N1_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_2_23_N2 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_2_23_N2_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_2_23_N3 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_2_23_N3_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_3_23_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_3_23_N0_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_3_23_N1 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_3_23_N1_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_3_23_N2 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_3_23_N2_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_3_23_N3 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_3_23_N3_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_4_4_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_4_4_N0_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_4_4_N1 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_4_4_N1_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_4_4_N2 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_4_4_N2_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_4_4_N3 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_4_4_N3_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_0_01_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_0_01_N0_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_0_01_N1 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_0_01_N1_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_0_01_N2 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_0_01_N2_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_0_01_N3 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_0_01_N3_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_1_01_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_1_01_N0_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_1_01_N1 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_1_01_N1_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_1_01_N2 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_1_01_N2_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_1_01_N3 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_1_01_N3_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_2_23_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_2_23_N0_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_2_23_N1 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_2_23_N1_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_2_23_N2 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_2_23_N2_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_2_23_N3 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_2_23_N3_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_3_23_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_3_23_N0_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_3_23_N1 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_3_23_N1_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_3_23_N2 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_3_23_N2_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_3_23_N3 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_3_23_N3_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_4_4_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_4_4_N0_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_4_4_N1 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_4_4_N1_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_4_4_N2 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_4_4_N2_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_4_4_N3 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_4_4_N3_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_0_01_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_0_01_N0_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_0_01_N1 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_0_01_N1_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_0_01_N2 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_0_01_N2_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_0_01_N3 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_0_01_N3_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_1_01_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_1_01_N0_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_1_01_N1 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_1_01_N1_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_1_01_N2 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_1_01_N2_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_1_01_N3 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_1_01_N3_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_2_23_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_2_23_N0_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_2_23_N1 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_2_23_N1_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_2_23_N2 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_2_23_N2_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_2_23_N3 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_2_23_N3_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_3_23_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_3_23_N0_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_3_23_N1 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_3_23_N1_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_3_23_N2 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_3_23_N2_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_3_23_N3 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_3_23_N3_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_4_4_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_4_4_N0_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_4_4_N1 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_4_4_N1_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_4_4_N2 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_4_4_N2_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_4_4_N3 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_4_4_N3_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_0_01_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_0_01_N0_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_0_01_N1 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_0_01_N1_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_0_01_N2 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_0_01_N2_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_0_01_N3 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_0_01_N3_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_1_01_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_1_01_N0_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_1_01_N1 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_1_01_N1_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_1_01_N2 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_1_01_N2_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_1_01_N3 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_1_01_N3_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_2_23_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_2_23_N0_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_2_23_N1 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_2_23_N1_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_2_23_N2 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_2_23_N2_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_2_23_N3 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_2_23_N3_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_3_23_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_3_23_N0_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_3_23_N1 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_3_23_N1_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_3_23_N2 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_3_23_N2_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_3_23_N3 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_3_23_N3_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_4_4_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_4_4_N0_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_4_4_N1 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_4_4_N1_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_4_4_N2 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_4_4_N2_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_4_4_N3 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_4_4_N3_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT0_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT0_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT1_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT1 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT1_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT2_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT2 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT2_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT3_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT3 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT3_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_DQSCLK_SELECT0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_DQSCLK_SELECT0_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_RDCLK_SELECT0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_RDCLK_SELECT0_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_DQSCLK_SELECT1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_DQSCLK_SELECT1_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_RDCLK_SELECT1 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_RDCLK_SELECT1_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_DQSCLK_SELECT2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_DQSCLK_SELECT2_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_RDCLK_SELECT2 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_RDCLK_SELECT2_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_DQSCLK_SELECT3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_DQSCLK_SELECT3_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_RDCLK_SELECT3 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_RDCLK_SELECT3_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_DQSCLK_SELECT0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_DQSCLK_SELECT0_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_RDCLK_SELECT0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_RDCLK_SELECT0_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_DQSCLK_SELECT1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_DQSCLK_SELECT1_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_RDCLK_SELECT1 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_RDCLK_SELECT1_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_DQSCLK_SELECT2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_DQSCLK_SELECT2_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_RDCLK_SELECT2 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_RDCLK_SELECT2_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_DQSCLK_SELECT3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_DQSCLK_SELECT3_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_RDCLK_SELECT3 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_RDCLK_SELECT3_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_DQSCLK_SELECT0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_DQSCLK_SELECT0_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_RDCLK_SELECT0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_RDCLK_SELECT0_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_DQSCLK_SELECT1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_DQSCLK_SELECT1_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_RDCLK_SELECT1 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_RDCLK_SELECT1_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_DQSCLK_SELECT2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_DQSCLK_SELECT2_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_RDCLK_SELECT2 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_RDCLK_SELECT2_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_DQSCLK_SELECT3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_DQSCLK_SELECT3_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_RDCLK_SELECT3 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_RDCLK_SELECT3_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_DQSCLK_SELECT0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_DQSCLK_SELECT0_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_RDCLK_SELECT0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_RDCLK_SELECT0_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_DQSCLK_SELECT1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_DQSCLK_SELECT1_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_RDCLK_SELECT1 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_RDCLK_SELECT1_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_DQSCLK_SELECT2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_DQSCLK_SELECT2_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_RDCLK_SELECT2 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_RDCLK_SELECT2_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_DQSCLK_SELECT3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_DQSCLK_SELECT3_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_RDCLK_SELECT3 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_RDCLK_SELECT3_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_DQSCLK_SELECT0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_DQSCLK_SELECT0_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_RDCLK_SELECT0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_RDCLK_SELECT0_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_DQSCLK_SELECT1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_DQSCLK_SELECT1_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_RDCLK_SELECT1 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_RDCLK_SELECT1_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_DQSCLK_SELECT2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_DQSCLK_SELECT2_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_RDCLK_SELECT2 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_RDCLK_SELECT2_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_DQSCLK_SELECT3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_DQSCLK_SELECT3_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_RDCLK_SELECT3 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_RDCLK_SELECT3_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_DQSCLK_SELECT0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_DQSCLK_SELECT0_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_RDCLK_SELECT0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_RDCLK_SELECT0_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_DQSCLK_SELECT1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_DQSCLK_SELECT1_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_RDCLK_SELECT1 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_RDCLK_SELECT1_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_DQSCLK_SELECT2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_DQSCLK_SELECT2_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_RDCLK_SELECT2 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_RDCLK_SELECT2_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_DQSCLK_SELECT3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_DQSCLK_SELECT3_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_RDCLK_SELECT3 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_RDCLK_SELECT3_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_DQSCLK_SELECT0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_DQSCLK_SELECT0_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_RDCLK_SELECT0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_RDCLK_SELECT0_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_DQSCLK_SELECT1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_DQSCLK_SELECT1_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_RDCLK_SELECT1 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_RDCLK_SELECT1_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_DQSCLK_SELECT2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_DQSCLK_SELECT2_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_RDCLK_SELECT2 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_RDCLK_SELECT2_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_DQSCLK_SELECT3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_DQSCLK_SELECT3_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_RDCLK_SELECT3 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_RDCLK_SELECT3_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_DQSCLK_SELECT0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_DQSCLK_SELECT0_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_RDCLK_SELECT0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_RDCLK_SELECT0_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_DQSCLK_SELECT1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_DQSCLK_SELECT1_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_RDCLK_SELECT1 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_RDCLK_SELECT1_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_DQSCLK_SELECT2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_DQSCLK_SELECT2_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_RDCLK_SELECT2 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_RDCLK_SELECT2_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_DQSCLK_SELECT3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_DQSCLK_SELECT3_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_RDCLK_SELECT3 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_RDCLK_SELECT3_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_DQSCLK_SELECT0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_DQSCLK_SELECT0_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_RDCLK_SELECT0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_RDCLK_SELECT0_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_DQSCLK_SELECT1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_DQSCLK_SELECT1_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_RDCLK_SELECT1 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_RDCLK_SELECT1_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_DQSCLK_SELECT2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_DQSCLK_SELECT2_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_RDCLK_SELECT2 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_RDCLK_SELECT2_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_DQSCLK_SELECT3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_DQSCLK_SELECT3_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_RDCLK_SELECT3 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_RDCLK_SELECT3_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_DQSCLK_SELECT0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_DQSCLK_SELECT0_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_RDCLK_SELECT0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_RDCLK_SELECT0_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_DQSCLK_SELECT1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_DQSCLK_SELECT1_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_RDCLK_SELECT1 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_RDCLK_SELECT1_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_DQSCLK_SELECT2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_DQSCLK_SELECT2_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_RDCLK_SELECT2 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_RDCLK_SELECT2_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_DQSCLK_SELECT3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_DQSCLK_SELECT3_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_RDCLK_SELECT3 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_RDCLK_SELECT3_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_DQSCLK_SELECT0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_DQSCLK_SELECT0_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_RDCLK_SELECT0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_RDCLK_SELECT0_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_DQSCLK_SELECT1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_DQSCLK_SELECT1_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_RDCLK_SELECT1 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_RDCLK_SELECT1_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_DQSCLK_SELECT2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_DQSCLK_SELECT2_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_RDCLK_SELECT2 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_RDCLK_SELECT2_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_DQSCLK_SELECT3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_DQSCLK_SELECT3_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_RDCLK_SELECT3 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_RDCLK_SELECT3_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_DQSCLK_SELECT0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_DQSCLK_SELECT0_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_RDCLK_SELECT0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_RDCLK_SELECT0_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_DQSCLK_SELECT1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_DQSCLK_SELECT1_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_RDCLK_SELECT1 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_RDCLK_SELECT1_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_DQSCLK_SELECT2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_DQSCLK_SELECT2_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_RDCLK_SELECT2 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_RDCLK_SELECT2_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_DQSCLK_SELECT3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_DQSCLK_SELECT3_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_RDCLK_SELECT3 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_RDCLK_SELECT3_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_DQSCLK_SELECT0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_DQSCLK_SELECT0_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_RDCLK_SELECT0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_RDCLK_SELECT0_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_DQSCLK_SELECT1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_DQSCLK_SELECT1_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_RDCLK_SELECT1 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_RDCLK_SELECT1_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_DQSCLK_SELECT2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_DQSCLK_SELECT2_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_RDCLK_SELECT2 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_RDCLK_SELECT2_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_DQSCLK_SELECT3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_DQSCLK_SELECT3_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_RDCLK_SELECT3 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_RDCLK_SELECT3_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_DQSCLK_SELECT0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_DQSCLK_SELECT0_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_RDCLK_SELECT0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_RDCLK_SELECT0_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_DQSCLK_SELECT1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_DQSCLK_SELECT1_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_RDCLK_SELECT1 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_RDCLK_SELECT1_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_DQSCLK_SELECT2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_DQSCLK_SELECT2_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_RDCLK_SELECT2 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_RDCLK_SELECT2_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_DQSCLK_SELECT3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_DQSCLK_SELECT3_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_RDCLK_SELECT3 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_RDCLK_SELECT3_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_DQSCLK_SELECT0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_DQSCLK_SELECT0_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_RDCLK_SELECT0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_RDCLK_SELECT0_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_DQSCLK_SELECT1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_DQSCLK_SELECT1_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_RDCLK_SELECT1 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_RDCLK_SELECT1_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_DQSCLK_SELECT2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_DQSCLK_SELECT2_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_RDCLK_SELECT2 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_RDCLK_SELECT2_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_DQSCLK_SELECT3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_DQSCLK_SELECT3_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_RDCLK_SELECT3 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_RDCLK_SELECT3_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_DQSCLK_SELECT0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_DQSCLK_SELECT0_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_RDCLK_SELECT0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_RDCLK_SELECT0_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_DQSCLK_SELECT1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_DQSCLK_SELECT1_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_RDCLK_SELECT1 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_RDCLK_SELECT1_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_DQSCLK_SELECT2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_DQSCLK_SELECT2_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_RDCLK_SELECT2 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_RDCLK_SELECT2_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_DQSCLK_SELECT3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_DQSCLK_SELECT3_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_RDCLK_SELECT3 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_RDCLK_SELECT3_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_DQSCLK_SELECT0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_DQSCLK_SELECT0_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_RDCLK_SELECT0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_RDCLK_SELECT0_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_DQSCLK_SELECT1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_DQSCLK_SELECT1_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_RDCLK_SELECT1 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_RDCLK_SELECT1_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_DQSCLK_SELECT2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_DQSCLK_SELECT2_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_RDCLK_SELECT2 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_RDCLK_SELECT2_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_DQSCLK_SELECT3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_DQSCLK_SELECT3_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_RDCLK_SELECT3 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_RDCLK_SELECT3_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_DQSCLK_SELECT0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_DQSCLK_SELECT0_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_RDCLK_SELECT0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_RDCLK_SELECT0_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_DQSCLK_SELECT1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_DQSCLK_SELECT1_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_RDCLK_SELECT1 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_RDCLK_SELECT1_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_DQSCLK_SELECT2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_DQSCLK_SELECT2_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_RDCLK_SELECT2 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_RDCLK_SELECT2_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_DQSCLK_SELECT3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_DQSCLK_SELECT3_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_RDCLK_SELECT3 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_RDCLK_SELECT3_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_DQSCLK_SELECT0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_DQSCLK_SELECT0_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_RDCLK_SELECT0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_RDCLK_SELECT0_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_DQSCLK_SELECT1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_DQSCLK_SELECT1_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_RDCLK_SELECT1 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_RDCLK_SELECT1_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_DQSCLK_SELECT2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_DQSCLK_SELECT2_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_RDCLK_SELECT2 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_RDCLK_SELECT2_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_DQSCLK_SELECT3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_DQSCLK_SELECT3_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_RDCLK_SELECT3 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_RDCLK_SELECT3_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P0_0_01_0_15 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P0_0_01_0_15_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P0_1_01_0_15 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P0_1_01_0_15_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P0_2_23_0_15 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P0_2_23_0_15_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P0_3_23_0_15 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P0_3_23_0_15_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P0_4_4_0_15 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP0_P0_4_4_0_15_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P0_0_01_0_15 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P0_0_01_0_15_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P0_1_01_0_15 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P0_1_01_0_15_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P0_2_23_0_15 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P0_2_23_0_15_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P0_3_23_0_15 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P0_3_23_0_15_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P0_4_4_0_15 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP1_P0_4_4_0_15_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P0_0_01_0_15 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P0_0_01_0_15_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P0_1_01_0_15 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P0_1_01_0_15_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P0_2_23_0_15 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P0_2_23_0_15_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P0_3_23_0_15 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P0_3_23_0_15_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P0_4_4_0_15 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP2_P0_4_4_0_15_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P0_0_01_0_15 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P0_0_01_0_15_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P0_1_01_0_15 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P0_1_01_0_15_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P0_2_23_0_15 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P0_2_23_0_15_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P0_3_23_0_15 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P0_3_23_0_15_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P0_4_4_0_15 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_DISABLE_RP3_P0_4_4_0_15_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_ENABLE0_P0_0_01_DATA_ENABLE_15 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_ENABLE0_P0_0_01_DATA_ENABLE_15_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_ENABLE0_P0_1_01_DATA_ENABLE_0_15 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_ENABLE0_P0_1_01_DATA_ENABLE_0_15_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_ENABLE0_P0_2_23_DATA_ENABLE_0_15 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_ENABLE0_P0_2_23_DATA_ENABLE_0_15_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_ENABLE0_P0_3_23_DATA_ENABLE_0_15 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_ENABLE0_P0_3_23_DATA_ENABLE_0_15_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_ENABLE0_P0_4_4_DATA_ENABLE_0_15 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_BIT_ENABLE0_P0_4_4_DATA_ENABLE_0_15_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P0_0_01_VALUE_15 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P0_0_01_VALUE_15_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P0_1_01_VALUE_0_15 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P0_1_01_VALUE_0_15_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P0_2_23_VALUE_0_15 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P0_2_23_VALUE_0_15_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P0_3_23_VALUE_0_15 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P0_3_23_VALUE_0_15_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P0_4_4_VALUE_0_15 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_FORCE_OUTPUTS_P0_4_4_VALUE_0_15_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_0_01_N0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_0_01_N0_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_0_01_N1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_0_01_N1_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_0_01_N2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_0_01_N2_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_0_01_N3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_0_01_N3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_1_01_N0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_1_01_N0_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_1_01_N1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_1_01_N1_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_1_01_N2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_1_01_N2_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_1_01_N3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_1_01_N3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_2_23_N0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_2_23_N0_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_2_23_N1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_2_23_N1_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_2_23_N2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_2_23_N2_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_2_23_N3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_2_23_N3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_3_23_N0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_3_23_N0_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_3_23_N1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_3_23_N1_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_3_23_N2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_3_23_N2_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_3_23_N3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_3_23_N3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_4_4_N0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_4_4_N0_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_4_4_N1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_4_4_N1_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_4_4_N2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_4_4_N2_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_4_4_N3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_4_4_N3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_0_01_N0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_0_01_N0_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_0_01_N1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_0_01_N1_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_0_01_N2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_0_01_N2_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_0_01_N3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_0_01_N3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_1_01_N0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_1_01_N0_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_1_01_N1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_1_01_N1_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_1_01_N2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_1_01_N2_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_1_01_N3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_1_01_N3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_2_23_N0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_2_23_N0_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_2_23_N1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_2_23_N1_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_2_23_N2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_2_23_N2_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_2_23_N3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_2_23_N3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_3_23_N0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_3_23_N0_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_3_23_N1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_3_23_N1_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_3_23_N2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_3_23_N2_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_3_23_N3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_3_23_N3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_4_4_N0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_4_4_N0_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_4_4_N1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_4_4_N1_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_4_4_N2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_4_4_N2_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_4_4_N3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_4_4_N3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_0_01_N0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_0_01_N0_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_0_01_N1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_0_01_N1_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_0_01_N2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_0_01_N2_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_0_01_N3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_0_01_N3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_1_01_N0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_1_01_N0_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_1_01_N1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_1_01_N1_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_1_01_N2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_1_01_N2_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_1_01_N3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_1_01_N3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_2_23_N0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_2_23_N0_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_2_23_N1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_2_23_N1_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_2_23_N2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_2_23_N2_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_2_23_N3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_2_23_N3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_3_23_N0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_3_23_N0_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_3_23_N1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_3_23_N1_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_3_23_N2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_3_23_N2_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_3_23_N3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_3_23_N3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_4_4_N0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_4_4_N0_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_4_4_N1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_4_4_N1_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_4_4_N2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_4_4_N2_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_4_4_N3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_4_4_N3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_0_01_N0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_0_01_N0_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_0_01_N1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_0_01_N1_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_0_01_N2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_0_01_N2_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_0_01_N3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_0_01_N3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_1_01_N0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_1_01_N0_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_1_01_N1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_1_01_N1_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_1_01_N2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_1_01_N2_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_1_01_N3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_1_01_N3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_2_23_N0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_2_23_N0_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_2_23_N1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_2_23_N1_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_2_23_N2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_2_23_N2_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_2_23_N3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_2_23_N3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_3_23_N0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_3_23_N0_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_3_23_N1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_3_23_N1_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_3_23_N2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_3_23_N2_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_3_23_N3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_3_23_N3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_4_4_N0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_4_4_N0_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_4_4_N1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_4_4_N1_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_4_4_N2 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_4_4_N2_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_4_4_N3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_4_4_N3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_0_01_DD2_BLUE_EXTEND_RANGE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_0_01_DD2_BLUE_EXTEND_RANGE_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_0_01_MIN_RD_EYE_SIZE = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_0_01_MIN_RD_EYE_SIZE_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_0_01_DD2_SPARE_L2SFF_CG_DISABLE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_0_01_DD2_PERRDCTR_FIX_DISABLE = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_0_01_MAX_DQS = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_0_01_MAX_DQS_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_1_01_DD2_BLUE_EXTEND_RANGE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_1_01_DD2_BLUE_EXTEND_RANGE_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_1_01_MIN_RD_EYE_SIZE = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_1_01_MIN_RD_EYE_SIZE_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_1_01_DD2_SPARE_L2SFF_CG_DISABLE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_1_01_DD2_PERRDCTR_FIX_DISABLE = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_1_01_MAX_DQS = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_1_01_MAX_DQS_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_2_23_DD2_BLUE_EXTEND_RANGE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_2_23_DD2_BLUE_EXTEND_RANGE_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_2_23_MIN_RD_EYE_SIZE = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_2_23_MIN_RD_EYE_SIZE_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_2_23_DD2_SPARE_L2SFF_CG_DISABLE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_2_23_DD2_PERRDCTR_FIX_DISABLE = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_2_23_MAX_DQS = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_2_23_MAX_DQS_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_3_23_DD2_BLUE_EXTEND_RANGE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_3_23_DD2_BLUE_EXTEND_RANGE_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_3_23_MIN_RD_EYE_SIZE = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_3_23_MIN_RD_EYE_SIZE_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_3_23_DD2_SPARE_L2SFF_CG_DISABLE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_3_23_DD2_PERRDCTR_FIX_DISABLE = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_3_23_MAX_DQS = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_3_23_MAX_DQS_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_4_4_DD2_BLUE_EXTEND_RANGE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_4_4_DD2_BLUE_EXTEND_RANGE_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_4_4_MIN_RD_EYE_SIZE = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_4_4_MIN_RD_EYE_SIZE_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_4_4_DD2_SPARE_L2SFF_CG_DISABLE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_4_4_DD2_PERRDCTR_FIX_DISABLE = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_4_4_MAX_DQS = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_4_4_MAX_DQS_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_0_01_ROT_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_0_01_ROT_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_0_01_ROT_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_0_01_ROT_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_1_01_ROT_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_1_01_ROT_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_1_01_ROT_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_1_01_ROT_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_2_23_ROT_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_2_23_ROT_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_2_23_ROT_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_2_23_ROT_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_3_23_ROT_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_3_23_ROT_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_3_23_ROT_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_3_23_ROT_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_4_4_ROT_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_4_4_ROT_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_4_4_ROT_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_4_4_ROT_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_0_01_ROT_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_0_01_ROT_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_0_01_ROT_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_0_01_ROT_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_1_01_ROT_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_1_01_ROT_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_1_01_ROT_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_1_01_ROT_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_2_23_ROT_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_2_23_ROT_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_2_23_ROT_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_2_23_ROT_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_3_23_ROT_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_3_23_ROT_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_3_23_ROT_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_3_23_ROT_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_4_4_ROT_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_4_4_ROT_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_4_4_ROT_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_4_4_ROT_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_0_01_ROT_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_0_01_ROT_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_0_01_ROT_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_0_01_ROT_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_1_01_ROT_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_1_01_ROT_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_1_01_ROT_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_1_01_ROT_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_2_23_ROT_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_2_23_ROT_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_2_23_ROT_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_2_23_ROT_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_3_23_ROT_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_3_23_ROT_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_3_23_ROT_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_3_23_ROT_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_4_4_ROT_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_4_4_ROT_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_4_4_ROT_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_4_4_ROT_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_0_01_ROT_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_0_01_ROT_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_0_01_ROT_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_0_01_ROT_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_1_01_ROT_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_1_01_ROT_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_1_01_ROT_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_1_01_ROT_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_2_23_ROT_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_2_23_ROT_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_2_23_ROT_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_2_23_ROT_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_3_23_ROT_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_3_23_ROT_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_3_23_ROT_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_3_23_ROT_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_4_4_ROT_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_4_4_ROT_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_4_4_ROT_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_4_4_ROT_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_0_01_ROT_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_0_01_ROT_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_0_01_ROT_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_0_01_ROT_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_1_01_ROT_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_1_01_ROT_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_1_01_ROT_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_1_01_ROT_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_2_23_ROT_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_2_23_ROT_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_2_23_ROT_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_2_23_ROT_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_3_23_ROT_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_3_23_ROT_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_3_23_ROT_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_3_23_ROT_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_4_4_ROT_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_4_4_ROT_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_4_4_ROT_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_4_4_ROT_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_0_01_ROT_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_0_01_ROT_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_0_01_ROT_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_0_01_ROT_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_1_01_ROT_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_1_01_ROT_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_1_01_ROT_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_1_01_ROT_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_2_23_ROT_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_2_23_ROT_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_2_23_ROT_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_2_23_ROT_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_3_23_ROT_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_3_23_ROT_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_3_23_ROT_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_3_23_ROT_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_4_4_ROT_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_4_4_ROT_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_4_4_ROT_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_4_4_ROT_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_0_01_ROT_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_0_01_ROT_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_0_01_ROT_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_0_01_ROT_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_1_01_ROT_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_1_01_ROT_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_1_01_ROT_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_1_01_ROT_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_2_23_ROT_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_2_23_ROT_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_2_23_ROT_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_2_23_ROT_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_3_23_ROT_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_3_23_ROT_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_3_23_ROT_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_3_23_ROT_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_4_4_ROT_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_4_4_ROT_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_4_4_ROT_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_4_4_ROT_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_0_01_ROT_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_0_01_ROT_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_0_01_ROT_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_0_01_ROT_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_1_01_ROT_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_1_01_ROT_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_1_01_ROT_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_1_01_ROT_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_2_23_ROT_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_2_23_ROT_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_2_23_ROT_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_2_23_ROT_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_3_23_ROT_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_3_23_ROT_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_3_23_ROT_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_3_23_ROT_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_4_4_ROT_N0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_4_4_ROT_N0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_4_4_ROT_N1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_4_4_ROT_N1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_0_01_STRENGTH = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_0_01_STRENGTH_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_0_01_DD2_RESET_READ_FIX_DISABLE = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_1_01_STRENGTH = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_1_01_STRENGTH_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_1_01_DD2_RESET_READ_FIX_DISABLE = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_2_23_STRENGTH = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_2_23_STRENGTH_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_2_23_DD2_RESET_READ_FIX_DISABLE = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_3_23_STRENGTH = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_3_23_STRENGTH_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_3_23_DD2_RESET_READ_FIX_DISABLE = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_4_4_STRENGTH = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_4_4_STRENGTH_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_4_4_DD2_RESET_READ_FIX_DISABLE = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_0_01_EN_N_WR = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_0_01_EN_N_WR_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_0_01_EN_P_WR = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_0_01_EN_P_WR_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_1_01_EN_N_WR = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_1_01_EN_N_WR_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_1_01_EN_P_WR = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_1_01_EN_P_WR_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_2_23_EN_N_WR = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_2_23_EN_N_WR_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_2_23_EN_P_WR = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_2_23_EN_P_WR_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_3_23_EN_N_WR = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_3_23_EN_N_WR_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_3_23_EN_P_WR = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_3_23_EN_P_WR_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_4_4_EN_N_WR = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_4_4_EN_N_WR_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_4_4_EN_P_WR = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_4_4_EN_P_WR_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_0_01_EN_P_WR = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_0_01_EN_P_WR_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_1_01_EN_P_WR = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_1_01_EN_P_WR_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_2_23_EN_P_WR = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_2_23_EN_P_WR_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_3_23_EN_P_WR = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_3_23_EN_P_WR_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_4_4_EN_P_WR = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_4_4_EN_P_WR_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_0_01_SEL_A = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_0_01_SEL_A_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_0_01_SEL_B = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_0_01_SEL_B_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_1_01_SEL_A = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_1_01_SEL_A_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_1_01_SEL_B = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_1_01_SEL_B_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_2_23_SEL_A = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_2_23_SEL_A_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_2_23_SEL_B = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_2_23_SEL_B_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_3_23_SEL_A = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_3_23_SEL_A_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_3_23_SEL_B = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_3_23_SEL_B_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_4_4_SEL_A = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_4_4_SEL_A_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_4_4_SEL_B = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_4_4_SEL_B_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD00 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD00_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD01 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD01_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD02 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD02_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD03 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD03_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD04 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD04_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD05 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD05_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD06 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD06_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD07 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD07_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD00 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD00_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD01 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD01_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD02 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD02_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD03 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD03_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD04 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD04_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD05 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD05_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD06 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD06_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD07 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD07_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD00 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD00_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD01 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD01_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD02 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD02_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD03 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD03_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD04 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD04_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD05 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD05_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD06 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD06_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD07 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD07_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD00 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD00_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD01 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD01_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD02 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD02_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD03 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD03_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD04 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD04_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD05 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD05_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD06 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD06_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD07 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD07_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD00 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD00_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD01 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD01_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD02 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD02_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD03 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD03_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD04 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD04_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD05 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD05_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD06 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD06_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD07 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD07_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD08 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD08_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD09 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD09_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD10 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD10_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD11 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD11_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD12 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD12_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD13 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD13_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD14 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD14_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD15 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD15_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD08 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD08_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD09 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD09_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD10 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD10_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD11 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD11_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD12 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD12_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD13 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD13_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD14 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD14_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD15 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD15_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD08 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD08_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD09 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD09_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD10 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD10_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD11 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD11_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD12 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD12_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD13 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD13_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD14 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD14_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD15 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD15_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD08 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD08_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD09 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD09_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD10 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD10_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD11 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD11_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD12 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD12_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD13 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD13_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD14 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD14_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD15 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD15_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD08 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD08_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD09 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD09_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD10 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD10_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD11 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD11_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD12 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD12_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD13 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD13_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD14 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD14_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD15 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD15_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_0_01_SYSCLK_DQSCLK_OFFSET = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_0_01_SYSCLK_DQSCLK_OFFSET_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_0_01_SYSCLK_RDCLK_OFFSET = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_0_01_SYSCLK_RDCLK_OFFSET_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_1_01_SYSCLK_DQSCLK_OFFSET = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_1_01_SYSCLK_DQSCLK_OFFSET_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_1_01_SYSCLK_RDCLK_OFFSET = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_1_01_SYSCLK_RDCLK_OFFSET_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_2_23_SYSCLK_DQSCLK_OFFSET = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_2_23_SYSCLK_DQSCLK_OFFSET_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_2_23_SYSCLK_RDCLK_OFFSET = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_2_23_SYSCLK_RDCLK_OFFSET_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_3_23_SYSCLK_DQSCLK_OFFSET = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_3_23_SYSCLK_DQSCLK_OFFSET_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_3_23_SYSCLK_RDCLK_OFFSET = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_3_23_SYSCLK_RDCLK_OFFSET_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_4_4_SYSCLK_DQSCLK_OFFSET = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_4_4_SYSCLK_DQSCLK_OFFSET_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_4_4_SYSCLK_RDCLK_OFFSET = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_4_4_SYSCLK_RDCLK_OFFSET_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_0_01_DQS_ALIGN_SM = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_0_01_DQS_ALIGN_SM_LEN = 5 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_0_01_DQS_ALIGN_CNTR = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_0_01_DQS_ALIGN_CNTR_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_0_01_ITERATION_CNTR = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_0_01_ITERATION_CNTR_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_1_01_DQS_ALIGN_SM = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_1_01_DQS_ALIGN_SM_LEN = 5 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_1_01_DQS_ALIGN_CNTR = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_1_01_DQS_ALIGN_CNTR_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_1_01_ITERATION_CNTR = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_1_01_ITERATION_CNTR_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_2_23_DQS_ALIGN_SM = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_2_23_DQS_ALIGN_SM_LEN = 5 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_2_23_DQS_ALIGN_CNTR = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_2_23_DQS_ALIGN_CNTR_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_2_23_ITERATION_CNTR = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_2_23_ITERATION_CNTR_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_3_23_DQS_ALIGN_SM = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_3_23_DQS_ALIGN_SM_LEN = 5 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_3_23_DQS_ALIGN_CNTR = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_3_23_DQS_ALIGN_CNTR_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_3_23_ITERATION_CNTR = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_3_23_ITERATION_CNTR_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_4_4_DQS_ALIGN_SM = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_4_4_DQS_ALIGN_SM_LEN = 5 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_4_4_DQS_ALIGN_CNTR = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_4_4_DQS_ALIGN_CNTR_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_4_4_ITERATION_CNTR = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_4_4_ITERATION_CNTR_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_CALIBRATE_BIT = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_CALIBRATE_BIT_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_DQS_ALIGN_QUAD = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_DQS_ALIGN_QUAD_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_DQS_QUAD_CONFIG = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_DQS_QUAD_CONFIG_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_OPERATE_MODE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_OPERATE_MODE_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_EN_DQS_OFFSET = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_DQS_ALIGN_JITTER = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_DIS_CLK_GATE = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_MAX_DQS_ITER = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_CALIBRATE_BIT = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_CALIBRATE_BIT_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_DQS_ALIGN_QUAD = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_DQS_ALIGN_QUAD_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_DQS_QUAD_CONFIG = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_DQS_QUAD_CONFIG_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_OPERATE_MODE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_OPERATE_MODE_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_EN_DQS_OFFSET = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_DQS_ALIGN_JITTER = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_DIS_CLK_GATE = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_MAX_DQS_ITER = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_CALIBRATE_BIT = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_CALIBRATE_BIT_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_DQS_ALIGN_QUAD = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_DQS_ALIGN_QUAD_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_DQS_QUAD_CONFIG = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_DQS_QUAD_CONFIG_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_OPERATE_MODE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_OPERATE_MODE_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_EN_DQS_OFFSET = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_DQS_ALIGN_JITTER = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_DIS_CLK_GATE = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_MAX_DQS_ITER = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_CALIBRATE_BIT = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_CALIBRATE_BIT_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_DQS_ALIGN_QUAD = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_DQS_ALIGN_QUAD_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_DQS_QUAD_CONFIG = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_DQS_QUAD_CONFIG_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_OPERATE_MODE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_OPERATE_MODE_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_EN_DQS_OFFSET = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_DQS_ALIGN_JITTER = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_DIS_CLK_GATE = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_MAX_DQS_ITER = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_CALIBRATE_BIT = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_CALIBRATE_BIT_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_DQS_ALIGN_QUAD = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_DQS_ALIGN_QUAD_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_DQS_QUAD_CONFIG = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_DQS_QUAD_CONFIG_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_OPERATE_MODE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_OPERATE_MODE_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_EN_DQS_OFFSET = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_DQS_ALIGN_JITTER = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_DIS_CLK_GATE = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_MAX_DQS_ITER = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_0_01_DESIRED_EDGE_CNTR_TARGET_HIGH = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_0_01_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_0_01_DESIRED_EDGE_CNTR_TARGET_LOW = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_0_01_DESIRED_EDGE_CNTR_TARGET_LOW_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_1_01_DESIRED_EDGE_CNTR_TARGET_HIGH = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_1_01_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_1_01_DESIRED_EDGE_CNTR_TARGET_LOW = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_1_01_DESIRED_EDGE_CNTR_TARGET_LOW_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_2_23_DESIRED_EDGE_CNTR_TARGET_HIGH = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_2_23_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_2_23_DESIRED_EDGE_CNTR_TARGET_LOW = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_2_23_DESIRED_EDGE_CNTR_TARGET_LOW_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_3_23_DESIRED_EDGE_CNTR_TARGET_HIGH = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_3_23_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_3_23_DESIRED_EDGE_CNTR_TARGET_LOW = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_3_23_DESIRED_EDGE_CNTR_TARGET_LOW_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_4_4_DESIRED_EDGE_CNTR_TARGET_HIGH = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_4_4_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_4_4_DESIRED_EDGE_CNTR_TARGET_LOW = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_4_4_DESIRED_EDGE_CNTR_TARGET_LOW_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_0_01_DQS_ALIGN_FIX_DIS = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_0_01_CDD2_FIFO_FIX_DIS = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_1_01_DQS_ALIGN_FIX_DIS = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_1_01_CDD2_FIFO_FIX_DIS = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_2_23_DQS_ALIGN_FIX_DIS = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_2_23_CDD2_FIFO_FIX_DIS = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_3_23_DQS_ALIGN_FIX_DIS = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_3_23_CDD2_FIFO_FIX_DIS = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_4_4_DQS_ALIGN_FIX_DIS = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_4_4_CDD2_FIFO_FIX_DIS = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_DYN_POWER_CNTL_EN = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_DYN_MCTERM_CNTL_EN = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_DYN_RX_GATE_CNTL_EN = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_CALGATE_ON = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_PER_CAL_UPDATE_DISABLE = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_DQS_PIPE_FIX_DIS = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_DQS_PIPE_FIX_DIS_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_CDD2_DQS_FIX_DIS = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_DL_FORCE_ON = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_BLFIFO_DIS = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_WTRFL_AVE_DIS = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_PERCAL_PWR_DIS = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_LOOPBACK_FIX_EN = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_LOOPBACK_DLY12 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_CDD2_WTRFL_SYNC_DIS = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_FORCE_FIFO_CAPTURE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_DYN_POWER_CNTL_EN = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_DYN_MCTERM_CNTL_EN = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_DYN_RX_GATE_CNTL_EN = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_CALGATE_ON = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_PER_CAL_UPDATE_DISABLE = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_DQS_PIPE_FIX_DIS = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_DQS_PIPE_FIX_DIS_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_CDD2_DQS_FIX_DIS = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_DL_FORCE_ON = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_BLFIFO_DIS = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_WTRFL_AVE_DIS = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_PERCAL_PWR_DIS = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_LOOPBACK_FIX_EN = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_LOOPBACK_DLY12 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_CDD2_WTRFL_SYNC_DIS = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_FORCE_FIFO_CAPTURE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_DYN_POWER_CNTL_EN = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_DYN_MCTERM_CNTL_EN = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_DYN_RX_GATE_CNTL_EN = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_CALGATE_ON = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_PER_CAL_UPDATE_DISABLE = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_DQS_PIPE_FIX_DIS = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_DQS_PIPE_FIX_DIS_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_CDD2_DQS_FIX_DIS = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_DL_FORCE_ON = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_BLFIFO_DIS = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_WTRFL_AVE_DIS = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_PERCAL_PWR_DIS = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_LOOPBACK_FIX_EN = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_LOOPBACK_DLY12 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_CDD2_WTRFL_SYNC_DIS = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_FORCE_FIFO_CAPTURE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_DYN_POWER_CNTL_EN = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_DYN_MCTERM_CNTL_EN = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_DYN_RX_GATE_CNTL_EN = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_CALGATE_ON = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_PER_CAL_UPDATE_DISABLE = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_DQS_PIPE_FIX_DIS = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_DQS_PIPE_FIX_DIS_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_CDD2_DQS_FIX_DIS = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_DL_FORCE_ON = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_BLFIFO_DIS = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_WTRFL_AVE_DIS = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_PERCAL_PWR_DIS = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_LOOPBACK_FIX_EN = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_LOOPBACK_DLY12 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_CDD2_WTRFL_SYNC_DIS = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_FORCE_FIFO_CAPTURE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_DYN_POWER_CNTL_EN = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_DYN_MCTERM_CNTL_EN = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_DYN_RX_GATE_CNTL_EN = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_CALGATE_ON = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_PER_CAL_UPDATE_DISABLE = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_DQS_PIPE_FIX_DIS = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_DQS_PIPE_FIX_DIS_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_CDD2_DQS_FIX_DIS = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_DL_FORCE_ON = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_BLFIFO_DIS = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_WTRFL_AVE_DIS = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_PERCAL_PWR_DIS = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_LOOPBACK_FIX_EN = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_LOOPBACK_DLY12 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_CDD2_WTRFL_SYNC_DIS = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_FORCE_FIFO_CAPTURE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_NO_EYE_DETECTED_MASK = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_LEADING_EDGE_FOUND_MASK = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_TRAILING_EDGE_FOUND_MASK = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_INCOMPLETE_CAL_N0_MASK = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_INCOMPLETE_CAL_N1_MASK = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_INCOMPLETE_CAL_N2_MASK = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_INCOMPLETE_CAL_N3_MASK = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_COARSE_PATTERN_ERR_N0_MASK = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_COARSE_PATTERN_ERR_N1_MASK = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_COARSE_PATTERN_ERR_N2_MASK = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_COARSE_PATTERN_ERR_N3_MASK = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_EYE_CLIPPING_MASK = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_NO_DQS_MASK = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_NO_LOCK_MASK = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_DRIFT_MASK = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_MIN_EYE_MASK = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_NO_EYE_DETECTED_MASK = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_LEADING_EDGE_FOUND_MASK = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_TRAILING_EDGE_FOUND_MASK = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_INCOMPLETE_CAL_N0_MASK = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_INCOMPLETE_CAL_N1_MASK = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_INCOMPLETE_CAL_N2_MASK = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_INCOMPLETE_CAL_N3_MASK = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_COARSE_PATTERN_ERR_N0_MASK = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_COARSE_PATTERN_ERR_N1_MASK = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_COARSE_PATTERN_ERR_N2_MASK = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_COARSE_PATTERN_ERR_N3_MASK = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_EYE_CLIPPING_MASK = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_NO_DQS_MASK = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_NO_LOCK_MASK = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_DRIFT_MASK = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_MIN_EYE_MASK = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_NO_EYE_DETECTED_MASK = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_LEADING_EDGE_FOUND_MASK = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_TRAILING_EDGE_FOUND_MASK = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_INCOMPLETE_CAL_N0_MASK = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_INCOMPLETE_CAL_N1_MASK = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_INCOMPLETE_CAL_N2_MASK = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_INCOMPLETE_CAL_N3_MASK = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_COARSE_PATTERN_ERR_N0_MASK = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_COARSE_PATTERN_ERR_N1_MASK = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_COARSE_PATTERN_ERR_N2_MASK = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_COARSE_PATTERN_ERR_N3_MASK = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_EYE_CLIPPING_MASK = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_NO_DQS_MASK = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_NO_LOCK_MASK = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_DRIFT_MASK = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_MIN_EYE_MASK = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_NO_EYE_DETECTED_MASK = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_LEADING_EDGE_FOUND_MASK = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_TRAILING_EDGE_FOUND_MASK = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_INCOMPLETE_CAL_N0_MASK = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_INCOMPLETE_CAL_N1_MASK = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_INCOMPLETE_CAL_N2_MASK = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_INCOMPLETE_CAL_N3_MASK = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_COARSE_PATTERN_ERR_N0_MASK = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_COARSE_PATTERN_ERR_N1_MASK = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_COARSE_PATTERN_ERR_N2_MASK = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_COARSE_PATTERN_ERR_N3_MASK = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_EYE_CLIPPING_MASK = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_NO_DQS_MASK = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_NO_LOCK_MASK = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_DRIFT_MASK = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_MIN_EYE_MASK = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_NO_EYE_DETECTED_MASK = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_LEADING_EDGE_FOUND_MASK = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_TRAILING_EDGE_FOUND_MASK = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_INCOMPLETE_CAL_N0_MASK = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_INCOMPLETE_CAL_N1_MASK = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_INCOMPLETE_CAL_N2_MASK = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_INCOMPLETE_CAL_N3_MASK = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_COARSE_PATTERN_ERR_N0_MASK = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_COARSE_PATTERN_ERR_N1_MASK = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_COARSE_PATTERN_ERR_N2_MASK = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_COARSE_PATTERN_ERR_N3_MASK = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_EYE_CLIPPING_MASK = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_NO_DQS_MASK = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_NO_LOCK_MASK = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_DRIFT_MASK = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_MIN_EYE_MASK = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_0_01_LEADING_EDGE_NOT_FOUND_15 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_0_01_LEADING_EDGE_NOT_FOUND_15_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_1_01_LEADING_EDGE_NOT_FOUND_0_15 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_1_01_LEADING_EDGE_NOT_FOUND_0_15_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_2_23_LEADING_EDGE_NOT_FOUND_0_15 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_2_23_LEADING_EDGE_NOT_FOUND_0_15_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_3_23_LEADING_EDGE_NOT_FOUND_0_15 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_3_23_LEADING_EDGE_NOT_FOUND_0_15_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_4_4_LEADING_EDGE_NOT_FOUND_0_15 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_4_4_LEADING_EDGE_NOT_FOUND_0_15_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_0_01_TRAILING_EDGE_NOT_FOUND_15 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_0_01_TRAILING_EDGE_NOT_FOUND_15_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_1_01_TRAILING_EDGE_NOT_FOUND_0_15 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_1_01_TRAILING_EDGE_NOT_FOUND_0_15_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_2_23_TRAILING_EDGE_NOT_FOUND_0_15 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_2_23_TRAILING_EDGE_NOT_FOUND_0_15_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_3_23_TRAILING_EDGE_NOT_FOUND_0_15 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_3_23_TRAILING_EDGE_NOT_FOUND_0_15_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_4_4_TRAILING_EDGE_NOT_FOUND_0_15 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_4_4_TRAILING_EDGE_NOT_FOUND_0_15_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_NO_EYE_DETECTED = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_LEADING_EDGE_NOT_FOUND = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_TRAILING_EDGE_NOT_FOUND = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_INCOMPLETE_CAL_N0 = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_INCOMPLETE_CAL_N1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_INCOMPLETE_CAL_N2 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_INCOMPLETE_CAL_N3 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_COARSE_PATTERN_ERR_N0 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_COARSE_PATTERN_ERR_N1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_COARSE_PATTERN_ERR_N2 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_COARSE_PATTERN_ERR_N3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_EYE_CLIPPING = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_NO_DQS = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_NO_LOCK = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_DRIFT_ERROR = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_MIN_EYE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_NO_EYE_DETECTED = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_LEADING_EDGE_NOT_FOUND = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_TRAILING_EDGE_NOT_FOUND = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_INCOMPLETE_CAL_N0 = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_INCOMPLETE_CAL_N1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_INCOMPLETE_CAL_N2 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_INCOMPLETE_CAL_N3 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_COARSE_PATTERN_ERR_N0 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_COARSE_PATTERN_ERR_N1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_COARSE_PATTERN_ERR_N2 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_COARSE_PATTERN_ERR_N3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_EYE_CLIPPING = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_NO_DQS = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_NO_LOCK = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_DRIFT_ERROR = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_MIN_EYE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_NO_EYE_DETECTED = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_LEADING_EDGE_NOT_FOUND = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_TRAILING_EDGE_NOT_FOUND = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_INCOMPLETE_CAL_N0 = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_INCOMPLETE_CAL_N1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_INCOMPLETE_CAL_N2 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_INCOMPLETE_CAL_N3 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_COARSE_PATTERN_ERR_N0 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_COARSE_PATTERN_ERR_N1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_COARSE_PATTERN_ERR_N2 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_COARSE_PATTERN_ERR_N3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_EYE_CLIPPING = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_NO_DQS = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_NO_LOCK = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_DRIFT_ERROR = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_MIN_EYE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_NO_EYE_DETECTED = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_LEADING_EDGE_NOT_FOUND = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_TRAILING_EDGE_NOT_FOUND = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_INCOMPLETE_CAL_N0 = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_INCOMPLETE_CAL_N1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_INCOMPLETE_CAL_N2 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_INCOMPLETE_CAL_N3 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_COARSE_PATTERN_ERR_N0 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_COARSE_PATTERN_ERR_N1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_COARSE_PATTERN_ERR_N2 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_COARSE_PATTERN_ERR_N3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_EYE_CLIPPING = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_NO_DQS = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_NO_LOCK = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_DRIFT_ERROR = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_MIN_EYE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_NO_EYE_DETECTED = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_LEADING_EDGE_NOT_FOUND = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_TRAILING_EDGE_NOT_FOUND = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_INCOMPLETE_CAL_N0 = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_INCOMPLETE_CAL_N1 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_INCOMPLETE_CAL_N2 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_INCOMPLETE_CAL_N3 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_COARSE_PATTERN_ERR_N0 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_COARSE_PATTERN_ERR_N1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_COARSE_PATTERN_ERR_N2 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_COARSE_PATTERN_ERR_N3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_EYE_CLIPPING = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_NO_DQS = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_NO_LOCK = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_DRIFT_ERROR = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_MIN_EYE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_0_01 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_0_01_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_1_01 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_1_01_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_2_23 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_2_23_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_3_23 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_3_23_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_4_4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_4_4_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_0_01 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_0_01_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_1_01 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_1_01_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_2_23 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_2_23_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_3_23 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_3_23_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_4_4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_4_4_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_0_01_NIB0_EN_FORCE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_0_01_BIT0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_0_01_BIT0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_0_01_NIB1_EN_FORCE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_0_01_BIT1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_0_01_BIT1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_1_01_NIB0_EN_FORCE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_1_01_BIT0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_1_01_BIT0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_1_01_NIB1_EN_FORCE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_1_01_BIT1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_1_01_BIT1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_2_23_NIB0_EN_FORCE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_2_23_BIT0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_2_23_BIT0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_2_23_NIB1_EN_FORCE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_2_23_BIT1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_2_23_BIT1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_3_23_NIB0_EN_FORCE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_3_23_BIT0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_3_23_BIT0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_3_23_NIB1_EN_FORCE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_3_23_BIT1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_3_23_BIT1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_4_4_NIB0_EN_FORCE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_4_4_BIT0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_4_4_BIT0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_4_4_NIB1_EN_FORCE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_4_4_BIT1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_0_P0_4_4_BIT1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_0_01_NIB2_EN_FORCE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_0_01_BIT2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_0_01_BIT2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_0_01_NIB3_EN_FORCE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_0_01_BIT3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_0_01_BIT3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_1_01_NIB2_EN_FORCE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_1_01_BIT2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_1_01_BIT2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_1_01_NIB3_EN_FORCE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_1_01_BIT3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_1_01_BIT3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_2_23_NIB2_EN_FORCE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_2_23_BIT2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_2_23_BIT2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_2_23_NIB3_EN_FORCE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_2_23_BIT3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_2_23_BIT3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_3_23_NIB2_EN_FORCE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_3_23_BIT2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_3_23_BIT2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_3_23_NIB3_EN_FORCE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_3_23_BIT3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_3_23_BIT3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_4_4_NIB2_EN_FORCE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_4_4_BIT2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_4_4_BIT2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_4_4_NIB3_EN_FORCE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_4_4_BIT3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_1_P0_4_4_BIT3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_0_01_BIT4 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_0_01_BIT4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_0_01_BIT5 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_0_01_BIT5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_1_01_BIT4 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_1_01_BIT4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_1_01_BIT5 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_1_01_BIT5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_2_23_BIT4 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_2_23_BIT4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_2_23_BIT5 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_2_23_BIT5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_3_23_BIT4 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_3_23_BIT4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_3_23_BIT5 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_3_23_BIT5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_4_4_BIT4 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_4_4_BIT4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_4_4_BIT5 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_2_P0_4_4_BIT5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_0_01_BIT6 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_0_01_BIT6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_0_01_BIT7 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_0_01_BIT7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_1_01_BIT6 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_1_01_BIT6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_1_01_BIT7 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_1_01_BIT7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_2_23_BIT6 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_2_23_BIT6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_2_23_BIT7 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_2_23_BIT7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_3_23_BIT6 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_3_23_BIT6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_3_23_BIT7 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_3_23_BIT7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_4_4_BIT6 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_4_4_BIT6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_4_4_BIT7 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_3_P0_4_4_BIT7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_0_01_BIT8 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_0_01_BIT8_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_0_01_BIT9 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_0_01_BIT9_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_1_01_BIT8 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_1_01_BIT8_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_1_01_BIT9 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_1_01_BIT9_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_2_23_BIT8 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_2_23_BIT8_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_2_23_BIT9 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_2_23_BIT9_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_3_23_BIT8 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_3_23_BIT8_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_3_23_BIT9 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_3_23_BIT9_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_4_BIT8 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_4_BIT8_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_4_BIT9 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_4_P0_4_BIT9_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_0_01_BIT10 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_0_01_BIT10_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_0_01_BIT11 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_0_01_BIT11_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_1_01_BIT10 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_1_01_BIT10_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_1_01_BIT11 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_1_01_BIT11_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_2_23_BIT10 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_2_23_BIT10_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_2_23_BIT11 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_2_23_BIT11_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_3_23_BIT10 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_3_23_BIT10_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_3_23_BIT11 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_3_23_BIT11_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_4_4_BIT10 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_4_4_BIT10_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_4_4_BIT11 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_5_P0_4_4_BIT11_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_0_01_BIT12 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_0_01_BIT12_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_0_01_BIT13 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_0_01_BIT13_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_1_01_BIT12 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_1_01_BIT12_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_1_01_BIT13 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_1_01_BIT13_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_2_23_BIT12 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_2_23_BIT12_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_2_23_BIT13 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_2_23_BIT13_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_3_23_BIT12 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_3_23_BIT12_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_3_23_BIT13 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_3_23_BIT13_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_4_4_BIT12 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_4_4_BIT12_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_4_4_BIT13 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_6_P0_4_4_BIT13_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_0_01_DD2_PERBIT_RDVREF_DISABLE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_0_01_BIT14 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_0_01_BIT14_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_0_01_BIT15 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_0_01_BIT15_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_1_01_DD2_PERBIT_RDVREF_DISABLE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_1_01_BIT14 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_1_01_BIT14_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_1_01_BIT15 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_1_01_BIT15_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_2_23_DD2_PERBIT_RDVREF_DISABLE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_2_23_BIT14 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_2_23_BIT14_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_2_23_BIT15 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_2_23_BIT15_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_3_23_DD2_PERBIT_RDVREF_DISABLE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_3_23_BIT14 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_3_23_BIT14_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_3_23_BIT15 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_3_23_BIT15_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_4_4_DD2_PERBIT_RDVREF_DISABLE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_4_4_BIT14 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_4_4_BIT14_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_4_4_BIT15 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_4_4_BIT15_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_0_01 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_0_01_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_1_01 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_1_01_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_2_23 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_2_23_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_3_23 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_3_23_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_4_4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_4_4_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD0_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD1_CLK16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD0_CLK18 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD1_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD2_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD3_CLK20 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD2_CLK22 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD3_CLK22 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD0_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD1_CLK16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD0_CLK18 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD1_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD2_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD3_CLK20 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD2_CLK22 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD3_CLK22 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD0_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD1_CLK16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD0_CLK18 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD1_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD2_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD3_CLK20 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD2_CLK22 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD3_CLK22 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD0_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD1_CLK16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD0_CLK18 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD1_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD2_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD3_CLK20 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD2_CLK22 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD3_CLK22 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4_4_QUAD0_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4_4_QUAD1_CLK16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4_4_QUAD0_CLK18 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4_4_QUAD1_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4_4_QUAD2_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4_4_QUAD3_CLK20 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4_4_QUAD2_CLK22 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4_4_QUAD3_CLK22 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD0_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD1_CLK16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD0_CLK18 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD1_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD2_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD3_CLK20 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD2_CLK22 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD3_CLK22 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD0_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD1_CLK16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD0_CLK18 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD1_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD2_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD3_CLK20 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD2_CLK22 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD3_CLK22 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD0_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD1_CLK16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD0_CLK18 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD1_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD2_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD3_CLK20 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD2_CLK22 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD3_CLK22 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD0_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD1_CLK16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD0_CLK18 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD1_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD2_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD3_CLK20 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD2_CLK22 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD3_CLK22 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4_4_QUAD0_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4_4_QUAD1_CLK16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4_4_QUAD0_CLK18 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4_4_QUAD1_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4_4_QUAD2_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4_4_QUAD3_CLK20 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4_4_QUAD2_CLK22 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4_4_QUAD3_CLK22 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD0_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD1_CLK16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD0_CLK18 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD1_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD2_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD3_CLK20 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD2_CLK22 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD3_CLK22 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD0_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD1_CLK16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD0_CLK18 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD1_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD2_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD3_CLK20 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD2_CLK22 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD3_CLK22 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD0_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD1_CLK16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD0_CLK18 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD1_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD2_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD3_CLK20 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD2_CLK22 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD3_CLK22 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD0_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD1_CLK16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD0_CLK18 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD1_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD2_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD3_CLK20 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD2_CLK22 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD3_CLK22 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4_4_QUAD0_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4_4_QUAD1_CLK16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4_4_QUAD0_CLK18 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4_4_QUAD1_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4_4_QUAD2_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4_4_QUAD3_CLK20 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4_4_QUAD2_CLK22 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4_4_QUAD3_CLK22 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD0_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD1_CLK16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD0_CLK18 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD1_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD2_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD3_CLK20 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD2_CLK22 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD3_CLK22 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD0_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD1_CLK16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD0_CLK18 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD1_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD2_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD3_CLK20 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD2_CLK22 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD3_CLK22 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD0_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD1_CLK16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD0_CLK18 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD1_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD2_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD3_CLK20 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD2_CLK22 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD3_CLK22 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD0_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD1_CLK16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD0_CLK18 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD1_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD2_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD3_CLK20 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD2_CLK22 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD3_CLK22 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4_4_QUAD0_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4_4_QUAD1_CLK16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4_4_QUAD0_CLK18 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4_4_QUAD1_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4_4_QUAD2_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4_4_QUAD3_CLK20 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4_4_QUAD2_CLK22 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4_4_QUAD3_CLK22 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_0_01_RD = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_0_01_RD_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_0_01_RD_DELAY1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_0_01_RD_DELAY1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_1_01_RD = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_1_01_RD_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_1_01_RD_DELAY1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_1_01_RD_DELAY1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_2_23_RD = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_2_23_RD_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_2_23_RD_DELAY1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_2_23_RD_DELAY1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_3_23_RD = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_3_23_RD_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_3_23_RD_DELAY1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_3_23_RD_DELAY1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_4_4_RD = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_4_4_RD_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_4_4_RD_DELAY1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_4_4_RD_DELAY1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_0_01_RD_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_0_01_RD_DELAY2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_0_01_RD_DELAY3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_0_01_RD_DELAY3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_1_01_RD_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_1_01_RD_DELAY2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_1_01_RD_DELAY3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_1_01_RD_DELAY3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_2_23_RD_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_2_23_RD_DELAY2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_2_23_RD_DELAY3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_2_23_RD_DELAY3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_3_23_RD_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_3_23_RD_DELAY2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_3_23_RD_DELAY3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_3_23_RD_DELAY3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_4_4_RD_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_4_4_RD_DELAY2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_4_4_RD_DELAY3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_4_4_RD_DELAY3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_0_01_RD_DELAY4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_0_01_RD_DELAY4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_0_01_RD_DELAY5 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_0_01_RD_DELAY5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_1_01_RD_DELAY4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_1_01_RD_DELAY4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_1_01_RD_DELAY5 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_1_01_RD_DELAY5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_2_23_RD_DELAY4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_2_23_RD_DELAY4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_2_23_RD_DELAY5 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_2_23_RD_DELAY5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_3_23_RD_DELAY4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_3_23_RD_DELAY4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_3_23_RD_DELAY5 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_3_23_RD_DELAY5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_4_4_RD_DELAY4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_4_4_RD_DELAY4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_4_4_RD_DELAY5 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_4_4_RD_DELAY5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_0_01_RD_DELAY6 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_0_01_RD_DELAY6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_0_01_RD_DELAY7 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_0_01_RD_DELAY7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_1_01_RD_DELAY6 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_1_01_RD_DELAY6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_1_01_RD_DELAY7 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_1_01_RD_DELAY7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_2_23_RD_DELAY6 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_2_23_RD_DELAY6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_2_23_RD_DELAY7 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_2_23_RD_DELAY7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_3_23_RD_DELAY6 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_3_23_RD_DELAY6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_3_23_RD_DELAY7 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_3_23_RD_DELAY7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_4_4_RD_DELAY6 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_4_4_RD_DELAY6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_4_4_RD_DELAY7 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_4_4_RD_DELAY7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_0_01_RD_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_0_01_RD_DELAY0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_0_01_RD = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_0_01_RD_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_1_01_RD_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_1_01_RD_DELAY0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_1_01_RD = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_1_01_RD_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_2_23_RD_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_2_23_RD_DELAY0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_2_23_RD = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_2_23_RD_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_3_23_RD_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_3_23_RD_DELAY0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_3_23_RD = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_3_23_RD_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_4_4_RD_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_4_4_RD_DELAY0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_4_4_RD = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_4_4_RD_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_0_01_RD_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_0_01_RD_DELAY2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_0_01_RD_DELAY3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_0_01_RD_DELAY3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_1_01_RD_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_1_01_RD_DELAY2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_1_01_RD_DELAY3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_1_01_RD_DELAY3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_2_23_RD_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_2_23_RD_DELAY2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_2_23_RD_DELAY3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_2_23_RD_DELAY3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_3_23_RD_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_3_23_RD_DELAY2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_3_23_RD_DELAY3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_3_23_RD_DELAY3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_4_4_RD_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_4_4_RD_DELAY2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_4_4_RD_DELAY3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_4_4_RD_DELAY3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_0_01_RD_DELAY4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_0_01_RD_DELAY4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_0_01_RD_DELAY5 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_0_01_RD_DELAY5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_1_01_RD_DELAY4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_1_01_RD_DELAY4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_1_01_RD_DELAY5 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_1_01_RD_DELAY5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_2_23_RD_DELAY4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_2_23_RD_DELAY4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_2_23_RD_DELAY5 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_2_23_RD_DELAY5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_3_23_RD_DELAY4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_3_23_RD_DELAY4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_3_23_RD_DELAY5 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_3_23_RD_DELAY5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_4_4_RD_DELAY4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_4_4_RD_DELAY4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_4_4_RD_DELAY5 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_4_4_RD_DELAY5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_0_01_RD_DELAY6 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_0_01_RD_DELAY6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_0_01_RD_DELAY7 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_0_01_RD_DELAY7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_1_01_RD_DELAY6 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_1_01_RD_DELAY6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_1_01_RD_DELAY7 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_1_01_RD_DELAY7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_2_23_RD_DELAY6 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_2_23_RD_DELAY6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_2_23_RD_DELAY7 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_2_23_RD_DELAY7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_3_23_RD_DELAY6 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_3_23_RD_DELAY6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_3_23_RD_DELAY7 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_3_23_RD_DELAY7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_4_4_RD_DELAY6 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_4_4_RD_DELAY6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_4_4_RD_DELAY7 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_4_4_RD_DELAY7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_0_01_RD_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_0_01_RD_DELAY0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_0_01_RD_DELAY1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_0_01_RD_DELAY1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_1_01_RD_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_1_01_RD_DELAY0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_1_01_RD_DELAY1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_1_01_RD_DELAY1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_2_23_RD_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_2_23_RD_DELAY0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_2_23_RD_DELAY1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_2_23_RD_DELAY1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_3_23_RD_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_3_23_RD_DELAY0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_3_23_RD_DELAY1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_3_23_RD_DELAY1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_4_4_RD_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_4_4_RD_DELAY0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_4_4_RD_DELAY1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_4_4_RD_DELAY1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_0_01_RD = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_0_01_RD_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_0_01_RD_DELAY3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_0_01_RD_DELAY3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_1_01_RD = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_1_01_RD_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_1_01_RD_DELAY3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_1_01_RD_DELAY3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_2_23_RD = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_2_23_RD_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_2_23_RD_DELAY3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_2_23_RD_DELAY3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_3_23_RD = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_3_23_RD_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_3_23_RD_DELAY3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_3_23_RD_DELAY3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_4_4_RD = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_4_4_RD_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_4_4_RD_DELAY3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_4_4_RD_DELAY3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_0_01_RD_DELAY4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_0_01_RD_DELAY4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_0_01_RD_DELAY5 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_0_01_RD_DELAY5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_1_01_RD_DELAY4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_1_01_RD_DELAY4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_1_01_RD_DELAY5 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_1_01_RD_DELAY5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_2_23_RD_DELAY4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_2_23_RD_DELAY4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_2_23_RD_DELAY5 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_2_23_RD_DELAY5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_3_23_RD_DELAY4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_3_23_RD_DELAY4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_3_23_RD_DELAY5 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_3_23_RD_DELAY5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_4_4_RD_DELAY4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_4_4_RD_DELAY4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_4_4_RD_DELAY5 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_4_4_RD_DELAY5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_0_01_RD_DELAY6 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_0_01_RD_DELAY6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_0_01_RD_DELAY7 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_0_01_RD_DELAY7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_1_01_RD_DELAY6 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_1_01_RD_DELAY6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_1_01_RD_DELAY7 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_1_01_RD_DELAY7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_2_23_RD_DELAY6 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_2_23_RD_DELAY6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_2_23_RD_DELAY7 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_2_23_RD_DELAY7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_3_23_RD_DELAY6 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_3_23_RD_DELAY6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_3_23_RD_DELAY7 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_3_23_RD_DELAY7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_4_4_RD_DELAY6 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_4_4_RD_DELAY6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_4_4_RD_DELAY7 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_4_4_RD_DELAY7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_0_01_RD_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_0_01_RD_DELAY0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_0_01_RD_DELAY1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_0_01_RD_DELAY1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_1_01_RD_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_1_01_RD_DELAY0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_1_01_RD_DELAY1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_1_01_RD_DELAY1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_2_23_RD_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_2_23_RD_DELAY0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_2_23_RD_DELAY1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_2_23_RD_DELAY1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_3_23_RD_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_3_23_RD_DELAY0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_3_23_RD_DELAY1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_3_23_RD_DELAY1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_4_4_RD_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_4_4_RD_DELAY0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_4_4_RD_DELAY1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_4_4_RD_DELAY1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_0_01_RD_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_0_01_RD_DELAY2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_0_01_RD = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_0_01_RD_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_1_01_RD_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_1_01_RD_DELAY2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_1_01_RD = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_1_01_RD_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_2_23_RD_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_2_23_RD_DELAY2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_2_23_RD = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_2_23_RD_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_3_23_RD_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_3_23_RD_DELAY2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_3_23_RD = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_3_23_RD_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_4_4_RD_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_4_4_RD_DELAY2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_4_4_RD = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_4_4_RD_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_0_01_RD_DELAY4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_0_01_RD_DELAY4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_0_01_RD_DELAY5 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_0_01_RD_DELAY5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_1_01_RD_DELAY4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_1_01_RD_DELAY4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_1_01_RD_DELAY5 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_1_01_RD_DELAY5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_2_23_RD_DELAY4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_2_23_RD_DELAY4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_2_23_RD_DELAY5 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_2_23_RD_DELAY5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_3_23_RD_DELAY4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_3_23_RD_DELAY4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_3_23_RD_DELAY5 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_3_23_RD_DELAY5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_4_4_RD_DELAY4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_4_4_RD_DELAY4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_4_4_RD_DELAY5 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_4_4_RD_DELAY5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_0_01_RD_DELAY6 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_0_01_RD_DELAY6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_0_01_RD_DELAY7 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_0_01_RD_DELAY7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_1_01_RD_DELAY6 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_1_01_RD_DELAY6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_1_01_RD_DELAY7 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_1_01_RD_DELAY7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_2_23_RD_DELAY6 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_2_23_RD_DELAY6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_2_23_RD_DELAY7 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_2_23_RD_DELAY7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_3_23_RD_DELAY6 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_3_23_RD_DELAY6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_3_23_RD_DELAY7 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_3_23_RD_DELAY7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_4_4_RD_DELAY6 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_4_4_RD_DELAY6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_4_4_RD_DELAY7 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_4_4_RD_DELAY7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_0_01_RD_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_0_01_RD_DELAY0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_0_01_RD_DELAY1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_0_01_RD_DELAY1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_1_01_RD_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_1_01_RD_DELAY0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_1_01_RD_DELAY1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_1_01_RD_DELAY1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_2_23_RD_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_2_23_RD_DELAY0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_2_23_RD_DELAY1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_2_23_RD_DELAY1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_3_23_RD_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_3_23_RD_DELAY0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_3_23_RD_DELAY1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_3_23_RD_DELAY1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_4_4_RD_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_4_4_RD_DELAY0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_4_4_RD_DELAY1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_4_4_RD_DELAY1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_0_01_RD_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_0_01_RD_DELAY2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_0_01_RD_DELAY3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_0_01_RD_DELAY3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_1_01_RD_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_1_01_RD_DELAY2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_1_01_RD_DELAY3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_1_01_RD_DELAY3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_2_23_RD_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_2_23_RD_DELAY2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_2_23_RD_DELAY3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_2_23_RD_DELAY3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_3_23_RD_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_3_23_RD_DELAY2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_3_23_RD_DELAY3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_3_23_RD_DELAY3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_4_4_RD_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_4_4_RD_DELAY2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_4_4_RD_DELAY3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_4_4_RD_DELAY3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_0_01_RD = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_0_01_RD_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_0_01_RD_DELAY5 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_0_01_RD_DELAY5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_1_01_RD = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_1_01_RD_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_1_01_RD_DELAY5 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_1_01_RD_DELAY5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_2_23_RD = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_2_23_RD_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_2_23_RD_DELAY5 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_2_23_RD_DELAY5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_3_23_RD = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_3_23_RD_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_3_23_RD_DELAY5 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_3_23_RD_DELAY5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_4_4_RD = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_4_4_RD_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_4_4_RD_DELAY5 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_4_4_RD_DELAY5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_0_01_RD_DELAY6 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_0_01_RD_DELAY6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_0_01_RD_DELAY7 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_0_01_RD_DELAY7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_1_01_RD_DELAY6 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_1_01_RD_DELAY6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_1_01_RD_DELAY7 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_1_01_RD_DELAY7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_2_23_RD_DELAY6 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_2_23_RD_DELAY6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_2_23_RD_DELAY7 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_2_23_RD_DELAY7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_3_23_RD_DELAY6 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_3_23_RD_DELAY6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_3_23_RD_DELAY7 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_3_23_RD_DELAY7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_4_4_RD_DELAY6 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_4_4_RD_DELAY6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_4_4_RD_DELAY7 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_4_4_RD_DELAY7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_0_01_RD_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_0_01_RD_DELAY0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_0_01_RD_DELAY1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_0_01_RD_DELAY1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_1_01_RD_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_1_01_RD_DELAY0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_1_01_RD_DELAY1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_1_01_RD_DELAY1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_2_23_RD_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_2_23_RD_DELAY0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_2_23_RD_DELAY1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_2_23_RD_DELAY1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_3_23_RD_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_3_23_RD_DELAY0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_3_23_RD_DELAY1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_3_23_RD_DELAY1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_4_4_RD_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_4_4_RD_DELAY0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_4_4_RD_DELAY1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_4_4_RD_DELAY1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_0_01_RD_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_0_01_RD_DELAY2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_0_01_RD_DELAY3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_0_01_RD_DELAY3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_1_01_RD_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_1_01_RD_DELAY2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_1_01_RD_DELAY3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_1_01_RD_DELAY3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_2_23_RD_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_2_23_RD_DELAY2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_2_23_RD_DELAY3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_2_23_RD_DELAY3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_3_23_RD_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_3_23_RD_DELAY2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_3_23_RD_DELAY3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_3_23_RD_DELAY3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_4_4_RD_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_4_4_RD_DELAY2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_4_4_RD_DELAY3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_4_4_RD_DELAY3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_0_01_RD_DELAY4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_0_01_RD_DELAY4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_0_01_RD = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_0_01_RD_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_1_01_RD_DELAY4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_1_01_RD_DELAY4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_1_01_RD = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_1_01_RD_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_2_23_RD_DELAY4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_2_23_RD_DELAY4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_2_23_RD = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_2_23_RD_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_3_23_RD_DELAY4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_3_23_RD_DELAY4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_3_23_RD = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_3_23_RD_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_4_4_RD_DELAY4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_4_4_RD_DELAY4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_4_4_RD = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_4_4_RD_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_0_01_RD_DELAY6 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_0_01_RD_DELAY6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_0_01_RD_DELAY7 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_0_01_RD_DELAY7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_1_01_RD_DELAY6 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_1_01_RD_DELAY6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_1_01_RD_DELAY7 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_1_01_RD_DELAY7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_2_23_RD_DELAY6 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_2_23_RD_DELAY6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_2_23_RD_DELAY7 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_2_23_RD_DELAY7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_3_23_RD_DELAY6 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_3_23_RD_DELAY6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_3_23_RD_DELAY7 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_3_23_RD_DELAY7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_4_4_RD_DELAY6 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_4_4_RD_DELAY6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_4_4_RD_DELAY7 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_4_4_RD_DELAY7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_0_01_RD_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_0_01_RD_DELAY0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_0_01_RD_DELAY1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_0_01_RD_DELAY1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_1_01_RD_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_1_01_RD_DELAY0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_1_01_RD_DELAY1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_1_01_RD_DELAY1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_2_23_RD_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_2_23_RD_DELAY0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_2_23_RD_DELAY1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_2_23_RD_DELAY1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_3_23_RD_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_3_23_RD_DELAY0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_3_23_RD_DELAY1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_3_23_RD_DELAY1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_4_4_RD_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_4_4_RD_DELAY0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_4_4_RD_DELAY1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_4_4_RD_DELAY1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_0_01_RD_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_0_01_RD_DELAY2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_0_01_RD_DELAY3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_0_01_RD_DELAY3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_1_01_RD_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_1_01_RD_DELAY2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_1_01_RD_DELAY3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_1_01_RD_DELAY3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_2_23_RD_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_2_23_RD_DELAY2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_2_23_RD_DELAY3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_2_23_RD_DELAY3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_3_23_RD_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_3_23_RD_DELAY2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_3_23_RD_DELAY3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_3_23_RD_DELAY3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_4_4_RD_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_4_4_RD_DELAY2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_4_4_RD_DELAY3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_4_4_RD_DELAY3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_0_01_RD_DELAY4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_0_01_RD_DELAY4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_0_01_RD_DELAY5 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_0_01_RD_DELAY5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_1_01_RD_DELAY4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_1_01_RD_DELAY4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_1_01_RD_DELAY5 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_1_01_RD_DELAY5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_2_23_RD_DELAY4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_2_23_RD_DELAY4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_2_23_RD_DELAY5 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_2_23_RD_DELAY5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_3_23_RD_DELAY4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_3_23_RD_DELAY4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_3_23_RD_DELAY5 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_3_23_RD_DELAY5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_4_4_RD_DELAY4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_4_4_RD_DELAY4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_4_4_RD_DELAY5 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_4_4_RD_DELAY5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_0_01_RD = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_0_01_RD_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_0_01_RD_DELAY7 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_0_01_RD_DELAY7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_1_01_RD = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_1_01_RD_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_1_01_RD_DELAY7 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_1_01_RD_DELAY7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_2_23_RD = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_2_23_RD_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_2_23_RD_DELAY7 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_2_23_RD_DELAY7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_3_23_RD = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_3_23_RD_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_3_23_RD_DELAY7 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_3_23_RD_DELAY7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_4_4_RD = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_4_4_RD_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_4_4_RD_DELAY7 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_4_4_RD_DELAY7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_0_01_RD_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_0_01_RD_DELAY0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_0_01_RD_DELAY1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_0_01_RD_DELAY1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_1_01_RD_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_1_01_RD_DELAY0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_1_01_RD_DELAY1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_1_01_RD_DELAY1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_2_23_RD_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_2_23_RD_DELAY0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_2_23_RD_DELAY1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_2_23_RD_DELAY1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_3_23_RD_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_3_23_RD_DELAY0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_3_23_RD_DELAY1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_3_23_RD_DELAY1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_4_4_RD_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_4_4_RD_DELAY0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_4_4_RD_DELAY1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_4_4_RD_DELAY1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_0_01_RD_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_0_01_RD_DELAY2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_0_01_RD_DELAY3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_0_01_RD_DELAY3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_1_01_RD_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_1_01_RD_DELAY2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_1_01_RD_DELAY3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_1_01_RD_DELAY3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_2_23_RD_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_2_23_RD_DELAY2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_2_23_RD_DELAY3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_2_23_RD_DELAY3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_3_23_RD_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_3_23_RD_DELAY2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_3_23_RD_DELAY3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_3_23_RD_DELAY3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_4_4_RD_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_4_4_RD_DELAY2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_4_4_RD_DELAY3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_4_4_RD_DELAY3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_0_01_RD_DELAY4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_0_01_RD_DELAY4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_0_01_RD_DELAY5 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_0_01_RD_DELAY5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_1_01_RD_DELAY4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_1_01_RD_DELAY4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_1_01_RD_DELAY5 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_1_01_RD_DELAY5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_2_23_RD_DELAY4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_2_23_RD_DELAY4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_2_23_RD_DELAY5 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_2_23_RD_DELAY5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_3_23_RD_DELAY4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_3_23_RD_DELAY4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_3_23_RD_DELAY5 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_3_23_RD_DELAY5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_4_4_RD_DELAY4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_4_4_RD_DELAY4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_4_4_RD_DELAY5 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_4_4_RD_DELAY5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_0_01_RD_DELAY6 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_0_01_RD_DELAY6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_0_01_RD = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_0_01_RD_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_1_01_RD_DELAY6 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_1_01_RD_DELAY6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_1_01_RD = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_1_01_RD_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_2_23_RD_DELAY6 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_2_23_RD_DELAY6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_2_23_RD = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_2_23_RD_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_3_23_RD_DELAY6 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_3_23_RD_DELAY6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_3_23_RD = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_3_23_RD_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_4_4_RD_DELAY6 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_4_4_RD_DELAY6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_4_4_RD = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_4_4_RD_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0_01 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0_01_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0_01_OFFSET1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0_01_OFFSET1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_1_01 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_1_01_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_1_01_OFFSET1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_1_01_OFFSET1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_2_23 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_2_23_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_2_23_OFFSET1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_2_23_OFFSET1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_3_23 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_3_23_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_3_23_OFFSET1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_3_23_OFFSET1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_4_4 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_4_4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_4_4_OFFSET1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_4_4_OFFSET1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_0_01_OFFSET2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_0_01_OFFSET2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_0_01_OFFSET3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_0_01_OFFSET3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_1_01_OFFSET2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_1_01_OFFSET2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_1_01_OFFSET3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_1_01_OFFSET3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_2_23_OFFSET2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_2_23_OFFSET2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_2_23_OFFSET3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_2_23_OFFSET3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_3_23_OFFSET2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_3_23_OFFSET2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_3_23_OFFSET3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_3_23_OFFSET3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_4_4_OFFSET2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_4_4_OFFSET2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_4_4_OFFSET3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_4_4_OFFSET3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_0_01_OFFSET4 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_0_01_OFFSET4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_0_01_OFFSET5 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_0_01_OFFSET5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_1_01_OFFSET4 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_1_01_OFFSET4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_1_01_OFFSET5 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_1_01_OFFSET5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_2_23_OFFSET4 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_2_23_OFFSET4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_2_23_OFFSET5 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_2_23_OFFSET5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_3_23_OFFSET4 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_3_23_OFFSET4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_3_23_OFFSET5 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_3_23_OFFSET5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_4_4_OFFSET4 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_4_4_OFFSET4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_4_4_OFFSET5 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_4_4_OFFSET5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_0_01_OFFSET6 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_0_01_OFFSET6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_0_01_OFFSET7 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_0_01_OFFSET7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_1_01_OFFSET6 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_1_01_OFFSET6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_1_01_OFFSET7 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_1_01_OFFSET7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_2_23_OFFSET6 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_2_23_OFFSET6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_2_23_OFFSET7 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_2_23_OFFSET7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_3_23_OFFSET6 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_3_23_OFFSET6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_3_23_OFFSET7 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_3_23_OFFSET7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_4_4_OFFSET6 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_4_4_OFFSET6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_4_4_OFFSET7 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_4_4_OFFSET7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_0_01_OFFSET0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_0_01_OFFSET0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_0_01 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_0_01_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_1_01_OFFSET0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_1_01_OFFSET0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_1_01 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_1_01_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_2_23_OFFSET0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_2_23_OFFSET0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_2_23 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_2_23_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_3_23_OFFSET0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_3_23_OFFSET0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_3_23 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_3_23_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_4_4_OFFSET0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_4_4_OFFSET0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_4_4 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_4_4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_0_01_OFFSET2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_0_01_OFFSET2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_0_01_OFFSET3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_0_01_OFFSET3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_1_01_OFFSET2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_1_01_OFFSET2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_1_01_OFFSET3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_1_01_OFFSET3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_2_23_OFFSET2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_2_23_OFFSET2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_2_23_OFFSET3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_2_23_OFFSET3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_3_23_OFFSET2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_3_23_OFFSET2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_3_23_OFFSET3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_3_23_OFFSET3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_4_4_OFFSET2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_4_4_OFFSET2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_4_4_OFFSET3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_4_4_OFFSET3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_0_01_OFFSET4 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_0_01_OFFSET4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_0_01_OFFSET5 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_0_01_OFFSET5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_1_01_OFFSET4 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_1_01_OFFSET4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_1_01_OFFSET5 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_1_01_OFFSET5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_2_23_OFFSET4 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_2_23_OFFSET4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_2_23_OFFSET5 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_2_23_OFFSET5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_3_23_OFFSET4 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_3_23_OFFSET4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_3_23_OFFSET5 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_3_23_OFFSET5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_4_4_OFFSET4 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_4_4_OFFSET4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_4_4_OFFSET5 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_4_4_OFFSET5_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_0_01_OFFSET6 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_0_01_OFFSET6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_0_01_OFFSET7 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_0_01_OFFSET7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_1_01_OFFSET6 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_1_01_OFFSET6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_1_01_OFFSET7 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_1_01_OFFSET7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_2_23_OFFSET6 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_2_23_OFFSET6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_2_23_OFFSET7 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_2_23_OFFSET7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_3_23_OFFSET6 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_3_23_OFFSET6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_3_23_OFFSET7 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_3_23_OFFSET7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_4_4_OFFSET6 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_4_4_OFFSET6_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_4_4_OFFSET7 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_4_4_OFFSET7_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_0_01 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_0_01_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_1_01 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_1_01_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_2_23 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_2_23_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_3_23 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_3_23_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_4_4 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_4_4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_0_01_RD = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_0_01_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_0_01_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_1_01_RD = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_1_01_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_1_01_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_2_23_RD = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_2_23_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_2_23_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_3_23_RD = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_3_23_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_3_23_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_4_4_RD = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_4_4_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_4_4_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_0_01_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_0_01_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_1_01_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_1_01_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_2_23_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_2_23_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_3_23_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_3_23_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_4_4_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_4_4_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_0_01_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_0_01_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_1_01_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_1_01_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_2_23_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_2_23_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_3_23_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_3_23_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_4_4_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_4_4_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_0_01_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_0_01_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_1_01_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_1_01_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_2_23_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_2_23_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_3_23_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_3_23_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_4_4_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_4_4_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_0_01_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_0_01_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_1_01_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_1_01_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_2_23_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_2_23_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_3_23_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_3_23_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_4_4_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_4_4_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_0_01_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_0_01_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_1_01_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_1_01_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_2_23_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_2_23_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_3_23_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_3_23_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_4_4_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_4_4_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_0_01_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_0_01_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_1_01_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_1_01_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_2_23_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_2_23_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_3_23_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_3_23_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_4_4_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_4_4_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_0_01_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_0_01_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_1_01_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_1_01_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_2_23_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_2_23_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_3_23_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_3_23_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_4_4_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_4_4_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_0_01_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_0_01_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_1_01_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_1_01_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_2_23_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_2_23_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_3_23_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_3_23_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_4_4_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_4_4_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_0_01_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_0_01_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_1_01_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_1_01_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_2_23_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_2_23_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_3_23_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_3_23_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_4_4_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_4_4_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_0_01_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_0_01_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_1_01_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_1_01_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_2_23_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_2_23_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_3_23_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_3_23_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_4_4_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_4_4_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_0_01_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_0_01_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_1_01_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_1_01_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_2_23_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_2_23_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_3_23_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_3_23_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_4_4_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_4_4_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_0_01_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_0_01_RD = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_0_01_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_1_01_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_1_01_RD = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_1_01_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_2_23_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_2_23_RD = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_2_23_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_3_23_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_3_23_RD = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_3_23_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_4_4_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_4_4_RD = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_4_4_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_0_01_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_0_01_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_1_01_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_1_01_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_2_23_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_2_23_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_3_23_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_3_23_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_4_4_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_4_4_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_0_01_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_0_01_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_1_01_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_1_01_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_2_23_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_2_23_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_3_23_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_3_23_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_4_4_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_4_4_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_0_01_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_0_01_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_1_01_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_1_01_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_2_23_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_2_23_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_3_23_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_3_23_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_4_4_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_4_4_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_0_01_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_0_01_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_1_01_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_1_01_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_2_23_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_2_23_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_3_23_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_3_23_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_4_4_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_4_4_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_0_01_RD = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_0_01_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_0_01_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_1_01_RD = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_1_01_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_1_01_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_2_23_RD = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_2_23_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_2_23_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_3_23_RD = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_3_23_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_3_23_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_4_4_RD = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_4_4_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_4_4_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_0_01_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_0_01_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_1_01_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_1_01_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_2_23_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_2_23_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_3_23_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_3_23_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_4_4_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_4_4_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_0_01_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_0_01_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_1_01_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_1_01_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_2_23_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_2_23_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_3_23_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_3_23_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_4_4_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_4_4_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_0_01_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_0_01_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_1_01_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_1_01_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_2_23_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_2_23_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_3_23_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_3_23_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_4_4_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_4_4_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_0_01_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_0_01_RD = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_0_01_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_1_01_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_1_01_RD = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_1_01_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_2_23_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_2_23_RD = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_2_23_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_3_23_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_3_23_RD = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_3_23_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_4_4_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_4_4_RD = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_4_4_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_0_01_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_0_01_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_1_01_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_1_01_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_2_23_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_2_23_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_3_23_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_3_23_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_4_4_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_4_4_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_0_01_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_0_01_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_1_01_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_1_01_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_2_23_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_2_23_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_3_23_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_3_23_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_4_4_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_4_4_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_0_01_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_0_01_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_1_01_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_1_01_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_2_23_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_2_23_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_3_23_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_3_23_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_4_4_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_4_4_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_0_01_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_0_01_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_1_01_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_1_01_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_2_23_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_2_23_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_3_23_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_3_23_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_4_4_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_4_4_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_0_01_RD = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_0_01_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_0_01_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_1_01_RD = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_1_01_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_1_01_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_2_23_RD = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_2_23_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_2_23_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_3_23_RD = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_3_23_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_3_23_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_4_4_RD = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_4_4_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_4_4_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_0_01_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_0_01_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_1_01_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_1_01_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_2_23_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_2_23_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_3_23_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_3_23_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_4_4_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_4_4_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_0_01_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_0_01_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_1_01_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_1_01_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_2_23_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_2_23_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_3_23_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_3_23_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_4_4_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_4_4_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_0_01_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_0_01_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_1_01_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_1_01_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_2_23_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_2_23_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_3_23_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_3_23_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_4_4_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_4_4_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_0_01_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_0_01_RD = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_0_01_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_1_01_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_1_01_RD = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_1_01_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_2_23_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_2_23_RD = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_2_23_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_3_23_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_3_23_RD = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_3_23_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_4_4_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_4_4_RD = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_4_4_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_0_01_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_0_01_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_1_01_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_1_01_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_2_23_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_2_23_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_3_23_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_3_23_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_4_4_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_4_4_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_0_01_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_0_01_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_1_01_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_1_01_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_2_23_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_2_23_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_3_23_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_3_23_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_4_4_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_4_4_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_0_01_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_0_01_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_1_01_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_1_01_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_2_23_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_2_23_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_3_23_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_3_23_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_4_4_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_4_4_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_0_01_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_0_01_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_1_01_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_1_01_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_2_23_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_2_23_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_3_23_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_3_23_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_4_4_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_4_4_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_0_01_RD = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_0_01_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_0_01_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_1_01_RD = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_1_01_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_1_01_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_2_23_RD = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_2_23_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_2_23_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_3_23_RD = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_3_23_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_3_23_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_4_4_RD = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_4_4_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_4_4_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_0_01_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_0_01_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_1_01_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_1_01_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_2_23_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_2_23_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_3_23_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_3_23_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_4_4_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_4_4_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_0_01_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_0_01_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_1_01_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_1_01_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_2_23_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_2_23_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_3_23_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_3_23_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_4_4_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_4_4_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_0_01_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_0_01_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_1_01_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_1_01_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_2_23_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_2_23_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_3_23_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_3_23_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_4_4_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_4_4_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_0_01_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_0_01_RD = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_0_01_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_1_01_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_1_01_RD = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_1_01_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_2_23_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_2_23_RD = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_2_23_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_3_23_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_3_23_RD = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_3_23_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_4_4_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_4_4_RD = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_4_4_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_0_01_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_0_01_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_1_01_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_1_01_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_2_23_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_2_23_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_3_23_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_3_23_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_4_4_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_4_4_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_0_01_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_0_01_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_1_01_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_1_01_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_2_23_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_2_23_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_3_23_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_3_23_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_4_4_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_4_4_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_0_01_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_0_01_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_1_01_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_1_01_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_2_23_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_2_23_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_3_23_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_3_23_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_4_4_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_4_4_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_0_01_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_0_01_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_1_01_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_1_01_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_2_23_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_2_23_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_3_23_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_3_23_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_4_4_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_4_4_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_0_01_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_0_01_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_1_01_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_1_01_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_2_23_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_2_23_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_3_23_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_3_23_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_4_4_RD_SIZE0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_4_4_RD_SIZE1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_0_01_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_0_01_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_1_01_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_1_01_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_2_23_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_2_23_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_3_23_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_3_23_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_4_4_RD_SIZE2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_4_4_RD_SIZE3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_0_01_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_0_01_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_1_01_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_1_01_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_2_23_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_2_23_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_3_23_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_3_23_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_4_4_RD_SIZE4 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_4_4_RD_SIZE5 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_0_01_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_0_01_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_1_01_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_1_01_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_2_23_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_2_23_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_3_23_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_3_23_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_4_4_RD_SIZE6 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_4_4_RD_SIZE7 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_0_01 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_0_01_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_0_01_REFERENCE1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_0_01_REFERENCE1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_1_01 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_1_01_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_1_01_REFERENCE1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_1_01_REFERENCE1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_2_23 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_2_23_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_2_23_REFERENCE1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_2_23_REFERENCE1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_3_23 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_3_23_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_3_23_REFERENCE1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_3_23_REFERENCE1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_4_4 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_4_4_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_4_4_REFERENCE1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_4_4_REFERENCE1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_0_01_REFERENCE2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_0_01_REFERENCE2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_0_01_REFERENCE3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_0_01_REFERENCE3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_1_01_REFERENCE2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_1_01_REFERENCE2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_1_01_REFERENCE3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_1_01_REFERENCE3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_2_23_REFERENCE2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_2_23_REFERENCE2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_2_23_REFERENCE3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_2_23_REFERENCE3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_3_23_REFERENCE2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_3_23_REFERENCE2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_3_23_REFERENCE3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_3_23_REFERENCE3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_4_4_REFERENCE2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_4_4_REFERENCE2_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_4_4_REFERENCE3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_4_4_REFERENCE3_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_0_01_NIB0TCFLIP_DC = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_0_01_NIB1TCFLIP_DC = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_0_01_NIB2TCFLIP_DC = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_0_01_NIB3TCFLIP_DC = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_0_01_DD2_MCTERM_FIX_DISABLE = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_0_01_DD2_COARSE_ALN_FIX_DISABLE = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_0_01_DD2_RESET_READ_FIX_DISABLE = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_0_01_DD2_RDFIFO_CG_DISABLE = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_0_01_DD2_RDCNTL_CG_DISABLE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_0_01_DD2_WRCNTL_CG_DISABLE = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_0_01_DD2_PARERROR_FIX_DISABLE = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_0_01_DISABLE_TERMINATION = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_0_01_READ_CENTERING_MODE = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_0_01_READ_CENTERING_MODE_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_1_01_NIB0TCFLIP_DC = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_1_01_NIB1TCFLIP_DC = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_1_01_NIB2TCFLIP_DC = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_1_01_NIB3TCFLIP_DC = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_1_01_DD2_MCTERM_FIX_DISABLE = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_1_01_DD2_COARSE_ALN_FIX_DISABLE = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_1_01_DD2_RESET_READ_FIX_DISABLE = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_1_01_DD2_RDFIFO_CG_DISABLE = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_1_01_DD2_RDCNTL_CG_DISABLE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_1_01_DD2_WRCNTL_CG_DISABLE = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_1_01_DD2_PARERROR_FIX_DISABLE = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_1_01_DISABLE_TERMINATION = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_1_01_READ_CENTERING_MODE = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_1_01_READ_CENTERING_MODE_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_2_23_NIB0TCFLIP_DC = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_2_23_NIB1TCFLIP_DC = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_2_23_NIB2TCFLIP_DC = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_2_23_NIB3TCFLIP_DC = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_2_23_DD2_MCTERM_FIX_DISABLE = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_2_23_DD2_COARSE_ALN_FIX_DISABLE = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_2_23_DD2_RESET_READ_FIX_DISABLE = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_2_23_DD2_RDFIFO_CG_DISABLE = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_2_23_DD2_RDCNTL_CG_DISABLE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_2_23_DD2_WRCNTL_CG_DISABLE = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_2_23_DD2_PARERROR_FIX_DISABLE = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_2_23_DISABLE_TERMINATION = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_2_23_READ_CENTERING_MODE = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_2_23_READ_CENTERING_MODE_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_3_23_NIB0TCFLIP_DC = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_3_23_NIB1TCFLIP_DC = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_3_23_NIB2TCFLIP_DC = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_3_23_NIB3TCFLIP_DC = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_3_23_DD2_MCTERM_FIX_DISABLE = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_3_23_DD2_COARSE_ALN_FIX_DISABLE = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_3_23_DD2_RESET_READ_FIX_DISABLE = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_3_23_DD2_RDFIFO_CG_DISABLE = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_3_23_DD2_RDCNTL_CG_DISABLE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_3_23_DD2_WRCNTL_CG_DISABLE = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_3_23_DD2_PARERROR_FIX_DISABLE = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_3_23_DISABLE_TERMINATION = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_3_23_READ_CENTERING_MODE = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_3_23_READ_CENTERING_MODE_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_4_4_NIB0TCFLIP_DC = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_4_4_NIB1TCFLIP_DC = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_4_4_NIB2TCFLIP_DC = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_4_4_NIB3TCFLIP_DC = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_4_4_DD2_MCTERM_FIX_DISABLE = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_4_4_DD2_COARSE_ALN_FIX_DISABLE = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_4_4_DD2_RESET_READ_FIX_DISABLE = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_4_4_DD2_RDFIFO_CG_DISABLE = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_4_4_DD2_RDCNTL_CG_DISABLE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_4_4_DD2_WRCNTL_CG_DISABLE = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_4_4_DD2_PARERROR_FIX_DISABLE = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_4_4_DISABLE_TERMINATION = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_4_4_READ_CENTERING_MODE = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_RX_CONFIG0_P0_4_4_READ_CENTERING_MODE_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_ROT_OVERRIDE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_ROT_OVERRIDE_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_ROT_OVERRIDE_EN = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_PHASE_ALIGN_RESET = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_PHASE_CNTL_EN = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_PHASE_DEFAULT_EN = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_POS_EDGE_ALIGN = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_CONTINUOUS_UPDATE = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1_01_ROT_OVERRIDE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1_01_ROT_OVERRIDE_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1_01_ROT_OVERRIDE_EN = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1_01_PHASE_ALIGN_RESET = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1_01_PHASE_CNTL_EN = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1_01_PHASE_DEFAULT_EN = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1_01_POS_EDGE_ALIGN = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1_01_CONTINUOUS_UPDATE = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2_23_ROT_OVERRIDE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2_23_ROT_OVERRIDE_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2_23_ROT_OVERRIDE_EN = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2_23_PHASE_ALIGN_RESET = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2_23_PHASE_CNTL_EN = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2_23_PHASE_DEFAULT_EN = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2_23_POS_EDGE_ALIGN = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2_23_CONTINUOUS_UPDATE = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3_23_ROT_OVERRIDE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3_23_ROT_OVERRIDE_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3_23_ROT_OVERRIDE_EN = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3_23_PHASE_ALIGN_RESET = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3_23_PHASE_CNTL_EN = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3_23_PHASE_DEFAULT_EN = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3_23_POS_EDGE_ALIGN = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3_23_CONTINUOUS_UPDATE = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4_4_ROT_OVERRIDE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4_4_ROT_OVERRIDE_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4_4_ROT_OVERRIDE_EN = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4_4_PHASE_ALIGN_RESET = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4_4_PHASE_CNTL_EN = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4_4_PHASE_DEFAULT_EN = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4_4_POS_EDGE_ALIGN = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4_4_CONTINUOUS_UPDATE = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0_01_ROT_OVERRIDE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0_01_ROT_OVERRIDE_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0_01_ROT_OVERRIDE_EN = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0_01_PHASE_ALIGN_RESET = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0_01_PHASE_CNTL_EN = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0_01_PHASE_DEFAULT_EN = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0_01_POS_EDGE_ALIGN = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0_01_CONTINUOUS_UPDATE = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1_01_ROT_OVERRIDE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1_01_ROT_OVERRIDE_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1_01_ROT_OVERRIDE_EN = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1_01_PHASE_ALIGN_RESET = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1_01_PHASE_CNTL_EN = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1_01_PHASE_DEFAULT_EN = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1_01_POS_EDGE_ALIGN = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1_01_CONTINUOUS_UPDATE = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2_23_ROT_OVERRIDE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2_23_ROT_OVERRIDE_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2_23_ROT_OVERRIDE_EN = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2_23_PHASE_ALIGN_RESET = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2_23_PHASE_CNTL_EN = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2_23_PHASE_DEFAULT_EN = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2_23_POS_EDGE_ALIGN = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2_23_CONTINUOUS_UPDATE = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3_23_ROT_OVERRIDE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3_23_ROT_OVERRIDE_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3_23_ROT_OVERRIDE_EN = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3_23_PHASE_ALIGN_RESET = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3_23_PHASE_CNTL_EN = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3_23_PHASE_DEFAULT_EN = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3_23_POS_EDGE_ALIGN = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3_23_CONTINUOUS_UPDATE = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_4_4_ROT_OVERRIDE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_4_4_ROT_OVERRIDE_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_4_4_ROT_OVERRIDE_EN = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_4_4_PHASE_ALIGN_RESET = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_4_4_PHASE_CNTL_EN = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_4_4_PHASE_DEFAULT_EN = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_4_4_POS_EDGE_ALIGN = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR1_P0_4_4_CONTINUOUS_UPDATE = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_0_01_BB_LOCK0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_0_01_ROT0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_0_01_ROT0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_0_01_BB_LOCK1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_0_01_ROT1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_0_01_ROT1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_1_01_BB_LOCK0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_1_01_ROT0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_1_01_ROT0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_1_01_BB_LOCK1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_1_01_ROT1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_1_01_ROT1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_2_23_BB_LOCK0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_2_23_ROT0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_2_23_ROT0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_2_23_BB_LOCK1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_2_23_ROT1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_2_23_ROT1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_3_23_BB_LOCK0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_3_23_ROT0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_3_23_ROT0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_3_23_BB_LOCK1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_3_23_ROT1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_3_23_ROT1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_4_4_BB_LOCK0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_4_4_ROT0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_4_4_ROT0_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_4_4_BB_LOCK1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_4_4_ROT1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_4_4_ROT1_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD0_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD1_CLK16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD0_CLK18 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD1_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD2_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD3_CLK20 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD2_CLK22 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD3_CLK22 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_QUAD0_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_QUAD1_CLK16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_QUAD0_CLK18 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_QUAD1_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_QUAD2_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_QUAD3_CLK20 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_QUAD2_CLK22 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_QUAD3_CLK22 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_QUAD0_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_QUAD1_CLK16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_QUAD0_CLK18 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_QUAD1_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_QUAD2_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_QUAD3_CLK20 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_QUAD2_CLK22 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_QUAD3_CLK22 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_QUAD0_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_QUAD1_CLK16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_QUAD0_CLK18 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_QUAD1_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_QUAD2_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_QUAD3_CLK20 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_QUAD2_CLK22 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_QUAD3_CLK22 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_QUAD0_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_QUAD1_CLK16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_QUAD0_CLK18 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_QUAD1_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_QUAD2_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_QUAD3_CLK20 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_QUAD2_CLK22 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_QUAD3_CLK22 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_QUAD0_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_QUAD1_CLK16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_QUAD0_CLK18 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_QUAD1_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_QUAD2_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_QUAD3_CLK20 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_QUAD2_CLK22 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_QUAD3_CLK22 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_QUAD0_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_QUAD1_CLK16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_QUAD0_CLK18 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_QUAD1_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_QUAD2_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_QUAD3_CLK20 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_QUAD2_CLK22 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_QUAD3_CLK22 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_QUAD0_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_QUAD1_CLK16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_QUAD0_CLK18 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_QUAD1_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_QUAD2_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_QUAD3_CLK20 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_QUAD2_CLK22 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_QUAD3_CLK22 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_QUAD0_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_QUAD1_CLK16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_QUAD0_CLK18 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_QUAD1_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_QUAD2_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_QUAD3_CLK20 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_QUAD2_CLK22 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_QUAD3_CLK22 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_QUAD0_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_QUAD1_CLK16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_QUAD0_CLK18 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_QUAD1_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_QUAD2_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_QUAD3_CLK20 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_QUAD2_CLK22 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_QUAD3_CLK22 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_QUAD0_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_QUAD1_CLK16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_QUAD0_CLK18 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_QUAD1_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_QUAD2_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_QUAD3_CLK20 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_QUAD2_CLK22 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_QUAD3_CLK22 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_QUAD0_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_QUAD1_CLK16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_QUAD0_CLK18 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_QUAD1_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_QUAD2_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_QUAD3_CLK20 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_QUAD2_CLK22 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_QUAD3_CLK22 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_QUAD0_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_QUAD1_CLK16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_QUAD0_CLK18 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_QUAD1_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_QUAD2_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_QUAD3_CLK20 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_QUAD2_CLK22 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_QUAD3_CLK22 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_QUAD0_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_QUAD1_CLK16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_QUAD0_CLK18 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_QUAD1_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_QUAD2_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_QUAD3_CLK20 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_QUAD2_CLK22 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_QUAD3_CLK22 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_QUAD0_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_QUAD1_CLK16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_QUAD0_CLK18 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_QUAD1_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_QUAD2_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_QUAD3_CLK20 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_QUAD2_CLK22 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_QUAD3_CLK22 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_QUAD0_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_QUAD1_CLK16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_QUAD0_CLK18 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_QUAD1_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_QUAD2_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_QUAD3_CLK20 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_QUAD2_CLK22 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_QUAD3_CLK22 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_QUAD0_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_QUAD1_CLK16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_QUAD0_CLK18 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_QUAD1_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_QUAD2_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_QUAD3_CLK20 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_QUAD2_CLK22 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_QUAD3_CLK22 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_QUAD0_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_QUAD1_CLK16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_QUAD0_CLK18 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_QUAD1_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_QUAD2_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_QUAD3_CLK20 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_QUAD2_CLK22 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_QUAD3_CLK22 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_QUAD0_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_QUAD1_CLK16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_QUAD0_CLK18 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_QUAD1_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_QUAD2_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_QUAD3_CLK20 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_QUAD2_CLK22 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_QUAD3_CLK22 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_QUAD0_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_QUAD1_CLK16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_QUAD0_CLK18 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_QUAD1_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_QUAD2_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_QUAD3_CLK20 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_QUAD2_CLK22 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_QUAD3_CLK22 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_PR_P0_0_01_TSYS = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_PR_P0_0_01_TSYS_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_PR_P0_1_01_TSYS = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_PR_P0_1_01_TSYS_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_PR_P0_2_23_TSYS = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_PR_P0_2_23_TSYS_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_PR_P0_3_23_TSYS = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_PR_P0_3_23_TSYS_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_PR_P0_4_4_TSYS = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WRCLK_PR_P0_4_4_TSYS_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0_01_BIT_CENTERED = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0_01_BIT_CENTERED_LEN = 5 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0_01_SMALL_STEP_LEFT = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0_01_BIG_STEP_RIGHT = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0_01_MATCH_STEP_RIGHT = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0_01_JUMP_BACK_RIGHT = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0_01_SMALL_STEP_RIGHT = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0_01_DONE = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1_01_BIT_CENTERED = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1_01_BIT_CENTERED_LEN = 5 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1_01_SMALL_STEP_LEFT = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1_01_BIG_STEP_RIGHT = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1_01_MATCH_STEP_RIGHT = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1_01_JUMP_BACK_RIGHT = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1_01_SMALL_STEP_RIGHT = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1_01_DONE = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2_23_BIT_CENTERED = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2_23_BIT_CENTERED_LEN = 5 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2_23_SMALL_STEP_LEFT = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2_23_BIG_STEP_RIGHT = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2_23_MATCH_STEP_RIGHT = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2_23_JUMP_BACK_RIGHT = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2_23_SMALL_STEP_RIGHT = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2_23_DONE = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3_23_BIT_CENTERED = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3_23_BIT_CENTERED_LEN = 5 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3_23_SMALL_STEP_LEFT = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3_23_BIG_STEP_RIGHT = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3_23_MATCH_STEP_RIGHT = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3_23_JUMP_BACK_RIGHT = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3_23_SMALL_STEP_RIGHT = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3_23_DONE = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4_4_BIT_CENTERED = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4_4_BIT_CENTERED_LEN = 5 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4_4_SMALL_STEP_LEFT = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4_4_BIG_STEP_RIGHT = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4_4_MATCH_STEP_RIGHT = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4_4_JUMP_BACK_RIGHT = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4_4_SMALL_STEP_RIGHT = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4_4_DONE = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_0_01_FW_LEFT_SIDE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_0_01_FW_LEFT_SIDE_LEN = 11 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_1_01_FW_LEFT_SIDE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_1_01_FW_LEFT_SIDE_LEN = 11 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_2_23_FW_LEFT_SIDE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_2_23_FW_LEFT_SIDE_LEN = 11 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_3_23_FW_LEFT_SIDE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_3_23_FW_LEFT_SIDE_LEN = 11 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_4_4_FW_LEFT_SIDE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_4_4_FW_LEFT_SIDE_LEN = 11 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_0_01_FW_RIGHT_SIDE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_0_01_FW_RIGHT_SIDE_LEN = 11 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_1_01_FW_RIGHT_SIDE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_1_01_FW_RIGHT_SIDE_LEN = 11 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_2_23_FW_RIGHT_SIDE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_2_23_FW_RIGHT_SIDE_LEN = 11 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_3_23_FW_RIGHT_SIDE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_3_23_FW_RIGHT_SIDE_LEN = 11 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_4_4_FW_RIGHT_SIDE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_4_4_FW_RIGHT_SIDE_LEN = 11 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P0_0_01_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P0_0_01_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P0_1_01_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P0_1_01_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P0_2_23_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P0_2_23_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P0_3_23_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P0_3_23_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P0_4_4_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP0_P0_4_4_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P0_0_01_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P0_0_01_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P0_1_01_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P0_1_01_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P0_2_23_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P0_2_23_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P0_3_23_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P0_3_23_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P0_4_4_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP1_P0_4_4_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P0_0_01_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P0_0_01_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P0_1_01_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P0_1_01_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P0_2_23_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P0_2_23_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P0_3_23_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P0_3_23_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P0_4_4_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP2_P0_4_4_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P0_0_01_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P0_0_01_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P0_1_01_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P0_1_01_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P0_2_23_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P0_2_23_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P0_3_23_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P0_3_23_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P0_4_4_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_0_RP3_P0_4_4_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P0_0_01_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P0_0_01_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P0_1_01_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P0_1_01_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P0_2_23_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P0_2_23_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P0_3_23_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P0_3_23_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P0_4_4_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP0_P0_4_4_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P0_0_01_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P0_0_01_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P0_1_01_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P0_1_01_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P0_2_23_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P0_2_23_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P0_3_23_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P0_3_23_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P0_4_4_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP1_P0_4_4_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P0_0_01_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P0_0_01_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P0_1_01_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P0_1_01_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P0_2_23_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P0_2_23_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P0_3_23_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P0_3_23_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P0_4_4_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP2_P0_4_4_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P0_0_01_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P0_0_01_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P0_1_01_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P0_1_01_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P0_2_23_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P0_2_23_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P0_3_23_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P0_3_23_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P0_4_4_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_10_RP3_P0_4_4_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P0_0_01_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P0_0_01_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P0_1_01_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P0_1_01_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P0_2_23_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P0_2_23_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P0_3_23_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P0_3_23_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P0_4_4_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP0_P0_4_4_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P0_0_01_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P0_0_01_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P0_1_01_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P0_1_01_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P0_2_23_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P0_2_23_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P0_3_23_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P0_3_23_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P0_4_4_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP1_P0_4_4_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P0_0_01_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P0_0_01_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P0_1_01_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P0_1_01_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P0_2_23_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P0_2_23_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P0_3_23_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P0_3_23_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P0_4_4_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP2_P0_4_4_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P0_0_01_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P0_0_01_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P0_1_01_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P0_1_01_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P0_2_23_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P0_2_23_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P0_3_23_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P0_3_23_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P0_4_4_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_11_RP3_P0_4_4_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P0_0_01_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P0_0_01_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P0_1_01_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P0_1_01_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P0_2_23_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P0_2_23_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P0_3_23_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P0_3_23_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P0_4_4_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP0_P0_4_4_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P0_0_01_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P0_0_01_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P0_1_01_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P0_1_01_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P0_2_23_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P0_2_23_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P0_3_23_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P0_3_23_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P0_4_4_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP1_P0_4_4_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P0_0_01_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P0_0_01_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P0_1_01_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P0_1_01_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P0_2_23_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P0_2_23_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P0_3_23_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P0_3_23_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P0_4_4_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP2_P0_4_4_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P0_0_01_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P0_0_01_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P0_1_01_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P0_1_01_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P0_2_23_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P0_2_23_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P0_3_23_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P0_3_23_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P0_4_4_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_12_RP3_P0_4_4_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P0_0_01_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P0_0_01_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P0_1_01_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P0_1_01_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P0_2_23_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P0_2_23_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P0_3_23_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P0_3_23_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P0_4_4_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP0_P0_4_4_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P0_0_01_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P0_0_01_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P0_1_01_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P0_1_01_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P0_2_23_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P0_2_23_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P0_3_23_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P0_3_23_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P0_4_4_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP1_P0_4_4_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P0_0_01_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P0_0_01_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P0_1_01_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P0_1_01_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P0_2_23_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P0_2_23_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P0_3_23_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P0_3_23_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P0_4_4_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP2_P0_4_4_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P0_0_01_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P0_0_01_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P0_1_01_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P0_1_01_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P0_2_23_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P0_2_23_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P0_3_23_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P0_3_23_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P0_4_4_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_13_RP3_P0_4_4_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P0_0_01_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P0_0_01_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P0_1_01_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P0_1_01_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P0_2_23_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P0_2_23_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P0_3_23_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P0_3_23_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P0_4_4_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP0_P0_4_4_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P0_0_01_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P0_0_01_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P0_1_01_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P0_1_01_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P0_2_23_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P0_2_23_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P0_3_23_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P0_3_23_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P0_4_4_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP1_P0_4_4_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P0_0_01_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P0_0_01_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P0_1_01_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P0_1_01_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P0_2_23_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P0_2_23_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P0_3_23_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P0_3_23_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P0_4_4_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP2_P0_4_4_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P0_0_01_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P0_0_01_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P0_1_01_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P0_1_01_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P0_2_23_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P0_2_23_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P0_3_23_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P0_3_23_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P0_4_4_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_14_RP3_P0_4_4_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P0_0_01_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P0_0_01_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P0_1_01_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P0_1_01_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P0_2_23_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P0_2_23_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P0_3_23_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P0_3_23_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P0_4_4_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP0_P0_4_4_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P0_0_01_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P0_0_01_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P0_1_01_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P0_1_01_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P0_2_23_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P0_2_23_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P0_3_23_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P0_3_23_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P0_4_4_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP1_P0_4_4_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P0_0_01_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P0_0_01_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P0_1_01_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P0_1_01_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P0_2_23_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P0_2_23_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P0_3_23_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P0_3_23_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P0_4_4_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP2_P0_4_4_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P0_0_01_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P0_0_01_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P0_1_01_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P0_1_01_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P0_2_23_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P0_2_23_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P0_3_23_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P0_3_23_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P0_4_4_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_15_RP3_P0_4_4_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P0_0_01_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P0_0_01_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P0_1_01_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P0_1_01_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P0_2_23_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P0_2_23_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P0_3_23_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P0_3_23_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P0_4_4_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP0_P0_4_4_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P0_0_01_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P0_0_01_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P0_1_01_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P0_1_01_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P0_2_23_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P0_2_23_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P0_3_23_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P0_3_23_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P0_4_4_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP1_P0_4_4_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P0_0_01_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P0_0_01_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P0_1_01_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P0_1_01_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P0_2_23_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P0_2_23_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P0_3_23_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P0_3_23_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P0_4_4_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP2_P0_4_4_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P0_0_01_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P0_0_01_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P0_1_01_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P0_1_01_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P0_2_23_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P0_2_23_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P0_3_23_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P0_3_23_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P0_4_4_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_16_RP3_P0_4_4_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P0_0_01_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P0_0_01_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P0_1_01_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P0_1_01_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P0_2_23_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P0_2_23_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P0_3_23_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P0_3_23_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P0_4_4_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP0_P0_4_4_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P0_0_01_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P0_0_01_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P0_1_01_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P0_1_01_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P0_2_23_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P0_2_23_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P0_3_23_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P0_3_23_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P0_4_4_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP1_P0_4_4_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P0_0_01_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P0_0_01_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P0_1_01_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P0_1_01_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P0_2_23_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P0_2_23_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P0_3_23_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P0_3_23_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P0_4_4_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP2_P0_4_4_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P0_0_01_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P0_0_01_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P0_1_01_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P0_1_01_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P0_2_23_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P0_2_23_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P0_3_23_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P0_3_23_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P0_4_4_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_18_RP3_P0_4_4_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P0_0_01_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P0_0_01_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P0_1_01_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P0_1_01_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P0_2_23_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P0_2_23_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P0_3_23_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P0_3_23_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P0_4_4_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP0_P0_4_4_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P0_0_01_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P0_0_01_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P0_1_01_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P0_1_01_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P0_2_23_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P0_2_23_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P0_3_23_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P0_3_23_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P0_4_4_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP1_P0_4_4_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P0_0_01_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P0_0_01_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P0_1_01_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P0_1_01_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P0_2_23_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P0_2_23_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P0_3_23_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P0_3_23_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P0_4_4_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP2_P0_4_4_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P0_0_01_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P0_0_01_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P0_1_01_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P0_1_01_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P0_2_23_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P0_2_23_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P0_3_23_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P0_3_23_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P0_4_4_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_1_RP3_P0_4_4_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P0_0_01_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P0_0_01_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P0_1_01_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P0_1_01_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P0_2_23_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P0_2_23_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P0_3_23_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P0_3_23_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P0_4_4_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP0_P0_4_4_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P0_0_01_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P0_0_01_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P0_1_01_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P0_1_01_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P0_2_23_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P0_2_23_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P0_3_23_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P0_3_23_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P0_4_4_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP1_P0_4_4_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P0_0_01_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P0_0_01_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P0_1_01_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P0_1_01_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P0_2_23_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P0_2_23_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P0_3_23_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P0_3_23_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P0_4_4_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP2_P0_4_4_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P0_0_01_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P0_0_01_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P0_1_01_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P0_1_01_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P0_2_23_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P0_2_23_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P0_3_23_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P0_3_23_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P0_4_4_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_20_RP3_P0_4_4_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P0_0_01_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P0_0_01_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P0_1_01_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P0_1_01_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P0_2_23_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P0_2_23_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P0_3_23_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P0_3_23_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P0_4_4_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP0_P0_4_4_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P0_0_01_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P0_0_01_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P0_1_01_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P0_1_01_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P0_2_23_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P0_2_23_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P0_3_23_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P0_3_23_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P0_4_4_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP1_P0_4_4_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P0_0_01_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P0_0_01_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P0_1_01_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P0_1_01_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P0_2_23_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P0_2_23_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P0_3_23_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P0_3_23_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P0_4_4_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP2_P0_4_4_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P0_0_01_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P0_0_01_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P0_1_01_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P0_1_01_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P0_2_23_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P0_2_23_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P0_3_23_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P0_3_23_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P0_4_4_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_22_RP3_P0_4_4_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P0_0_01_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P0_0_01_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P0_1_01_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P0_1_01_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P0_2_23_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P0_2_23_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P0_3_23_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P0_3_23_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P0_4_4_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP0_P0_4_4_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P0_0_01_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P0_0_01_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P0_1_01_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P0_1_01_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P0_2_23_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P0_2_23_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P0_3_23_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P0_3_23_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P0_4_4_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP1_P0_4_4_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P0_0_01_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P0_0_01_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P0_1_01_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P0_1_01_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P0_2_23_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P0_2_23_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P0_3_23_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P0_3_23_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P0_4_4_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP2_P0_4_4_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P0_0_01_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P0_0_01_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P0_1_01_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P0_1_01_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P0_2_23_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P0_2_23_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P0_3_23_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P0_3_23_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P0_4_4_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_2_RP3_P0_4_4_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P0_0_01_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P0_0_01_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P0_1_01_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P0_1_01_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P0_2_23_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P0_2_23_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P0_3_23_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P0_3_23_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P0_4_4_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP0_P0_4_4_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P0_0_01_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P0_0_01_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P0_1_01_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P0_1_01_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P0_2_23_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P0_2_23_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P0_3_23_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P0_3_23_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P0_4_4_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP1_P0_4_4_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P0_0_01_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P0_0_01_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P0_1_01_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P0_1_01_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P0_2_23_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P0_2_23_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P0_3_23_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P0_3_23_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P0_4_4_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP2_P0_4_4_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P0_0_01_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P0_0_01_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P0_1_01_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P0_1_01_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P0_2_23_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P0_2_23_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P0_3_23_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P0_3_23_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P0_4_4_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_3_RP3_P0_4_4_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P0_0_01_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P0_0_01_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P0_1_01_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P0_1_01_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P0_2_23_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P0_2_23_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P0_3_23_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P0_3_23_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P0_4_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP0_P0_4_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P0_0_01_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P0_0_01_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P0_1_01_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P0_1_01_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P0_2_23_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P0_2_23_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P0_3_23_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P0_3_23_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P0_4_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP1_P0_4_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P0_0_01_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P0_0_01_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P0_1_01_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P0_1_01_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P0_2_23_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P0_2_23_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P0_3_23_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P0_3_23_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P0_4_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP2_P0_4_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P0_0_01_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P0_0_01_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P0_1_01_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P0_1_01_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P0_2_23_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P0_2_23_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P0_3_23_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P0_3_23_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P0_4_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_4_RP3_P0_4_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P0_0_01_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P0_0_01_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P0_1_01_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P0_1_01_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P0_2_23_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P0_2_23_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P0_3_23_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P0_3_23_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P0_4_4_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP0_P0_4_4_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P0_0_01_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P0_0_01_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P0_1_01_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P0_1_01_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P0_2_23_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P0_2_23_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P0_3_23_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P0_3_23_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P0_4_4_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP1_P0_4_4_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P0_0_01_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P0_0_01_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P0_1_01_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P0_1_01_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P0_2_23_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P0_2_23_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P0_3_23_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P0_3_23_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P0_4_4_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP2_P0_4_4_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P0_0_01_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P0_0_01_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P0_1_01_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P0_1_01_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P0_2_23_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P0_2_23_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P0_3_23_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P0_3_23_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P0_4_4_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_5_RP3_P0_4_4_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P0_0_01_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P0_0_01_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P0_1_01_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P0_1_01_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P0_2_23_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P0_2_23_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P0_3_23_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P0_3_23_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P0_4_4_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP0_P0_4_4_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P0_0_01_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P0_0_01_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P0_1_01_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P0_1_01_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P0_2_23_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P0_2_23_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P0_3_23_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P0_3_23_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P0_4_4_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP1_P0_4_4_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P0_0_01_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P0_0_01_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P0_1_01_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P0_1_01_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P0_2_23_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P0_2_23_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P0_3_23_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P0_3_23_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P0_4_4_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP2_P0_4_4_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P0_0_01_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P0_0_01_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P0_1_01_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P0_1_01_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P0_2_23_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P0_2_23_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P0_3_23_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P0_3_23_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P0_4_4_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_6_RP3_P0_4_4_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P0_0_01_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P0_0_01_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P0_1_01_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P0_1_01_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P0_2_23_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P0_2_23_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P0_3_23_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P0_3_23_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P0_4_4_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP0_P0_4_4_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P0_0_01_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P0_0_01_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P0_1_01_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P0_1_01_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P0_2_23_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P0_2_23_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P0_3_23_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P0_3_23_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P0_4_4_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP1_P0_4_4_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P0_0_01_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P0_0_01_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P0_1_01_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P0_1_01_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P0_2_23_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P0_2_23_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P0_3_23_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P0_3_23_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P0_4_4_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP2_P0_4_4_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P0_0_01_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P0_0_01_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P0_1_01_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P0_1_01_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P0_2_23_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P0_2_23_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P0_3_23_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P0_3_23_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P0_4_4_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_7_RP3_P0_4_4_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P0_0_01_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P0_0_01_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P0_1_01_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P0_1_01_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P0_2_23_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P0_2_23_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P0_3_23_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P0_3_23_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P0_4_4_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP0_P0_4_4_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P0_0_01_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P0_0_01_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P0_1_01_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P0_1_01_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P0_2_23_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P0_2_23_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P0_3_23_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P0_3_23_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P0_4_4_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP1_P0_4_4_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P0_0_01_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P0_0_01_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P0_1_01_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P0_1_01_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P0_2_23_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P0_2_23_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P0_3_23_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P0_3_23_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P0_4_4_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP2_P0_4_4_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P0_0_01_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P0_0_01_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P0_1_01_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P0_1_01_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P0_2_23_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P0_2_23_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P0_3_23_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P0_3_23_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P0_4_4_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_8_RP3_P0_4_4_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P0_0_01_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P0_0_01_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P0_1_01_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P0_1_01_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P0_2_23_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P0_2_23_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P0_3_23_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P0_3_23_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P0_4_4_DELAY0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP0_P0_4_4_DELAY0_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P0_0_01_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P0_0_01_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P0_1_01_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P0_1_01_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P0_2_23_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P0_2_23_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P0_3_23_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P0_3_23_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P0_4_4_DELAY1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP1_P0_4_4_DELAY1_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P0_0_01_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P0_0_01_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P0_1_01_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P0_1_01_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P0_2_23_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P0_2_23_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P0_3_23_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P0_3_23_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P0_4_4_DELAY2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP2_P0_4_4_DELAY2_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P0_0_01_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P0_0_01_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P0_1_01_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P0_1_01_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P0_2_23_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P0_2_23_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P0_3_23_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P0_3_23_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P0_4_4_DELAY3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_DELAY_VALUE_9_RP3_P0_4_4_DELAY3_LEN = 10 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_WL_ERR_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_WL_ERR_CLK18 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_WL_ERR_CLK20 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_WL_ERR_CLK22 = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_COARSE_ERR_CLK16 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_COARSE_ERR_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_COARSE_ERR_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_COARSE_ERR_CLK22 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_VALID_NS_BIG_L = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_INVALID_NS_SMALL_L = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_VALID_NS_BIG_R = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_INVALID_NS_BIG_R = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_VALID_NS_JUMP_BACK = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_INVALID_NS_SMALL_R = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_OFFSET_ERR = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_WL_ERR_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_WL_ERR_CLK18 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_WL_ERR_CLK20 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_WL_ERR_CLK22 = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_COARSE_ERR_CLK16 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_COARSE_ERR_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_COARSE_ERR_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_COARSE_ERR_CLK22 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_VALID_NS_BIG_L = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_INVALID_NS_SMALL_L = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_VALID_NS_BIG_R = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_INVALID_NS_BIG_R = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_VALID_NS_JUMP_BACK = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_INVALID_NS_SMALL_R = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_OFFSET_ERR = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_WL_ERR_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_WL_ERR_CLK18 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_WL_ERR_CLK20 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_WL_ERR_CLK22 = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_COARSE_ERR_CLK16 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_COARSE_ERR_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_COARSE_ERR_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_COARSE_ERR_CLK22 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_VALID_NS_BIG_L = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_INVALID_NS_SMALL_L = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_VALID_NS_BIG_R = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_INVALID_NS_BIG_R = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_VALID_NS_JUMP_BACK = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_INVALID_NS_SMALL_R = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_OFFSET_ERR = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_WL_ERR_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_WL_ERR_CLK18 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_WL_ERR_CLK20 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_WL_ERR_CLK22 = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_COARSE_ERR_CLK16 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_COARSE_ERR_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_COARSE_ERR_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_COARSE_ERR_CLK22 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_VALID_NS_BIG_L = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_INVALID_NS_SMALL_L = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_VALID_NS_BIG_R = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_INVALID_NS_BIG_R = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_VALID_NS_JUMP_BACK = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_INVALID_NS_SMALL_R = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_OFFSET_ERR = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_WL_ERR_CLK16 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_WL_ERR_CLK18 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_WL_ERR_CLK20 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_WL_ERR_CLK22 = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_COARSE_ERR_CLK16 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_COARSE_ERR_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_COARSE_ERR_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_COARSE_ERR_CLK22 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_VALID_NS_BIG_L = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_INVALID_NS_SMALL_L = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_VALID_NS_BIG_R = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_INVALID_NS_BIG_R = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_VALID_NS_JUMP_BACK = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_INVALID_NS_SMALL_R = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_OFFSET_ERR = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_WL_ERR_CLK16_MASK = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_WL_ERR_CLK18_MASK = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_WL_ERR_CLK20_MASK = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_ERR_CLK22_MASK = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_VALID_NS_BIG_L_MASK = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_INVALID_NS_SMALL_L_MASK = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_VALID_NS_BIG_R_MASK = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_INVALID_NS_BIG_R_MASK = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_VALID_NS_JUMP_BACK_MASK = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_INVALID_NS_SMALL_R_MASK = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_OFFSET_ERR_MASK = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_ADVANCE_PR_VALUE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_WL_ERR_CLK16_MASK = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_WL_ERR_CLK18_MASK = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_WL_ERR_CLK20_MASK = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_ERR_CLK22_MASK = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_VALID_NS_BIG_L_MASK = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_INVALID_NS_SMALL_L_MASK = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_VALID_NS_BIG_R_MASK = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_INVALID_NS_BIG_R_MASK = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_VALID_NS_JUMP_BACK_MASK = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_INVALID_NS_SMALL_R_MASK = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_OFFSET_ERR_MASK = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_ADVANCE_PR_VALUE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_WL_ERR_CLK16_MASK = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_WL_ERR_CLK18_MASK = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_WL_ERR_CLK20_MASK = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_ERR_CLK22_MASK = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_VALID_NS_BIG_L_MASK = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_INVALID_NS_SMALL_L_MASK = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_VALID_NS_BIG_R_MASK = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_INVALID_NS_BIG_R_MASK = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_VALID_NS_JUMP_BACK_MASK = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_INVALID_NS_SMALL_R_MASK = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_OFFSET_ERR_MASK = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_ADVANCE_PR_VALUE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_WL_ERR_CLK16_MASK = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_WL_ERR_CLK18_MASK = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_WL_ERR_CLK20_MASK = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_ERR_CLK22_MASK = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_VALID_NS_BIG_L_MASK = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_INVALID_NS_SMALL_L_MASK = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_VALID_NS_BIG_R_MASK = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_INVALID_NS_BIG_R_MASK = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_VALID_NS_JUMP_BACK_MASK = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_INVALID_NS_SMALL_R_MASK = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_OFFSET_ERR_MASK = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_ADVANCE_PR_VALUE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_WL_ERR_CLK16_MASK = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_WL_ERR_CLK18_MASK = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_WL_ERR_CLK20_MASK = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_ERR_CLK22_MASK = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_VALID_NS_BIG_L_MASK = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_INVALID_NS_SMALL_L_MASK = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_VALID_NS_BIG_R_MASK = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_INVALID_NS_BIG_R_MASK = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_VALID_NS_JUMP_BACK_MASK = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_INVALID_NS_SMALL_R_MASK = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_OFFSET_ERR_MASK = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_ADVANCE_PR_VALUE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0_01_CLK_LEVEL = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0_01_CLK_LEVEL_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0_01_FINE_STEPPING = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0_01_DONE = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0_01_WL_ERR_CLK16 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0_01_WL_ERR_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0_01_WL_ERR_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0_01_WL_ERR_CLK22 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0_01_ZERO_DETECTED = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1_01_CLK_LEVEL = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1_01_CLK_LEVEL_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1_01_FINE_STEPPING = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1_01_DONE = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1_01_WL_ERR_CLK16 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1_01_WL_ERR_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1_01_WL_ERR_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1_01_WL_ERR_CLK22 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1_01_ZERO_DETECTED = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2_23_CLK_LEVEL = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2_23_CLK_LEVEL_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2_23_FINE_STEPPING = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2_23_DONE = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2_23_WL_ERR_CLK16 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2_23_WL_ERR_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2_23_WL_ERR_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2_23_WL_ERR_CLK22 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2_23_ZERO_DETECTED = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3_23_CLK_LEVEL = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3_23_CLK_LEVEL_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3_23_FINE_STEPPING = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3_23_DONE = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3_23_WL_ERR_CLK16 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3_23_WL_ERR_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3_23_WL_ERR_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3_23_WL_ERR_CLK22 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3_23_ZERO_DETECTED = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4_4_CLK_LEVEL = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4_4_CLK_LEVEL_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4_4_FINE_STEPPING = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4_4_DONE = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4_4_WL_ERR_CLK16 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4_4_WL_ERR_CLK18 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4_4_WL_ERR_CLK20 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4_4_WL_ERR_CLK22 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4_4_ZERO_DETECTED = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_1D_MODE_SWITCH = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_RUN_FULL_1D = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_2D_SMALL_STEP_VAL = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_2D_SMALL_STEP_VAL_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_2D_BIG_STEP_VAL = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_2D_BIG_STEP_VAL_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_NUM_BITS_TO_SKIP = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_NUM_BITS_TO_SKIP_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_NUM_NO_INC_COMP = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_NUM_NO_INC_COMP_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_DD2_FIX_DISABLE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_CTR_1D_MODE_SWITCH = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_CTR_RUN_FULL_1D = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_CTR_2D_SMALL_STEP_VAL = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_CTR_2D_SMALL_STEP_VAL_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_CTR_2D_BIG_STEP_VAL = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_CTR_2D_BIG_STEP_VAL_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_CTR_NUM_BITS_TO_SKIP = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_CTR_NUM_BITS_TO_SKIP_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_CTR_NUM_NO_INC_COMP = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_CTR_NUM_NO_INC_COMP_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_DD2_FIX_DISABLE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_CTR_1D_MODE_SWITCH = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_CTR_RUN_FULL_1D = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_CTR_2D_SMALL_STEP_VAL = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_CTR_2D_SMALL_STEP_VAL_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_CTR_2D_BIG_STEP_VAL = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_CTR_2D_BIG_STEP_VAL_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_CTR_NUM_BITS_TO_SKIP = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_CTR_NUM_BITS_TO_SKIP_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_CTR_NUM_NO_INC_COMP = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_CTR_NUM_NO_INC_COMP_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_DD2_FIX_DISABLE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_CTR_1D_MODE_SWITCH = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_CTR_RUN_FULL_1D = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_CTR_2D_SMALL_STEP_VAL = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_CTR_2D_SMALL_STEP_VAL_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_CTR_2D_BIG_STEP_VAL = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_CTR_2D_BIG_STEP_VAL_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_CTR_NUM_BITS_TO_SKIP = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_CTR_NUM_BITS_TO_SKIP_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_CTR_NUM_NO_INC_COMP = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_CTR_NUM_NO_INC_COMP_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_DD2_FIX_DISABLE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_CTR_1D_MODE_SWITCH = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_CTR_RUN_FULL_1D = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_CTR_2D_SMALL_STEP_VAL = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_CTR_2D_SMALL_STEP_VAL_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_CTR_2D_BIG_STEP_VAL = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_CTR_2D_BIG_STEP_VAL_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_CTR_NUM_BITS_TO_SKIP = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_CTR_NUM_BITS_TO_SKIP_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_CTR_NUM_NO_INC_COMP = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_CTR_NUM_NO_INC_COMP_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_DD2_FIX_DISABLE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_0_01_CTR_RANGE_SELECT = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_0_01_CTR_RANGE_CROSSOVER = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_0_01_CTR_RANGE_CROSSOVER_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_0_01_CTR_SINGLE_RANGE_MAX = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_0_01_CTR_SINGLE_RANGE_MAX_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_1_01_CTR_RANGE_SELECT = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_1_01_CTR_RANGE_CROSSOVER = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_1_01_CTR_RANGE_CROSSOVER_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_1_01_CTR_SINGLE_RANGE_MAX = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_1_01_CTR_SINGLE_RANGE_MAX_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_2_23_CTR_RANGE_SELECT = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_2_23_CTR_RANGE_CROSSOVER = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_2_23_CTR_RANGE_CROSSOVER_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_2_23_CTR_SINGLE_RANGE_MAX = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_2_23_CTR_SINGLE_RANGE_MAX_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_3_23_CTR_RANGE_SELECT = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_3_23_CTR_RANGE_CROSSOVER = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_3_23_CTR_RANGE_CROSSOVER_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_3_23_CTR_SINGLE_RANGE_MAX = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_3_23_CTR_SINGLE_RANGE_MAX_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_4_4_CTR_RANGE_SELECT = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_4_4_CTR_RANGE_CROSSOVER = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_4_4_CTR_RANGE_CROSSOVER_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_4_4_CTR_SINGLE_RANGE_MAX = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_4_4_CTR_SINGLE_RANGE_MAX_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_MAX_RANGE_ERR0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_MIN_RANGE_ERR0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_TWO_RANGE_BEST_CASE_ERR0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_BIT_STEP_DELTA_ERR0 = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_STEP_RANGE_EDGE_ERR0 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_NO_INCREASE_ERR0 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_1D_EYE_NOISE_ERR0 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_BAD_BIT_ERR0 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_MAX_RANGE_ERR1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_MIN_RANGE_ERR1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_TWO_RANGE_BEST_CASE_ERR1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_BIT_STEP_DELTA_ERR1 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_STEP_RANGE_EDGE_ERR1 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_NO_INCREASE_ERR1 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_1D_EYE_NOISE_ERR1 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_BAD_BIT_ERR1 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_MAX_RANGE_ERR0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_MIN_RANGE_ERR0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_TWO_RANGE_BEST_CASE_ERR0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_BIT_STEP_DELTA_ERR0 = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_STEP_RANGE_EDGE_ERR0 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_NO_INCREASE_ERR0 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_1D_EYE_NOISE_ERR0 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_BAD_BIT_ERR0 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_MAX_RANGE_ERR1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_MIN_RANGE_ERR1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_TWO_RANGE_BEST_CASE_ERR1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_BIT_STEP_DELTA_ERR1 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_STEP_RANGE_EDGE_ERR1 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_NO_INCREASE_ERR1 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_1D_EYE_NOISE_ERR1 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_BAD_BIT_ERR1 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_MAX_RANGE_ERR0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_MIN_RANGE_ERR0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_TWO_RANGE_BEST_CASE_ERR0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_BIT_STEP_DELTA_ERR0 = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_STEP_RANGE_EDGE_ERR0 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_NO_INCREASE_ERR0 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_1D_EYE_NOISE_ERR0 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_BAD_BIT_ERR0 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_MAX_RANGE_ERR1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_MIN_RANGE_ERR1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_TWO_RANGE_BEST_CASE_ERR1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_BIT_STEP_DELTA_ERR1 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_STEP_RANGE_EDGE_ERR1 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_NO_INCREASE_ERR1 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_1D_EYE_NOISE_ERR1 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_BAD_BIT_ERR1 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_MAX_RANGE_ERR0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_MIN_RANGE_ERR0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_TWO_RANGE_BEST_CASE_ERR0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_BIT_STEP_DELTA_ERR0 = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_STEP_RANGE_EDGE_ERR0 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_NO_INCREASE_ERR0 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_1D_EYE_NOISE_ERR0 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_BAD_BIT_ERR0 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_MAX_RANGE_ERR1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_MIN_RANGE_ERR1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_TWO_RANGE_BEST_CASE_ERR1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_BIT_STEP_DELTA_ERR1 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_STEP_RANGE_EDGE_ERR1 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_NO_INCREASE_ERR1 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_1D_EYE_NOISE_ERR1 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_BAD_BIT_ERR1 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_MAX_RANGE_ERR0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_MIN_RANGE_ERR0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_TWO_RANGE_BEST_CASE_ERR0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_BIT_STEP_DELTA_ERR0 = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_STEP_RANGE_EDGE_ERR0 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_NO_INCREASE_ERR0 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_1D_EYE_NOISE_ERR0 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_BAD_BIT_ERR0 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_MAX_RANGE_ERR1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_MIN_RANGE_ERR1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_TWO_RANGE_BEST_CASE_ERR1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_BIT_STEP_DELTA_ERR1 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_STEP_RANGE_EDGE_ERR1 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_NO_INCREASE_ERR1 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_1D_EYE_NOISE_ERR1 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_BAD_BIT_ERR1 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_MAX_RANGE_ERR2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_MIN_RANGE_ERR2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_TWO_RANGE_BEST_CASE_ERR2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_BIT_STEP_DELTA_ERR2 = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_STEP_RANGE_EDGE_ERR2 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_NO_INCREASE_ERR2 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_1D_EYE_NOISE_ERR2 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_BAD_BIT_ERR2 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_MAX_RANGE_ERR3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_MIN_RANGE_ERR3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_TWO_RANGE_BEST_CASE_ERR3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_BIT_STEP_DELTA_ERR3 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_STEP_RANGE_EDGE_ERR3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_NO_INCREASE_ERR3 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_1D_EYE_NOISE_ERR3 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_BAD_BIT_ERR3 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_MAX_RANGE_ERR2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_MIN_RANGE_ERR2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_TWO_RANGE_BEST_CASE_ERR2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_BIT_STEP_DELTA_ERR2 = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_STEP_RANGE_EDGE_ERR2 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_NO_INCREASE_ERR2 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_1D_EYE_NOISE_ERR2 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_BAD_BIT_ERR2 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_MAX_RANGE_ERR3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_MIN_RANGE_ERR3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_TWO_RANGE_BEST_CASE_ERR3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_BIT_STEP_DELTA_ERR3 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_STEP_RANGE_EDGE_ERR3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_NO_INCREASE_ERR3 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_1D_EYE_NOISE_ERR3 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_BAD_BIT_ERR3 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_MAX_RANGE_ERR2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_MIN_RANGE_ERR2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_TWO_RANGE_BEST_CASE_ERR2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_BIT_STEP_DELTA_ERR2 = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_STEP_RANGE_EDGE_ERR2 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_NO_INCREASE_ERR2 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_1D_EYE_NOISE_ERR2 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_BAD_BIT_ERR2 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_MAX_RANGE_ERR3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_MIN_RANGE_ERR3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_TWO_RANGE_BEST_CASE_ERR3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_BIT_STEP_DELTA_ERR3 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_STEP_RANGE_EDGE_ERR3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_NO_INCREASE_ERR3 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_1D_EYE_NOISE_ERR3 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_BAD_BIT_ERR3 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_MAX_RANGE_ERR2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_MIN_RANGE_ERR2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_TWO_RANGE_BEST_CASE_ERR2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_BIT_STEP_DELTA_ERR2 = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_STEP_RANGE_EDGE_ERR2 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_NO_INCREASE_ERR2 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_1D_EYE_NOISE_ERR2 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_BAD_BIT_ERR2 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_MAX_RANGE_ERR3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_MIN_RANGE_ERR3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_TWO_RANGE_BEST_CASE_ERR3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_BIT_STEP_DELTA_ERR3 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_STEP_RANGE_EDGE_ERR3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_NO_INCREASE_ERR3 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_1D_EYE_NOISE_ERR3 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_BAD_BIT_ERR3 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_MAX_RANGE_ERR2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_MIN_RANGE_ERR2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_TWO_RANGE_BEST_CASE_ERR2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_BIT_STEP_DELTA_ERR2 = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_STEP_RANGE_EDGE_ERR2 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_NO_INCREASE_ERR2 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_1D_EYE_NOISE_ERR2 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_BAD_BIT_ERR2 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_MAX_RANGE_ERR3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_MIN_RANGE_ERR3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_TWO_RANGE_BEST_CASE_ERR3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_BIT_STEP_DELTA_ERR3 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_STEP_RANGE_EDGE_ERR3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_NO_INCREASE_ERR3 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_1D_EYE_NOISE_ERR3 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_BAD_BIT_ERR3 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_MAX_RANGE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_MIN_RANGE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_TWO_RANGE_BEST_CASE = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_BIT_STEP_DELTA = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_STEP_RANGE_EDGE = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_NO_INCREASE = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_1D_EYE_NOISE = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_BAD_BIT = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_MAX_RANGE_MASK1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_MIN_RANGE_MASK1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_TWO_RANGE_BEST_CASE_MASK1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_BIT_STEP_DELTA_MASK1 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_STEP_RANGE_EDGE_MASK1 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_NO_INCREASE_MASK1 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_1D_EYE_NOISE_MASK1 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_BAD_BIT_MASK1 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_MAX_RANGE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_MIN_RANGE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_TWO_RANGE_BEST_CASE = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_BIT_STEP_DELTA = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_STEP_RANGE_EDGE = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_NO_INCREASE = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_1D_EYE_NOISE = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_BAD_BIT = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_MAX_RANGE_MASK1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_MIN_RANGE_MASK1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_TWO_RANGE_BEST_CASE_MASK1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_BIT_STEP_DELTA_MASK1 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_STEP_RANGE_EDGE_MASK1 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_NO_INCREASE_MASK1 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_1D_EYE_NOISE_MASK1 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_BAD_BIT_MASK1 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_MAX_RANGE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_MIN_RANGE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_TWO_RANGE_BEST_CASE = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_BIT_STEP_DELTA = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_STEP_RANGE_EDGE = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_NO_INCREASE = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_1D_EYE_NOISE = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_BAD_BIT = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_MAX_RANGE_MASK1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_MIN_RANGE_MASK1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_TWO_RANGE_BEST_CASE_MASK1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_BIT_STEP_DELTA_MASK1 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_STEP_RANGE_EDGE_MASK1 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_NO_INCREASE_MASK1 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_1D_EYE_NOISE_MASK1 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_BAD_BIT_MASK1 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_MAX_RANGE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_MIN_RANGE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_TWO_RANGE_BEST_CASE = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_BIT_STEP_DELTA = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_STEP_RANGE_EDGE = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_NO_INCREASE = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_1D_EYE_NOISE = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_BAD_BIT = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_MAX_RANGE_MASK1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_MIN_RANGE_MASK1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_TWO_RANGE_BEST_CASE_MASK1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_BIT_STEP_DELTA_MASK1 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_STEP_RANGE_EDGE_MASK1 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_NO_INCREASE_MASK1 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_1D_EYE_NOISE_MASK1 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_BAD_BIT_MASK1 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_MAX_RANGE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_MIN_RANGE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_TWO_RANGE_BEST_CASE = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_BIT_STEP_DELTA = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_STEP_RANGE_EDGE = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_NO_INCREASE = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_1D_EYE_NOISE = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_BAD_BIT = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_MAX_RANGE_MASK1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_MIN_RANGE_MASK1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_TWO_RANGE_BEST_CASE_MASK1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_BIT_STEP_DELTA_MASK1 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_STEP_RANGE_EDGE_MASK1 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_NO_INCREASE_MASK1 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_1D_EYE_NOISE_MASK1 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_BAD_BIT_MASK1 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_MAX_RANGE_MASK2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_MIN_RANGE_MASK2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_TWO_RANGE_BEST_CASE_MASK2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_BIT_STEP_DELTA_MASK2 = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_STEP_RANGE_EDGE_MASK2 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_NO_INCREASE_MASK2 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_1D_EYE_NOISE_MASK2 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_BAD_BIT_MASK2 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_MAX_RANGE_MASK3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_MIN_RANGE_MASK3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_TWO_RANGE_BEST_CASE_MASK3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_BIT_STEP_DELTA_MASK3 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_STEP_RANGE_EDGE_MASK3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_NO_INCREASE_MASK3 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_1D_EYE_NOISE_MASK3 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_BAD_BIT_MASK3 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_MAX_RANGE_MASK2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_MIN_RANGE_MASK2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_TWO_RANGE_BEST_CASE_MASK2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_BIT_STEP_DELTA_MASK2 = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_STEP_RANGE_EDGE_MASK2 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_NO_INCREASE_MASK2 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_1D_EYE_NOISE_MASK2 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_BAD_BIT_MASK2 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_MAX_RANGE_MASK3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_MIN_RANGE_MASK3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_TWO_RANGE_BEST_CASE_MASK3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_BIT_STEP_DELTA_MASK3 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_STEP_RANGE_EDGE_MASK3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_NO_INCREASE_MASK3 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_1D_EYE_NOISE_MASK3 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_BAD_BIT_MASK3 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_MAX_RANGE_MASK2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_MIN_RANGE_MASK2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_TWO_RANGE_BEST_CASE_MASK2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_BIT_STEP_DELTA_MASK2 = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_STEP_RANGE_EDGE_MASK2 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_NO_INCREASE_MASK2 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_1D_EYE_NOISE_MASK2 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_BAD_BIT_MASK2 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_MAX_RANGE_MASK3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_MIN_RANGE_MASK3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_TWO_RANGE_BEST_CASE_MASK3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_BIT_STEP_DELTA_MASK3 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_STEP_RANGE_EDGE_MASK3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_NO_INCREASE_MASK3 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_1D_EYE_NOISE_MASK3 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_BAD_BIT_MASK3 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_MAX_RANGE_MASK2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_MIN_RANGE_MASK2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_TWO_RANGE_BEST_CASE_MASK2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_BIT_STEP_DELTA_MASK2 = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_STEP_RANGE_EDGE_MASK2 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_NO_INCREASE_MASK2 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_1D_EYE_NOISE_MASK2 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_BAD_BIT_MASK2 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_MAX_RANGE_MASK3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_MIN_RANGE_MASK3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_TWO_RANGE_BEST_CASE_MASK3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_BIT_STEP_DELTA_MASK3 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_STEP_RANGE_EDGE_MASK3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_NO_INCREASE_MASK3 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_1D_EYE_NOISE_MASK3 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_BAD_BIT_MASK3 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_MAX_RANGE_MASK2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_MIN_RANGE_MASK2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_TWO_RANGE_BEST_CASE_MASK2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_BIT_STEP_DELTA_MASK2 = 51 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_STEP_RANGE_EDGE_MASK2 = 52 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_NO_INCREASE_MASK2 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_1D_EYE_NOISE_MASK2 = 54 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_BAD_BIT_MASK2 = 55 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_MAX_RANGE_MASK3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_MIN_RANGE_MASK3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_TWO_RANGE_BEST_CASE_MASK3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_BIT_STEP_DELTA_MASK3 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_STEP_RANGE_EDGE_MASK3 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_NO_INCREASE_MASK3 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_1D_EYE_NOISE_MASK3 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_BAD_BIT_MASK3 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_0_01_CTR_NUM_WRRDREQ_CNT = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_0_01_CTR_NUM_WRRDREQ_CNT_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_1_01_CTR_NUM_WRRDREQ_CNT = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_1_01_CTR_NUM_WRRDREQ_CNT_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_2_23_CTR_NUM_WRRDREQ_CNT = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_2_23_CTR_NUM_WRRDREQ_CNT_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_3_23_CTR_NUM_WRRDREQ_CNT = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_3_23_CTR_NUM_WRRDREQ_CNT_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_4_4_CTR_NUM_WRRDREQ_CNT = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_4_4_CTR_NUM_WRRDREQ_CNT_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_0_01_CTR_NUM_VREFREQ_CNT = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_0_01_CTR_NUM_VREFREQ_CNT_LEN = 9 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_0_01_CTR_CUR = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_0_01_CTR_CUR_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_1_01_CTR_NUM_VREFREQ_CNT = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_1_01_CTR_NUM_VREFREQ_CNT_LEN = 9 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_1_01_CTR_CUR = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_1_01_CTR_CUR_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_2_23_CTR_NUM_VREFREQ_CNT = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_2_23_CTR_NUM_VREFREQ_CNT_LEN = 9 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_2_23_CTR_CUR = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_2_23_CTR_CUR_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_3_23_CTR_NUM_VREFREQ_CNT = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_3_23_CTR_NUM_VREFREQ_CNT_LEN = 9 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_3_23_CTR_CUR = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_3_23_CTR_CUR_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_4_4_CTR_NUM_VREFREQ_CNT = 48 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_4_4_CTR_NUM_VREFREQ_CNT_LEN = 9 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_4_4_CTR_CUR = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_4_4_CTR_CUR_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0_01_RANGE_DRAM0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0_01_VALUE_DRAM0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0_01_VALUE_DRAM0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0_01_RANGE_DRAM1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0_01_VALUE_DRAM1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0_01_VALUE_DRAM1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_1_01_RANGE_DRAM0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_1_01_VALUE_DRAM0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_1_01_VALUE_DRAM0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_1_01_RANGE_DRAM1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_1_01_VALUE_DRAM1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_1_01_VALUE_DRAM1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_2_23_RANGE_DRAM0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_2_23_VALUE_DRAM0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_2_23_VALUE_DRAM0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_2_23_RANGE_DRAM1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_2_23_VALUE_DRAM1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_2_23_VALUE_DRAM1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_3_23_RANGE_DRAM0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_3_23_VALUE_DRAM0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_3_23_VALUE_DRAM0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_3_23_RANGE_DRAM1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_3_23_VALUE_DRAM1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_3_23_VALUE_DRAM1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_4_4_RANGE_DRAM0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_4_4_VALUE_DRAM0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_4_4_VALUE_DRAM0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_4_4_RANGE_DRAM1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_4_4_VALUE_DRAM1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_4_4_VALUE_DRAM1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_0_01_RANGE_DRAM0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_0_01_VALUE_DRAM0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_0_01_VALUE_DRAM0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_0_01_RANGE_DRAM1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_0_01_VALUE_DRAM1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_0_01_VALUE_DRAM1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_1_01_RANGE_DRAM0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_1_01_VALUE_DRAM0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_1_01_VALUE_DRAM0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_1_01_RANGE_DRAM1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_1_01_VALUE_DRAM1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_1_01_VALUE_DRAM1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_2_23_RANGE_DRAM0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_2_23_VALUE_DRAM0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_2_23_VALUE_DRAM0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_2_23_RANGE_DRAM1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_2_23_VALUE_DRAM1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_2_23_VALUE_DRAM1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_3_23_RANGE_DRAM0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_3_23_VALUE_DRAM0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_3_23_VALUE_DRAM0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_3_23_RANGE_DRAM1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_3_23_VALUE_DRAM1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_3_23_VALUE_DRAM1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_4_4_RANGE_DRAM0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_4_4_VALUE_DRAM0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_4_4_VALUE_DRAM0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_4_4_RANGE_DRAM1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_4_4_VALUE_DRAM1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_4_4_VALUE_DRAM1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_0_01_RANGE_DRAM0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_0_01_VALUE_DRAM0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_0_01_VALUE_DRAM0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_0_01_RANGE_DRAM1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_0_01_VALUE_DRAM1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_0_01_VALUE_DRAM1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_1_01_RANGE_DRAM0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_1_01_VALUE_DRAM0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_1_01_VALUE_DRAM0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_1_01_RANGE_DRAM1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_1_01_VALUE_DRAM1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_1_01_VALUE_DRAM1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_2_23_RANGE_DRAM0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_2_23_VALUE_DRAM0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_2_23_VALUE_DRAM0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_2_23_RANGE_DRAM1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_2_23_VALUE_DRAM1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_2_23_VALUE_DRAM1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_3_23_RANGE_DRAM0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_3_23_VALUE_DRAM0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_3_23_VALUE_DRAM0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_3_23_RANGE_DRAM1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_3_23_VALUE_DRAM1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_3_23_VALUE_DRAM1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_4_4_RANGE_DRAM0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_4_4_VALUE_DRAM0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_4_4_VALUE_DRAM0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_4_4_RANGE_DRAM1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_4_4_VALUE_DRAM1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_4_4_VALUE_DRAM1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_0_01_RANGE_DRAM0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_0_01_VALUE_DRAM0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_0_01_VALUE_DRAM0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_0_01_RANGE_DRAM1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_0_01_VALUE_DRAM1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_0_01_VALUE_DRAM1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_1_01_RANGE_DRAM0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_1_01_VALUE_DRAM0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_1_01_VALUE_DRAM0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_1_01_RANGE_DRAM1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_1_01_VALUE_DRAM1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_1_01_VALUE_DRAM1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_2_23_RANGE_DRAM0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_2_23_VALUE_DRAM0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_2_23_VALUE_DRAM0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_2_23_RANGE_DRAM1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_2_23_VALUE_DRAM1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_2_23_VALUE_DRAM1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_3_23_RANGE_DRAM0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_3_23_VALUE_DRAM0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_3_23_VALUE_DRAM0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_3_23_RANGE_DRAM1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_3_23_VALUE_DRAM1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_3_23_VALUE_DRAM1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_4_4_RANGE_DRAM0 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_4_4_VALUE_DRAM0 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_4_4_VALUE_DRAM0_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_4_4_RANGE_DRAM1 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_4_4_VALUE_DRAM1 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_4_4_VALUE_DRAM1_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_0_01_RANGE_DRAM2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_0_01_VALUE_DRAM2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_0_01_VALUE_DRAM2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_0_01_RANGE_DRAM3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_0_01_VALUE_DRAM3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_0_01_VALUE_DRAM3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_1_01_RANGE_DRAM2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_1_01_VALUE_DRAM2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_1_01_VALUE_DRAM2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_1_01_RANGE_DRAM3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_1_01_VALUE_DRAM3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_1_01_VALUE_DRAM3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_2_23_RANGE_DRAM2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_2_23_VALUE_DRAM2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_2_23_VALUE_DRAM2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_2_23_RANGE_DRAM3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_2_23_VALUE_DRAM3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_2_23_VALUE_DRAM3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_3_23_RANGE_DRAM2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_3_23_VALUE_DRAM2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_3_23_VALUE_DRAM2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_3_23_RANGE_DRAM3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_3_23_VALUE_DRAM3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_3_23_VALUE_DRAM3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_4_4_RANGE_DRAM2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_4_4_VALUE_DRAM2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_4_4_VALUE_DRAM2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_4_4_RANGE_DRAM3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_4_4_VALUE_DRAM3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_4_4_VALUE_DRAM3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_0_01_RANGE_DRAM2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_0_01_VALUE_DRAM2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_0_01_VALUE_DRAM2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_0_01_RANGE_DRAM3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_0_01_VALUE_DRAM3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_0_01_VALUE_DRAM3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_1_01_RANGE_DRAM2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_1_01_VALUE_DRAM2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_1_01_VALUE_DRAM2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_1_01_RANGE_DRAM3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_1_01_VALUE_DRAM3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_1_01_VALUE_DRAM3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_2_23_RANGE_DRAM2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_2_23_VALUE_DRAM2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_2_23_VALUE_DRAM2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_2_23_RANGE_DRAM3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_2_23_VALUE_DRAM3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_2_23_VALUE_DRAM3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_3_23_RANGE_DRAM2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_3_23_VALUE_DRAM2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_3_23_VALUE_DRAM2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_3_23_RANGE_DRAM3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_3_23_VALUE_DRAM3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_3_23_VALUE_DRAM3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_4_4_RANGE_DRAM2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_4_4_VALUE_DRAM2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_4_4_VALUE_DRAM2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_4_4_RANGE_DRAM3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_4_4_VALUE_DRAM3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_4_4_VALUE_DRAM3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_0_01_RANGE_DRAM2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_0_01_VALUE_DRAM2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_0_01_VALUE_DRAM2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_0_01_RANGE_DRAM3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_0_01_VALUE_DRAM3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_0_01_VALUE_DRAM3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_1_01_RANGE_DRAM2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_1_01_VALUE_DRAM2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_1_01_VALUE_DRAM2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_1_01_RANGE_DRAM3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_1_01_VALUE_DRAM3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_1_01_VALUE_DRAM3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_2_23_RANGE_DRAM2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_2_23_VALUE_DRAM2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_2_23_VALUE_DRAM2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_2_23_RANGE_DRAM3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_2_23_VALUE_DRAM3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_2_23_VALUE_DRAM3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_3_23_RANGE_DRAM2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_3_23_VALUE_DRAM2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_3_23_VALUE_DRAM2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_3_23_RANGE_DRAM3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_3_23_VALUE_DRAM3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_3_23_VALUE_DRAM3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_4_4_RANGE_DRAM2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_4_4_VALUE_DRAM2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_4_4_VALUE_DRAM2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_4_4_RANGE_DRAM3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_4_4_VALUE_DRAM3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_4_4_VALUE_DRAM3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_0_01_RANGE_DRAM2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_0_01_VALUE_DRAM2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_0_01_VALUE_DRAM2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_0_01_RANGE_DRAM3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_0_01_VALUE_DRAM3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_0_01_VALUE_DRAM3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_1_01_RANGE_DRAM2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_1_01_VALUE_DRAM2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_1_01_VALUE_DRAM2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_1_01_RANGE_DRAM3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_1_01_VALUE_DRAM3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_1_01_VALUE_DRAM3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_2_23_RANGE_DRAM2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_2_23_VALUE_DRAM2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_2_23_VALUE_DRAM2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_2_23_RANGE_DRAM3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_2_23_VALUE_DRAM3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_2_23_VALUE_DRAM3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_3_23_RANGE_DRAM2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_3_23_VALUE_DRAM2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_3_23_VALUE_DRAM2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_3_23_RANGE_DRAM3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_3_23_VALUE_DRAM3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_3_23_VALUE_DRAM3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_4_4_RANGE_DRAM2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_4_4_VALUE_DRAM2 = 50 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_4_4_VALUE_DRAM2_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_4_4_RANGE_DRAM3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_4_4_VALUE_DRAM3 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_4_4_VALUE_DRAM3_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_PC_BASE_CNTR0_P0_PERIODIC = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_BASE_CNTR0_P0_PERIODIC_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_PC_BASE_CNTR1_P0_PERIODIC = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_BASE_CNTR1_P0_PERIODIC_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_PC_CAL_TIMER_P0_PERIODIC = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_CAL_TIMER_P0_PERIODIC_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE_P0_PERIODIC = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE_P0_PERIODIC_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG0_P0_PDA_ENABLE_OVERRIDE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG0_P0_PDA_ENABLE_OVERRIDE_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG0_P0_TCK_PREAMBLE_ENABLE = 52 ; static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG0_P0_PBA_ENABLE = 53 ; static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG0_P0_DDR4_CMD_SIG_REDUCTION = 54 ; static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG0_P0_SYSCLK_2X_MEMINTCLKO = 55 ; static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG0_P0_RANK_OVERRIDE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG0_P0_RANK_OVERRIDE_VALUE = 57 ; static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG0_P0_RANK_OVERRIDE_VALUE_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG0_P0_LOW_LATENCY = 60 ; static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG0_P0_DDR4_IPW_LOOP_DIS = 61 ; static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG0_P0_DDR4_VLEVEL_BANK_GROUP = 62 ; static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG0_P0_VPROTH_PSEL_MODE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG1_P0_WRITE_LATENCY_OFFSET = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG1_P0_WRITE_LATENCY_OFFSET_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG1_P0_READ_LATENCY_OFFSET = 52 ; static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG1_P0_READ_LATENCY_OFFSET_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG1_P0_MEMCTL_CIC_FAST = 56 ; static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG1_P0_MEMCTL_CTRN_IGNORE = 57 ; static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG1_P0_DISABLE_MEMCTL_CAL = 58 ; static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG1_P0_MEMORY_TYPE = 59 ; static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG1_P0_MEMORY_TYPE_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG1_P0_DDR4_LATENCY_SW = 62 ; static const uint8_t P9N2_MCA_DDRPHY_PC_CONFIG1_P0_RETRAIN_PERCAL_SW = 63 ; static const uint8_t P9N2_MCA_DDRPHY_PC_CSID_CFG_P0_CS0_INIT_CAL_VALUE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_CSID_CFG_P0_CS1_INIT_CAL_VALUE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_PC_CSID_CFG_P0_CS2_INIT_CAL_VALUE = 50 ; static const uint8_t P9N2_MCA_DDRPHY_PC_CSID_CFG_P0_CS3_INIT_CAL_VALUE = 51 ; static const uint8_t P9N2_MCA_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P0_DP_GOOD = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P0_DP_ERROR = 49 ; static const uint8_t P9N2_MCA_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P0_DP_ERROR_FINE = 50 ; static const uint8_t P9N2_MCA_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P0_ADR_GOOD = 51 ; static const uint8_t P9N2_MCA_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P0_ADR_ERROR = 52 ; static const uint8_t P9N2_MCA_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P0_ADR_ERROR_FINE = 53 ; static const uint8_t P9N2_MCA_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P0_DONE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_PC_ERROR_MASK0_P0_RC_MASK = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_ERROR_MASK0_P0_WC_MASK = 49 ; static const uint8_t P9N2_MCA_DDRPHY_PC_ERROR_MASK0_P0_SEQ_MASK = 50 ; static const uint8_t P9N2_MCA_DDRPHY_PC_ERROR_MASK0_P0_APB_MASK = 52 ; static const uint8_t P9N2_MCA_DDRPHY_PC_ERROR_MASK0_P0_MASK = 53 ; static const uint8_t P9N2_MCA_DDRPHY_PC_ERROR_STATUS0_P0_RC = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_ERROR_STATUS0_P0_WC = 49 ; static const uint8_t P9N2_MCA_DDRPHY_PC_ERROR_STATUS0_P0_SEQ = 50 ; static const uint8_t P9N2_MCA_DDRPHY_PC_ERROR_STATUS0_P0_RESERVED_51 = 51 ; static const uint8_t P9N2_MCA_DDRPHY_PC_ERROR_STATUS0_P0_APB = 52 ; static const uint8_t P9N2_MCA_DDRPHY_PC_ERROR_STATUS0_P0_ERROR = 53 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_WR_LEVEL = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_INITIAL_PAT_WR = 49 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_DQS_ALIGN = 50 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_RDCLK_ALIGN = 51 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_READ_CTR = 52 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_WRITE_CTR = 53 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_INITIAL_COARSE_WR = 54 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_COARSE_RD = 55 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_CUSTOM_RD = 56 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_CUSTOM_WR = 57 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ABORT_ON_ERROR = 58 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_DIGITAL_EYE = 59 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_RANK_PAIR = 60 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_RANK_PAIR_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_REFRESH_COUNT = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_REFRESH_COUNT_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_REFRESH_CONTROL = 52 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_REFRESH_CONTROL_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_REFRESH_ALL_RANKS = 54 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_CMD_SNOOP_DIS = 55 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_MRS_SNOOP_DIS = 56 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_REFRESH_INTERVAL = 57 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_REFRESH_INTERVAL_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_WR_LEVEL = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_INITIAL_PAT_WRITE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_DQS_ALIGN = 50 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_RDCLK_ALIGN = 51 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_READ_CTR = 52 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_WRITE_CTR = 53 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_INITIAL_COARSE_WR = 54 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_COARSE_RD = 55 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_CUSTOM_RD = 56 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_CUSTOM_WR = 57 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_DIGITAL_EYE = 58 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_VREF = 59 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_RANK_PAIR = 60 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_RANK_PAIR_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_WR_LEVEL = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_INITIAL_PAT_WRITE = 49 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_DQS_ALIGN = 50 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_RDCLK_ALIGN = 51 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_READ_CTR = 52 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_WRITE_CTR = 53 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_INITIAL_COARSE_WR = 54 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_COARSE_RD = 55 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_CUSTOM_RD = 56 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_CUSTOM_WR = 57 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_DIGITAL_EYE = 58 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_VREF = 59 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_STATUS_P0_COMPLETE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_STATUS_P0_COMPLETE_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_STATUS_P0_DFI_REQ_STATE = 52 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_STATUS_P0_DFI_REQ_STATE_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_STATUS_P0_PER_PEND_OVRFLW = 56 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_STATUS_P0_PER_ABORT = 57 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_STATUS_P0_RESERVED_58 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_STATUS_P0_ICAL_STATE = 59 ; static const uint8_t P9N2_MCA_DDRPHY_PC_INIT_CAL_STATUS_P0_ICAL_STATE_LEN = 5 ; static const uint8_t P9N2_MCA_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_PVTPB = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_PVTPL = 49 ; static const uint8_t P9N2_MCA_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_PVTPL_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_PVTNB = 56 ; static const uint8_t P9N2_MCA_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_PVTNL = 57 ; static const uint8_t P9N2_MCA_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_PVTNL_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_PC_IO_PVT_FET_STATUS_P0_PVTPB = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_IO_PVT_FET_STATUS_P0_PVTPL = 49 ; static const uint8_t P9N2_MCA_DDRPHY_PC_IO_PVT_FET_STATUS_P0_PVTPL_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_PC_IO_PVT_FET_STATUS_P0_PVTNB = 56 ; static const uint8_t P9N2_MCA_DDRPHY_PC_IO_PVT_FET_STATUS_P0_PVTNL = 57 ; static const uint8_t P9N2_MCA_DDRPHY_PC_IO_PVT_FET_STATUS_P0_PVTNL_LEN = 7 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MIRROR_CONFIG_P0_ADDR_RP0_PRI = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MIRROR_CONFIG_P0_ADDR_RP0_SEC = 49 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MIRROR_CONFIG_P0_ADDR_RP1_PRI = 50 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MIRROR_CONFIG_P0_ADDR_RP1_SEC = 51 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MIRROR_CONFIG_P0_ADDR_RP2_PRI = 52 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MIRROR_CONFIG_P0_ADDR_RP2_SEC = 53 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MIRROR_CONFIG_P0_ADDR_RP3_PRI = 54 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MIRROR_CONFIG_P0_ADDR_RP3_SEC = 55 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MIRROR_CONFIG_P0_ADDR_A3_A4 = 58 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MIRROR_CONFIG_P0_ADDR_A5_A6 = 59 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MIRROR_CONFIG_P0_ADDR_A7_A8 = 60 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MIRROR_CONFIG_P0_ADDR_A11_A13 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MIRROR_CONFIG_P0_ADDR_BA0_BA1 = 62 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MIRROR_CONFIG_P0_ADDR_BG0_BG1 = 63 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR0_RP0_P0_MODE_REGISTER_0_VALUE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR0_RP0_P0_MODE_REGISTER_0_VALUE_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR0_RP1_P0_MODE_REGISTER_0_VALUE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR0_RP1_P0_MODE_REGISTER_0_VALUE_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR0_RP2_P0_MODE_REGISTER_0_VALUE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR0_RP2_P0_MODE_REGISTER_0_VALUE_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR0_RP3_P0_MODE_REGISTER_0_VALUE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR0_RP3_P0_MODE_REGISTER_0_VALUE_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR1_RP0_P0_MODE_REGISTER_1_VALUE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR1_RP0_P0_MODE_REGISTER_1_VALUE_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR1_RP1_P0_MODE_REGISTER_1_VALUE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR1_RP1_P0_MODE_REGISTER_1_VALUE_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR1_RP2_P0_MODE_REGISTER_1_VALUE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR1_RP2_P0_MODE_REGISTER_1_VALUE_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR1_RP3_P0_MODE_REGISTER_1_VALUE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR1_RP3_P0_MODE_REGISTER_1_VALUE_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR2_RP0_P0_MODE_REGISTER_2_VALUE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR2_RP0_P0_MODE_REGISTER_2_VALUE_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR2_RP1_P0_MODE_REGISTER_2_VALUE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR2_RP1_P0_MODE_REGISTER_2_VALUE_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR2_RP2_P0_MODE_REGISTER_2_VALUE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR2_RP2_P0_MODE_REGISTER_2_VALUE_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR2_RP3_P0_MODE_REGISTER_2_VALUE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR2_RP3_P0_MODE_REGISTER_2_VALUE_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR3_RP0_P0_MODE_REGISTER_3_VALUE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR3_RP0_P0_MODE_REGISTER_3_VALUE_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR3_RP1_P0_MODE_REGISTER_3_VALUE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR3_RP1_P0_MODE_REGISTER_3_VALUE_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR3_RP2_P0_MODE_REGISTER_3_VALUE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR3_RP2_P0_MODE_REGISTER_3_VALUE_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR3_RP3_P0_MODE_REGISTER_3_VALUE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR3_RP3_P0_MODE_REGISTER_3_VALUE_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR4_RP0_P0_MODE_REGISTER_4_VALUE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR4_RP0_P0_MODE_REGISTER_4_VALUE_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR4_RP1_P0_MODE_REGISTER_4_VALUE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR4_RP1_P0_MODE_REGISTER_4_VALUE_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR4_RP2_P0_MODE_REGISTER_4_VALUE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR4_RP2_P0_MODE_REGISTER_4_VALUE_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR4_RP3_P0_MODE_REGISTER_4_VALUE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR4_RP3_P0_MODE_REGISTER_4_VALUE_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR5_RP0_P0_MODE_REGISTER_5_VALUE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR5_RP0_P0_MODE_REGISTER_5_VALUE_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR5_RP1_P0_MODE_REGISTER_5_VALUE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR5_RP1_P0_MODE_REGISTER_5_VALUE_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR5_RP2_P0_MODE_REGISTER_5_VALUE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR5_RP2_P0_MODE_REGISTER_5_VALUE_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR5_RP3_P0_MODE_REGISTER_5_VALUE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR5_RP3_P0_MODE_REGISTER_5_VALUE_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR6_RP0_P0_MODE_REGISTER_6_VALUE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR6_RP0_P0_MODE_REGISTER_6_VALUE_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR6_RP1_P0_MODE_REGISTER_6_VALUE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR6_RP1_P0_MODE_REGISTER_6_VALUE_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR6_RP2_P0_MODE_REGISTER_6_VALUE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR6_RP2_P0_MODE_REGISTER_6_VALUE_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR6_RP3_P0_MODE_REGISTER_6_VALUE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR6_RP3_P0_MODE_REGISTER_6_VALUE_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR7_RP0_P0_MODE_REGISTER_7_VALUE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR7_RP0_P0_MODE_REGISTER_7_VALUE_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR7_RP1_P0_MODE_REGISTER_7_VALUE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR7_RP1_P0_MODE_REGISTER_7_VALUE_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR7_RP2_P0_MODE_REGISTER_7_VALUE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR7_RP2_P0_MODE_REGISTER_7_VALUE_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR7_RP3_P0_MODE_REGISTER_7_VALUE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_MR7_RP3_P0_MODE_REGISTER_7_VALUE_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_PC_PBA_CONTROL_P0_SNOOPED_F0RC4X_BIT4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_PBA_CONTROL_P0_PHY_CSN_MAP = 49 ; static const uint8_t P9N2_MCA_DDRPHY_PC_PBA_CONTROL_P0_PHY_CSN_MAP_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_ENA_RANK_PAIR = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_ENA_RANK_PAIR_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_ENA_ZCAL = 52 ; static const uint8_t P9N2_MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_ENA_SYSCLK_ALIGN = 53 ; static const uint8_t P9N2_MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_ENA_READ_CTR = 54 ; static const uint8_t P9N2_MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_ENA_RDCLK_ALIGN = 55 ; static const uint8_t P9N2_MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_ENA_DQS_ALIGN = 56 ; static const uint8_t P9N2_MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_NEXT_RANK_PAIR = 57 ; static const uint8_t P9N2_MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_NEXT_RANK_PAIR_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_FAST_SIM_CNTR = 59 ; static const uint8_t P9N2_MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_START_INIT = 60 ; static const uint8_t P9N2_MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_START = 61 ; static const uint8_t P9N2_MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_ABORT_ON_ERR_EN = 62 ; static const uint8_t P9N2_MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_DD2_FIX_DIS = 63 ; static const uint8_t P9N2_MCA_DDRPHY_PC_PER_ERR_INJECT_P0_CA_PARITY = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_PER_ERR_INJECT_P0_HARD_ERROR = 49 ; static const uint8_t P9N2_MCA_DDRPHY_PC_PER_ERR_INJECT_P0_HAS_FIRED = 50 ; static const uint8_t P9N2_MCA_DDRPHY_PC_PER_ERR_INJECT_P0_RECUR_ERROR = 51 ; static const uint8_t P9N2_MCA_DDRPHY_PC_PER_ERR_INJECT_P0_CONFIG_CNT = 52 ; static const uint8_t P9N2_MCA_DDRPHY_PC_PER_ERR_INJECT_P0_CONFIG_CNT_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_PC_PER_ERR_INJECT_P0_EN_PARITY_ERROR = 58 ; static const uint8_t P9N2_MCA_DDRPHY_PC_PER_ERR_INJECT_P0_ERROR_THROWN_COUNT = 59 ; static const uint8_t P9N2_MCA_DDRPHY_PC_PER_ERR_INJECT_P0_ERROR_THROWN_COUNT_LEN = 5 ; static const uint8_t P9N2_MCA_DDRPHY_PC_PER_ZCAL_CONFIG_P0_ENA_RANK = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_PER_ZCAL_CONFIG_P0_ENA_RANK_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_PC_PER_ZCAL_CONFIG_P0_NEXT_RANK = 56 ; static const uint8_t P9N2_MCA_DDRPHY_PC_PER_ZCAL_CONFIG_P0_NEXT_RANK_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_PC_PER_ZCAL_CONFIG_P0_START = 59 ; static const uint8_t P9N2_MCA_DDRPHY_PC_POWERDOWN_1_P0_MASTER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_POWERDOWN_1_P0_DLL = 49 ; static const uint8_t P9N2_MCA_DDRPHY_PC_POWERDOWN_1_P0_DLL_CLOCK_GATE = 50 ; static const uint8_t P9N2_MCA_DDRPHY_PC_POWERDOWN_1_P0_DQS = 51 ; static const uint8_t P9N2_MCA_DDRPHY_PC_POWERDOWN_1_P0_VPROTH = 52 ; static const uint8_t P9N2_MCA_DDRPHY_PC_POWERDOWN_1_P0_KPRIME = 53 ; static const uint8_t P9N2_MCA_DDRPHY_PC_POWERDOWN_1_P0_PORTPOWERDOWN = 54 ; static const uint8_t P9N2_MCA_DDRPHY_PC_POWERDOWN_1_P0_ANALOG_INPUT_STAB = 55 ; static const uint8_t P9N2_MCA_DDRPHY_PC_POWERDOWN_1_P0_ZCAL = 56 ; static const uint8_t P9N2_MCA_DDRPHY_PC_POWERDOWN_1_P0_DELAY_LINE_CTL_OVERRIDE = 57 ; static const uint8_t P9N2_MCA_DDRPHY_PC_POWERDOWN_1_P0_WR_FIFO_STAB = 58 ; static const uint8_t P9N2_MCA_DDRPHY_PC_POWERDOWN_1_P0_RX = 60 ; static const uint8_t P9N2_MCA_DDRPHY_PC_POWERDOWN_1_P0_DP_TX_TRISTATE = 61 ; static const uint8_t P9N2_MCA_DDRPHY_PC_POWERDOWN_1_P0_ADR_TX_TRISTATE = 62 ; static const uint8_t P9N2_MCA_DDRPHY_PC_POWERDOWN_1_P0_VREG_S = 63 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP0_TER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP0_QUA = 49 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP1_TER = 50 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP1_QUA = 51 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP2_TER = 52 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP2_QUA = 53 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP3_TER = 54 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP3_QUA = 55 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR0_P0_PRI = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR0_P0_PRI_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR0_P0_PRI_V = 51 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR0_P0_SEC = 52 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR0_P0_SEC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR0_P0_SEC_V = 55 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR0_P0_PAIR1_PRI = 56 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR0_P0_PAIR1_PRI_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR0_P0_PAIR1_PRI_V = 59 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR0_P0_PAIR1_SEC = 60 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR0_P0_PAIR1_SEC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR0_P0_PAIR1_SEC_V = 63 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR2_PRI = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR2_PRI_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR2_PRI_V = 51 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR2_SEC = 52 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR2_SEC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR2_SEC_V = 55 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR3_PRI = 56 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR3_PRI_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR3_PRI_V = 59 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR3_SEC = 60 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR3_SEC_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR3_SEC_V = 63 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR0_TER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR0_TER_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR0_TER_V = 51 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR0_QUA = 52 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR0_QUA_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR0_QUA_V = 55 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR1_TER = 56 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR1_TER_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR1_TER_V = 59 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR1_QUA = 60 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR1_QUA_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR1_QUA_V = 63 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR3_P0_PAIR2_TER = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR3_P0_PAIR2_TER_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR3_P0_PAIR2_TER_V = 51 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR3_P0_PAIR2_QUA = 52 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR3_P0_PAIR2_QUA_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR3_P0_PAIR2_QUA_V = 55 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR3_P0_TER = 56 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR3_P0_TER_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR3_P0_TER_V = 59 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR3_P0_QUA = 60 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR3_P0_QUA_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RANK_PAIR3_P0_QUA_V = 63 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RELOAD_VALUE0_P0_PERIODIC_CAL_REQ_EN = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RELOAD_VALUE0_P0_PERIODIC = 49 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RELOAD_VALUE0_P0_PERIODIC_LEN = 15 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RESETS_P0_SYSCLK_RESET = 49 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RESETS_P0_PVT_OVERRIDE = 50 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RESETS_P0_ENABLE_ZCAL = 51 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RESETS_P0_VREF_85PER = 52 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RESETS_P0_DD2_WR_PRE_DLY_EXT = 56 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RESETS_P0_DD2_ADR_CG_DISABLE = 57 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RESETS_P0_DD2_WC_CA_ERROR_DISABLE = 58 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RESETS_P0_DD2_CAL_REG_CG_DISABLE = 59 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RESETS_P0_DD2_CMDS_REG_CG_DISABLE = 60 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RESETS_P0_PBA_CW_F0RC06_DISABLE = 61 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RESETS_P0_DD2_RESET_READ_FIX_DISABLE = 62 ; static const uint8_t P9N2_MCA_DDRPHY_PC_RESETS_P0_DD2_BABG_INV_FIX_DISABLE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_PC_ZCAL_TIMER_P0_PERIODIC = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_ZCAL_TIMER_P0_PERIODIC_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE_P0_PERIODIC = 48 ; static const uint8_t P9N2_MCA_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE_P0_PERIODIC_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_RC_CONFIG0_P0_GLOBAL_PHY_OFFSET = 48 ; static const uint8_t P9N2_MCA_DDRPHY_RC_CONFIG0_P0_GLOBAL_PHY_OFFSET_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_RC_CONFIG0_P0_PER_DUTY_CYCLE_SW = 53 ; static const uint8_t P9N2_MCA_DDRPHY_RC_CONFIG0_P0_PER_REPEAT_COUNT = 54 ; static const uint8_t P9N2_MCA_DDRPHY_RC_CONFIG0_P0_PER_REPEAT_COUNT_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_RC_CONFIG0_P0_PERFORM_RDCLK_ALIGN = 62 ; static const uint8_t P9N2_MCA_DDRPHY_RC_CONFIG0_P0_STAGGERED_PATTERN = 63 ; static const uint8_t P9N2_MCA_DDRPHY_RC_CONFIG1_P0_OUTER_LOOP_CNT = 48 ; static const uint8_t P9N2_MCA_DDRPHY_RC_CONFIG1_P0_OUTER_LOOP_CNT_LEN = 14 ; static const uint8_t P9N2_MCA_DDRPHY_RC_CONFIG2_P0_CONSEC_PASS = 48 ; static const uint8_t P9N2_MCA_DDRPHY_RC_CONFIG2_P0_CONSEC_PASS_LEN = 5 ; static const uint8_t P9N2_MCA_DDRPHY_RC_CONFIG2_P0_ALLOW_RD_FIFO_AUTO_RESET = 59 ; static const uint8_t P9N2_MCA_DDRPHY_RC_CONFIG3_P0_FINE_CAL_STEP_SIZE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_RC_CONFIG3_P0_FINE_CAL_STEP_SIZE_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_RC_CONFIG3_P0_COARSE_CAL_STEP_SIZE = 51 ; static const uint8_t P9N2_MCA_DDRPHY_RC_CONFIG3_P0_COARSE_CAL_STEP_SIZE_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_RC_CONFIG3_P0_DQ_SEL_QUAD = 55 ; static const uint8_t P9N2_MCA_DDRPHY_RC_CONFIG3_P0_DQ_SEL_QUAD_LEN = 2 ; static const uint8_t P9N2_MCA_DDRPHY_RC_CONFIG3_P0_DQ_SEL_LANE = 57 ; static const uint8_t P9N2_MCA_DDRPHY_RC_CONFIG3_P0_DQ_SEL_LANE_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_RC_ERROR_MASK0_P0_RD_CNTL_MASK = 48 ; static const uint8_t P9N2_MCA_DDRPHY_RC_ERROR_STATUS0_P0_ERROR = 48 ; static const uint8_t P9N2_MCA_DDRPHY_RC_ERROR_STATUS0_P0_DP16 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_RC_ERROR_STATUS0_P0_CNTR_UNDERFLOW = 50 ; static const uint8_t P9N2_MCA_DDRPHY_RC_ERROR_STATUS0_P0_CNTR_OVERFLOW = 51 ; static const uint8_t P9N2_MCA_DDRPHY_RC_RDVREF_CONFIG0_P0_WAIT_TIME = 48 ; static const uint8_t P9N2_MCA_DDRPHY_RC_RDVREF_CONFIG0_P0_WAIT_TIME_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_RC_RDVREF_CONFIG1_P0_CMD_PRECEDE_TIME = 48 ; static const uint8_t P9N2_MCA_DDRPHY_RC_RDVREF_CONFIG1_P0_CMD_PRECEDE_TIME_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_RC_RDVREF_CONFIG1_P0_MPR_LOCATION = 56 ; static const uint8_t P9N2_MCA_DDRPHY_RC_RDVREF_CONFIG1_P0_MPR_LOCATION_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_RC_RDVREF_CONFIG1_P0_CALIBRATION_ENABLE = 60 ; static const uint8_t P9N2_MCA_DDRPHY_RC_RDVREF_CONFIG1_P0_SKIP_RDCENTERING = 61 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_CONFIG0_P0_MPR_PATTERN_BIT = 48 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_CONFIG0_P0_TWO_CYCLE_ADDR_EN = 49 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_CONFIG0_P0_MR_MASK_EN = 50 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_CONFIG0_P0_MR_MASK_EN_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_CONFIG0_P0_DELAYED_PAR = 54 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_CONFIG0_P0_LRDIMM_CONTEXT = 55 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_CONFIG0_P0_FORCE_RESERVED = 56 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_CONFIG0_P0_HALT_ROTATION = 57 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_CONFIG0_P0_PAR_INVERT = 60 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_CONFIG0_P0_IPW_SIDEAB_SEL = 61 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_CONFIG0_P0_PAR_17_MASK = 62 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_CONFIG0_P0_CW_MIRROR = 63 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ERROR_MASK0_P0_MULT_REQ_ERR_MASK = 48 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ERROR_MASK0_P0_INVALID_REQTYPE_ERR_MASK = 49 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ERROR_MASK0_P0_EARLY_REQ_ERR_MASK = 50 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ERROR_STATUS0_P0_MULTIPLE_REQ = 48 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ERROR_STATUS0_P0_EARLY_REQ = 50 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ERROR_STATUS0_P0_MULTIPLE_REQ_SOURCE = 51 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ERROR_STATUS0_P0_MULTIPLE_REQ_SOURCE_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ERROR_STATUS0_P0_INVALID_REQTYPE = 54 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ERROR_STATUS0_P0_INVALID_REQTYPE_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ERROR_STATUS0_P0_INVALID_REQ_SOURCE = 58 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ERROR_STATUS0_P0_INVALID_REQ_SOURCE_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ERROR_STATUS0_P0_EARLY_REQ_SOURCE = 61 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ERROR_STATUS0_P0_EARLY_REQ_SOURCE_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_LPT_ADDR2_P0_ADDR2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_LPT_ADDR2_P0_ADDR2_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_LPT_ADDR3_P0_ADDR3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_LPT_ADDR3_P0_ADDR3_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_LPT_ADDR4_P0_ADDR4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_LPT_ADDR4_P0_ADDR4_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TMOD_CYCLES = 48 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TMOD_CYCLES_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TRCD_CYCLES = 52 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TRCD_CYCLES_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TRP_CYCLES = 56 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TRP_CYCLES_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TRFC_CYCLES = 60 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TRFC_CYCLES_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TZQINIT_CYCLES = 48 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TZQINIT_CYCLES_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TZQCS_CYCLES = 52 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TZQCS_CYCLES_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TWLDQSEN_CYCLES = 56 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TWLDQSEN_CYCLES_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TWRMRD_CYCLES = 60 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TWRMRD_CYCLES_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0_TODTLON_OFF_CYCLES = 48 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0_TODTLON_OFF_CYCLES_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ODT_DEFAULT_CONFIG_P0_DEF_VALUES = 48 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ODT_DEFAULT_CONFIG_P0_DEF_VALUES_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ODT_RD_CONFIG0_P0_VALUES0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ODT_RD_CONFIG0_P0_VALUES0_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ODT_RD_CONFIG0_P0_VALUES1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ODT_RD_CONFIG0_P0_VALUES1_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ODT_RD_CONFIG1_P0_VALUES2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ODT_RD_CONFIG1_P0_VALUES2_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ODT_RD_CONFIG1_P0_VALUES3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ODT_RD_CONFIG1_P0_VALUES3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ODT_WR_CONFIG0_P0_VALUES0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ODT_WR_CONFIG0_P0_VALUES0_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ODT_WR_CONFIG0_P0_VALUES1 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ODT_WR_CONFIG0_P0_VALUES1_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ODT_WR_CONFIG1_P0_VALUES2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ODT_WR_CONFIG1_P0_VALUES2_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ODT_WR_CONFIG1_P0_VALUES3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ODT_WR_CONFIG1_P0_VALUES3_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_RD_WR_DATA0_P0_DATA_REG0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_RD_WR_DATA0_P0_DATA_REG0_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_RD_WR_DATA1_P0_DATA_REG1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_RD_WR_DATA1_P0_DATA_REG1_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_RESERVED_ADDR0_P0_ADDR0 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_RESERVED_ADDR0_P0_ADDR0_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_RESERVED_ADDR1_P0_ADDR1 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_RESERVED_ADDR1_P0_ADDR1_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_RESERVED_ADDR2_P0_ADDR2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_RESERVED_ADDR2_P0_ADDR2_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_RESERVED_ADDR3_P0_ADDR3 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_RESERVED_ADDR3_P0_ADDR3_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_RESERVED_ADDR4_P0_ADDR4 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_RESERVED_ADDR4_P0_ADDR4_LEN = 16 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_WR_TERM_SWAP0_P0_RTT_WR0_NOM_VALUE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_WR_TERM_SWAP0_P0_RTT_WR0_NOM_VALUE_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_WR_TERM_SWAP0_P0_RTT_WR1_NOM_VALUE = 51 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_WR_TERM_SWAP0_P0_RTT_WR1_NOM_VALUE_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_WR_TERM_SWAP0_P0_RTT_WR2_NOM_VALUE = 54 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_WR_TERM_SWAP0_P0_RTT_WR2_NOM_VALUE_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_WR_TERM_SWAP0_P0_RTT_WR3_NOM_VALUE = 57 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_WR_TERM_SWAP0_P0_RTT_WR3_NOM_VALUE_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_WR_TERM_SWAP0_P0_RTT_WR4_NOM_VALUE = 60 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_WR_TERM_SWAP0_P0_RTT_WR4_NOM_VALUE_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_WR_TERM_SWAP0_P0_DD2_VREF_FIX_DISABLE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_WR_TERM_SWAP1_P0_RTT_WR5_NOM_VALUE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_WR_TERM_SWAP1_P0_RTT_WR5_NOM_VALUE_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_WR_TERM_SWAP1_P0_RTT_WR6_NOM_VALUE = 51 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_WR_TERM_SWAP1_P0_RTT_WR6_NOM_VALUE_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_WR_TERM_SWAP1_P0_RTT_WR7_NOM_VALUE = 54 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_WR_TERM_SWAP1_P0_RTT_WR7_NOM_VALUE_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0_0_2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0_SEL_TYPE_0_2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0_SEL_0_2 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0_SEL_0_2_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0_1_3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0_SEL_TYPE_1_3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0_SEL_1_3 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0_SEL_1_3_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0_0_2 = 48 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0_SEL_TYPE_0_2 = 49 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0_SEL_0_2 = 53 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0_SEL_0_2_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0_1_3 = 56 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0_SEL_TYPE_1_3 = 57 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0_SEL_1_3 = 61 ; static const uint8_t P9N2_MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0_SEL_1_3_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG0_P0_TWLO_TWLOE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG0_P0_TWLO_TWLOE_LEN = 8 ; static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG0_P0_WL_ONE_DQS_PULSE = 56 ; static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG0_P0_FW_WR_RD = 57 ; static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG0_P0_FW_WR_RD_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG0_P0_CUSTOM_INIT_WRITE = 63 ; static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG1_P0_BIG_STEP = 48 ; static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG1_P0_BIG_STEP_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG1_P0_SMALL_STEP = 52 ; static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG1_P0_SMALL_STEP_LEN = 3 ; static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG1_P0_WR_PRE_DLY = 55 ; static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG1_P0_WR_PRE_DLY_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG2_P0_NUM_VALID_SAMPLES = 48 ; static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG2_P0_NUM_VALID_SAMPLES_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG2_P0_FW_RD_WR = 52 ; static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG2_P0_FW_RD_WR_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG2_P0_IPW_WR_WR = 58 ; static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG2_P0_IPW_WR_WR_LEN = 4 ; static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG2_P0_EN_RESET_DD2_FIX_DIS = 62 ; static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG2_P0_EN_RESET_WR_DELAY_WL = 63 ; static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG3_P0_PDA_RANKDELAY_ENABLE = 48 ; static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG3_P0_MRS_CMD_DQ_ON = 49 ; static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG3_P0_MRS_CMD_DQ_ON_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG3_P0_MRS_CMD_DQ_OFF = 55 ; static const uint8_t P9N2_MCA_DDRPHY_WC_CONFIG3_P0_MRS_CMD_DQ_OFF_LEN = 6 ; static const uint8_t P9N2_MCA_DDRPHY_WC_ERROR_MASK0_P0_WR_CNTL_MASK = 48 ; static const uint8_t P9N2_MCA_DDRPHY_WC_ERROR_STATUS0_P0_WR_CNTL = 48 ; static const uint8_t P9N2_MCA_DDRPHY_WC_RTT_WR_SWAP_ENABLE_P0_WL = 48 ; static const uint8_t P9N2_MCA_DDRPHY_WC_RTT_WR_SWAP_ENABLE_P0_CTR = 49 ; static const uint8_t P9N2_MCA_DDRPHY_WC_RTT_WR_SWAP_ENABLE_P0_CTR_VREF_COUNTER_RESET_VAL = 50 ; static const uint8_t P9N2_MCA_DDRPHY_WC_RTT_WR_SWAP_ENABLE_P0_CTR_VREF_COUNTER_RESET_VAL_LEN = 10 ; static const uint8_t P9N2_MCA_DQS0R_CFG_BYTE0_SWIZZLE = 0 ; static const uint8_t P9N2_MCA_DQS0R_CFG_BYTE0_SWIZZLE_LEN = 11 ; static const uint8_t P9N2_MCA_DQS0R_CFG_BYTE1_SWIZZLE = 11 ; static const uint8_t P9N2_MCA_DQS0R_CFG_BYTE1_SWIZZLE_LEN = 11 ; static const uint8_t P9N2_MCA_DQS0R_CFG_BYTE2_SWIZZLE = 22 ; static const uint8_t P9N2_MCA_DQS0R_CFG_BYTE2_SWIZZLE_LEN = 11 ; static const uint8_t P9N2_MCA_DQS0R_CFG_BYTE3_SWIZZLE = 33 ; static const uint8_t P9N2_MCA_DQS0R_CFG_BYTE3_SWIZZLE_LEN = 11 ; static const uint8_t P9N2_MCA_DQS0R_CFG_BYTE4_SWIZZLE = 44 ; static const uint8_t P9N2_MCA_DQS0R_CFG_BYTE4_SWIZZLE_LEN = 11 ; static const uint8_t P9N2_MCA_DQS1R_CFG_BYTE5_SWIZZLE = 0 ; static const uint8_t P9N2_MCA_DQS1R_CFG_BYTE5_SWIZZLE_LEN = 11 ; static const uint8_t P9N2_MCA_DQS1R_CFG_BYTE6_SWIZZLE = 11 ; static const uint8_t P9N2_MCA_DQS1R_CFG_BYTE6_SWIZZLE_LEN = 11 ; static const uint8_t P9N2_MCA_DQS1R_CFG_BYTE7_SWIZZLE = 22 ; static const uint8_t P9N2_MCA_DQS1R_CFG_BYTE7_SWIZZLE_LEN = 11 ; static const uint8_t P9N2_MCA_DQS1R_CFG_BYTE8_SWIZZLE = 33 ; static const uint8_t P9N2_MCA_DQS1R_CFG_BYTE8_SWIZZLE_LEN = 11 ; static const uint8_t P9N2_MCA_DQS1R_CFG_ODD_RANK_SWIZZLE_EN = 44 ; static const uint8_t P9N2_MCA_EICR_ADDRESS = 0 ; static const uint8_t P9N2_MCA_EICR_ADDRESS_LEN = 37 ; static const uint8_t P9N2_MCA_EICR_RESERVED = 37 ; static const uint8_t P9N2_MCA_EICR_PERSIST = 38 ; static const uint8_t P9N2_MCA_EICR_PERSIST_LEN = 2 ; static const uint8_t P9N2_MCA_EICR_REGION = 40 ; static const uint8_t P9N2_MCA_EICR_REGION_LEN = 3 ; static const uint8_t P9N2_MCA_EICR_TYPE = 43 ; static const uint8_t P9N2_MCA_EICR_TYPE_LEN = 5 ; static const uint8_t P9N2_MCA_EICR_MISC = 48 ; static const uint8_t P9N2_MCA_EICR_MISC_LEN = 4 ; static const uint8_t P9N2_MCA_ELPR_LOG_FULL = 0 ; static const uint8_t P9N2_MCA_ELPR_LOG_POINTER = 2 ; static const uint8_t P9N2_MCA_ELPR_LOG_POINTER_LEN = 6 ; static const uint8_t P9N2_MCA_WDF_FIR_MAINLINE_MPE_RANK_0_TO_7 = 0 ; static const uint8_t P9N2_MCA_WDF_FIR_MAINLINE_MPE_RANK_0_TO_7_LEN = 8 ; static const uint8_t P9N2_MCA_WDF_FIR_MAINLINE_NCE = 8 ; static const uint8_t P9N2_MCA_WDF_FIR_MAINLINE_TCE = 9 ; static const uint8_t P9N2_MCA_WDF_FIR_MAINLINE_SCE = 10 ; static const uint8_t P9N2_MCA_WDF_FIR_MAINLINE_MCE = 11 ; static const uint8_t P9N2_MCA_WDF_FIR_MAINLINE_SUE = 12 ; static const uint8_t P9N2_MCA_WDF_FIR_MAINLINE_AUE = 13 ; static const uint8_t P9N2_MCA_WDF_FIR_MAINLINE_UE = 14 ; static const uint8_t P9N2_MCA_WDF_FIR_MAINLINE_RCD = 15 ; static const uint8_t P9N2_MCA_WDF_FIR_MAINLINE_IAUE = 16 ; static const uint8_t P9N2_MCA_WDF_FIR_MAINLINE_IUE = 17 ; static const uint8_t P9N2_MCA_WDF_FIR_MAINLINE_IRCD = 18 ; static const uint8_t P9N2_MCA_WDF_FIR_MAINLINE_IMPE = 19 ; static const uint8_t P9N2_MCA_WDF_FIR_MAINTENANCE_MPE_RANK_0_TO_7 = 20 ; static const uint8_t P9N2_MCA_WDF_FIR_MAINTENANCE_MPE_RANK_0_TO_7_LEN = 8 ; static const uint8_t P9N2_MCA_WDF_FIR_MAINTENANCE_NCE = 28 ; static const uint8_t P9N2_MCA_WDF_FIR_MAINTENANCE_TCE = 29 ; static const uint8_t P9N2_MCA_WDF_FIR_MAINTENANCE_SCE = 30 ; static const uint8_t P9N2_MCA_WDF_FIR_MAINTENANCE_MCE = 31 ; static const uint8_t P9N2_MCA_WDF_FIR_MAINTENANCE_SUE = 32 ; static const uint8_t P9N2_MCA_WDF_FIR_MAINTENANCE_AUE = 33 ; static const uint8_t P9N2_MCA_WDF_FIR_MAINTENANCE_UE = 34 ; static const uint8_t P9N2_MCA_WDF_FIR_MAINTENANCE_RCD = 35 ; static const uint8_t P9N2_MCA_WDF_FIR_MAINTENANCE_IAUE = 36 ; static const uint8_t P9N2_MCA_WDF_FIR_MAINTENANCE_IUE = 37 ; static const uint8_t P9N2_MCA_WDF_FIR_MAINTENANCE_IRCD = 38 ; static const uint8_t P9N2_MCA_WDF_FIR_MAINTENANCE_IMPE = 39 ; static const uint8_t P9N2_MCA_WDF_FIR_SCOM_PARITY_CRC_SWIZZLE = 40 ; static const uint8_t P9N2_MCA_WDF_FIR_SCOM_PARITY_CLASS_STATUS = 41 ; static const uint8_t P9N2_MCA_WDF_FIR_SCOM_PARITY_CLASS_RECOVERABLE = 42 ; static const uint8_t P9N2_MCA_WDF_FIR_SCOM_PARITY_CLASS_UNRECOVERABLE = 43 ; static const uint8_t P9N2_MCA_WDF_FIR_ECC_CORRECTOR_INTERNAL_PARITY_ERROR = 44 ; static const uint8_t P9N2_MCA_WDF_FIR_WRITE_RMW_CE = 45 ; static const uint8_t P9N2_MCA_WDF_FIR_WRITE_RMW_UE = 46 ; static const uint8_t P9N2_MCA_WDF_FIR_WRITE_RMW_SUE = 47 ; static const uint8_t P9N2_MCA_WDF_FIR_WDF_OVERRUN_ERROR_0 = 48 ; static const uint8_t P9N2_MCA_WDF_FIR_WDF_OVERRUN_ERROR_1 = 49 ; static const uint8_t P9N2_MCA_WDF_FIR_WDF_SCOM_SEQUENCE_ERROR = 50 ; static const uint8_t P9N2_MCA_WDF_FIR_WDF_STATE_MACHINE_ERROR = 51 ; static const uint8_t P9N2_MCA_WDF_FIR_WDF_MISC_REGISTER_PARITY_ERROR = 52 ; static const uint8_t P9N2_MCA_WDF_FIR_WRT_SCOM_SEQUENCE_ERROR = 53 ; static const uint8_t P9N2_MCA_WDF_FIR_WRT_MISC_REGISTER_PARITY_ERROR = 54 ; static const uint8_t P9N2_MCA_WDF_FIR_ECC_GENERATOR_INTERNAL_PARITY_ERROR = 55 ; static const uint8_t P9N2_MCA_WDF_FIR_READ_BUFFER_OVERFLOW_ERROR = 56 ; static const uint8_t P9N2_MCA_WDF_FIR_WDF_ASYNC_INTERFACE_ERROR = 57 ; static const uint8_t P9N2_MCA_WDF_FIR_RESERVED_58 = 58 ; static const uint8_t P9N2_MCA_WDF_FIR_RESERVED_59 = 59 ; static const uint8_t P9N2_MCA_WDF_FIR_SCOM_PARITY_DEBUG_WAT = 60 ; static const uint8_t P9N2_MCA_WDF_FIR_RESERVED = 61 ; static const uint8_t P9N2_MCA_WDF_FIR_INTERNAL_SCOM_ERROR = 62 ; static const uint8_t P9N2_MCA_WDF_FIR_INTERNAL_SCOM_ERROR_COPY = 63 ; static const uint8_t P9N2_MCA_FIR_MAINLINE_MPE_RANK_0_TO_7 = 0 ; static const uint8_t P9N2_MCA_FIR_MAINLINE_MPE_RANK_0_TO_7_LEN = 8 ; static const uint8_t P9N2_MCA_FIR_MAINLINE_NCE = 8 ; static const uint8_t P9N2_MCA_FIR_MAINLINE_TCE = 9 ; static const uint8_t P9N2_MCA_FIR_MAINLINE_SCE = 10 ; static const uint8_t P9N2_MCA_FIR_MAINLINE_MCE = 11 ; static const uint8_t P9N2_MCA_FIR_MAINLINE_SUE = 12 ; static const uint8_t P9N2_MCA_FIR_MAINLINE_AUE = 13 ; static const uint8_t P9N2_MCA_FIR_MAINLINE_UE = 14 ; static const uint8_t P9N2_MCA_FIR_MAINLINE_RCD = 15 ; static const uint8_t P9N2_MCA_FIR_MAINLINE_IAUE = 16 ; static const uint8_t P9N2_MCA_FIR_MAINLINE_IUE = 17 ; static const uint8_t P9N2_MCA_FIR_MAINLINE_IRCD = 18 ; static const uint8_t P9N2_MCA_FIR_MAINLINE_IMPE = 19 ; static const uint8_t P9N2_MCA_FIR_MAINTENANCE_MPE_RANK_0_TO_7 = 20 ; static const uint8_t P9N2_MCA_FIR_MAINTENANCE_MPE_RANK_0_TO_7_LEN = 8 ; static const uint8_t P9N2_MCA_FIR_MAINTENANCE_NCE = 28 ; static const uint8_t P9N2_MCA_FIR_MAINTENANCE_TCE = 29 ; static const uint8_t P9N2_MCA_FIR_MAINTENANCE_SCE = 30 ; static const uint8_t P9N2_MCA_FIR_MAINTENANCE_MCE = 31 ; static const uint8_t P9N2_MCA_FIR_MAINTENANCE_SUE = 32 ; static const uint8_t P9N2_MCA_FIR_MAINTENANCE_AUE = 33 ; static const uint8_t P9N2_MCA_FIR_MAINTENANCE_UE = 34 ; static const uint8_t P9N2_MCA_FIR_MAINTENANCE_RCD = 35 ; static const uint8_t P9N2_MCA_FIR_MAINTENANCE_IAUE = 36 ; static const uint8_t P9N2_MCA_FIR_MAINTENANCE_IUE = 37 ; static const uint8_t P9N2_MCA_FIR_MAINTENANCE_IRCD = 38 ; static const uint8_t P9N2_MCA_FIR_MAINTENANCE_IMPE = 39 ; static const uint8_t P9N2_MCA_FIR_SCOM_PARITY_CRC_SWIZZLE = 40 ; static const uint8_t P9N2_MCA_FIR_SCOM_PARITY_CLASS_STATUS = 41 ; static const uint8_t P9N2_MCA_FIR_SCOM_PARITY_CLASS_RECOVERABLE = 42 ; static const uint8_t P9N2_MCA_FIR_SCOM_PARITY_CLASS_UNRECOVERABLE = 43 ; static const uint8_t P9N2_MCA_FIR_ECC_CORRECTOR_INTERNAL_PARITY_ERROR = 44 ; static const uint8_t P9N2_MCA_FIR_WRITE_RMW_CE = 45 ; static const uint8_t P9N2_MCA_FIR_WRITE_RMW_UE = 46 ; static const uint8_t P9N2_MCA_FIR_WRITE_RMW_SUE = 47 ; static const uint8_t P9N2_MCA_FIR_WDF_OVERRUN_ERROR_0 = 48 ; static const uint8_t P9N2_MCA_FIR_WDF_OVERRUN_ERROR_1 = 49 ; static const uint8_t P9N2_MCA_FIR_WDF_SCOM_SEQUENCE_ERROR = 50 ; static const uint8_t P9N2_MCA_FIR_WDF_STATE_MACHINE_ERROR = 51 ; static const uint8_t P9N2_MCA_FIR_WDF_MISC_REGISTER_PARITY_ERROR = 52 ; static const uint8_t P9N2_MCA_FIR_WRT_SCOM_SEQUENCE_ERROR = 53 ; static const uint8_t P9N2_MCA_FIR_WRT_MISC_REGISTER_PARITY_ERROR = 54 ; static const uint8_t P9N2_MCA_FIR_ECC_GENERATOR_INTERNAL_PARITY_ERROR = 55 ; static const uint8_t P9N2_MCA_FIR_READ_BUFFER_OVERFLOW_ERROR = 56 ; static const uint8_t P9N2_MCA_FIR_WDF_ASYNC_INTERFACE_ERROR = 57 ; static const uint8_t P9N2_MCA_FIR_RESERVED_58 = 58 ; static const uint8_t P9N2_MCA_FIR_RESERVED_59 = 59 ; static const uint8_t P9N2_MCA_FIR_SCOM_PARITY_DEBUG_WAT = 60 ; static const uint8_t P9N2_MCA_FIR_RESERVED = 61 ; static const uint8_t P9N2_MCA_FIR_INTERNAL_SCOM_ERROR = 62 ; static const uint8_t P9N2_MCA_FIR_INTERNAL_SCOM_ERROR_COPY = 63 ; static const uint8_t P9N2_MCA_FWMS0_MARK = 0 ; static const uint8_t P9N2_MCA_FWMS0_MARK_LEN = 8 ; static const uint8_t P9N2_MCA_FWMS0_TYPE = 8 ; static const uint8_t P9N2_MCA_FWMS0_REGION = 9 ; static const uint8_t P9N2_MCA_FWMS0_REGION_LEN = 3 ; static const uint8_t P9N2_MCA_FWMS0_ADDRESS = 12 ; static const uint8_t P9N2_MCA_FWMS0_ADDRESS_LEN = 11 ; static const uint8_t P9N2_MCA_FWMS0_EXIT_1 = 23 ; static const uint8_t P9N2_MCA_WREITE_FWMS1_MARK = 0 ; static const uint8_t P9N2_MCA_WREITE_FWMS1_MARK_LEN = 8 ; static const uint8_t P9N2_MCA_WREITE_FWMS1_TYPE = 8 ; static const uint8_t P9N2_MCA_WREITE_FWMS1_REGION = 9 ; static const uint8_t P9N2_MCA_WREITE_FWMS1_REGION_LEN = 3 ; static const uint8_t P9N2_MCA_WREITE_FWMS1_ADDRESS = 12 ; static const uint8_t P9N2_MCA_WREITE_FWMS1_ADDRESS_LEN = 11 ; static const uint8_t P9N2_MCA_WREITE_FWMS1_EXIT_1 = 23 ; static const uint8_t P9N2_MCA_FWMS2_MARK = 0 ; static const uint8_t P9N2_MCA_FWMS2_MARK_LEN = 8 ; static const uint8_t P9N2_MCA_FWMS2_TYPE = 8 ; static const uint8_t P9N2_MCA_FWMS2_REGION = 9 ; static const uint8_t P9N2_MCA_FWMS2_REGION_LEN = 3 ; static const uint8_t P9N2_MCA_FWMS2_ADDRESS = 12 ; static const uint8_t P9N2_MCA_FWMS2_ADDRESS_LEN = 11 ; static const uint8_t P9N2_MCA_FWMS2_EXIT_1 = 23 ; static const uint8_t P9N2_MCA_FWMS3_MARK = 0 ; static const uint8_t P9N2_MCA_FWMS3_MARK_LEN = 8 ; static const uint8_t P9N2_MCA_FWMS3_TYPE = 8 ; static const uint8_t P9N2_MCA_FWMS3_REGION = 9 ; static const uint8_t P9N2_MCA_FWMS3_REGION_LEN = 3 ; static const uint8_t P9N2_MCA_FWMS3_ADDRESS = 12 ; static const uint8_t P9N2_MCA_FWMS3_ADDRESS_LEN = 11 ; static const uint8_t P9N2_MCA_FWMS3_EXIT_1 = 23 ; static const uint8_t P9N2_MCA_FWMS4_MARK = 0 ; static const uint8_t P9N2_MCA_FWMS4_MARK_LEN = 8 ; static const uint8_t P9N2_MCA_FWMS4_TYPE = 8 ; static const uint8_t P9N2_MCA_FWMS4_REGION = 9 ; static const uint8_t P9N2_MCA_FWMS4_REGION_LEN = 3 ; static const uint8_t P9N2_MCA_FWMS4_ADDRESS = 12 ; static const uint8_t P9N2_MCA_FWMS4_ADDRESS_LEN = 11 ; static const uint8_t P9N2_MCA_FWMS4_EXIT_1 = 23 ; static const uint8_t P9N2_MCA_FWMS5_MARK = 0 ; static const uint8_t P9N2_MCA_FWMS5_MARK_LEN = 8 ; static const uint8_t P9N2_MCA_FWMS5_TYPE = 8 ; static const uint8_t P9N2_MCA_FWMS5_REGION = 9 ; static const uint8_t P9N2_MCA_FWMS5_REGION_LEN = 3 ; static const uint8_t P9N2_MCA_FWMS5_ADDRESS = 12 ; static const uint8_t P9N2_MCA_FWMS5_ADDRESS_LEN = 11 ; static const uint8_t P9N2_MCA_FWMS5_EXIT_1 = 23 ; static const uint8_t P9N2_MCA_FWMS6_MARK = 0 ; static const uint8_t P9N2_MCA_FWMS6_MARK_LEN = 8 ; static const uint8_t P9N2_MCA_FWMS6_TYPE = 8 ; static const uint8_t P9N2_MCA_FWMS6_REGION = 9 ; static const uint8_t P9N2_MCA_FWMS6_REGION_LEN = 3 ; static const uint8_t P9N2_MCA_FWMS6_ADDRESS = 12 ; static const uint8_t P9N2_MCA_FWMS6_ADDRESS_LEN = 11 ; static const uint8_t P9N2_MCA_FWMS6_EXIT_1 = 23 ; static const uint8_t P9N2_MCA_FWMS7_MARK = 0 ; static const uint8_t P9N2_MCA_FWMS7_MARK_LEN = 8 ; static const uint8_t P9N2_MCA_FWMS7_TYPE = 8 ; static const uint8_t P9N2_MCA_FWMS7_REGION = 9 ; static const uint8_t P9N2_MCA_FWMS7_REGION_LEN = 3 ; static const uint8_t P9N2_MCA_FWMS7_ADDRESS = 12 ; static const uint8_t P9N2_MCA_FWMS7_ADDRESS_LEN = 11 ; static const uint8_t P9N2_MCA_FWMS7_EXIT_1 = 23 ; static const uint8_t P9N2_MCA_HWMS0_CHIPMARK = 0 ; static const uint8_t P9N2_MCA_HWMS0_CHIPMARK_LEN = 8 ; static const uint8_t P9N2_MCA_HWMS0_CONFIRMED = 8 ; static const uint8_t P9N2_MCA_HWMS0_EXIT_1 = 9 ; static const uint8_t P9N2_MCA_WDF_HWMS1_CHIPMARK = 0 ; static const uint8_t P9N2_MCA_WDF_HWMS1_CHIPMARK_LEN = 8 ; static const uint8_t P9N2_MCA_WDF_HWMS1_CONFIRMED = 8 ; static const uint8_t P9N2_MCA_WDF_HWMS1_EXIT_1 = 9 ; static const uint8_t P9N2_MCA_HWMS2_CHIPMARK = 0 ; static const uint8_t P9N2_MCA_HWMS2_CHIPMARK_LEN = 8 ; static const uint8_t P9N2_MCA_HWMS2_CONFIRMED = 8 ; static const uint8_t P9N2_MCA_HWMS2_EXIT_1 = 9 ; static const uint8_t P9N2_MCA_HWMS3_CHIPMARK = 0 ; static const uint8_t P9N2_MCA_HWMS3_CHIPMARK_LEN = 8 ; static const uint8_t P9N2_MCA_HWMS3_CONFIRMED = 8 ; static const uint8_t P9N2_MCA_HWMS3_EXIT_1 = 9 ; static const uint8_t P9N2_MCA_HWMS4_CHIPMARK = 0 ; static const uint8_t P9N2_MCA_HWMS4_CHIPMARK_LEN = 8 ; static const uint8_t P9N2_MCA_HWMS4_CONFIRMED = 8 ; static const uint8_t P9N2_MCA_HWMS4_EXIT_1 = 9 ; static const uint8_t P9N2_MCA_HWMS5_CHIPMARK = 0 ; static const uint8_t P9N2_MCA_HWMS5_CHIPMARK_LEN = 8 ; static const uint8_t P9N2_MCA_HWMS5_CONFIRMED = 8 ; static const uint8_t P9N2_MCA_HWMS5_EXIT_1 = 9 ; static const uint8_t P9N2_MCA_HWMS6_CHIPMARK = 0 ; static const uint8_t P9N2_MCA_HWMS6_CHIPMARK_LEN = 8 ; static const uint8_t P9N2_MCA_HWMS6_CONFIRMED = 8 ; static const uint8_t P9N2_MCA_HWMS6_EXIT_1 = 9 ; static const uint8_t P9N2_MCA_HWMS7_CHIPMARK = 0 ; static const uint8_t P9N2_MCA_HWMS7_CHIPMARK_LEN = 8 ; static const uint8_t P9N2_MCA_HWMS7_CONFIRMED = 8 ; static const uint8_t P9N2_MCA_HWMS7_EXIT_1 = 9 ; static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_ACTION0_REG_DDR = 54 ; static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_ACTION0_REG_DDR_LEN = 8 ; static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_ACTION1_REG_DDR = 54 ; static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_ACTION1_REG_DDR_LEN = 8 ; static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_MASK_REG_DDR_ERROR_0 = 54 ; static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_MASK_REG_DDR_ERROR_1 = 55 ; static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_MASK_REG_DDR_ERROR_2 = 56 ; static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_MASK_REG_DDR_ERROR_3 = 57 ; static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_MASK_REG_DDR_ERROR_4 = 58 ; static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_MASK_REG_DDR_ERROR_5 = 59 ; static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_MASK_REG_DDR_ERROR_6 = 60 ; static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_MASK_REG_DDR_ERROR_7 = 61 ; static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_REG_DDR_ERROR_0 = 54 ; static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_REG_DDR_ERROR_1 = 55 ; static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_REG_DDR_ERROR_2 = 56 ; static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_REG_DDR_ERROR_3 = 57 ; static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_REG_DDR_ERROR_4 = 58 ; static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_REG_DDR_ERROR_5 = 59 ; static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_REG_DDR_ERROR_6 = 60 ; static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_REG_DDR_ERROR_7 = 61 ; static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_WOF_REG_DDR = 54 ; static const uint8_t P9N2_MCA_IOM_PHY0_DDRPHY_FIR_WOF_REG_DDR_LEN = 8 ; static const uint8_t P9N2_MCA_MASK_FIR = 0 ; static const uint8_t P9N2_MCA_MASK_FIR_LEN = 64 ; static const uint8_t P9N2_MCA_MBACALFIRQ_MBA_RECOVERABLE_ERROR = 0 ; static const uint8_t P9N2_MCA_MBACALFIRQ_MBA_NONRECOVERABLE_ERROR = 1 ; static const uint8_t P9N2_MCA_MBACALFIRQ_REFRESH_OVERRUN = 2 ; static const uint8_t P9N2_MCA_MBACALFIRQ_WAT_ERROR = 3 ; static const uint8_t P9N2_MCA_MBACALFIRQ_RCD_PARITY_ERROR = 4 ; static const uint8_t P9N2_MCA_MBACALFIRQ_DDR_CAL_TIMEOUT_ERR = 5 ; static const uint8_t P9N2_MCA_MBACALFIRQ_EMERGENCY_THROTTLE = 6 ; static const uint8_t P9N2_MCA_MBACALFIRQ_DDR_CAL_RESET_TIMEOUT = 7 ; static const uint8_t P9N2_MCA_MBACALFIRQ_DDR_MBA_EVENT_N = 8 ; static const uint8_t P9N2_MCA_MBACALFIRQ_WRQ_RRQ_HANG_ERR = 9 ; static const uint8_t P9N2_MCA_MBACALFIRQ_SM_1HOT_ERR = 10 ; static const uint8_t P9N2_MCA_MBACALFIRQ_ASYNC_IF_ERROR = 11 ; static const uint8_t P9N2_MCA_MBACALFIRQ_CMD_PARITY_ERROR = 12 ; static const uint8_t P9N2_MCA_MBACALFIRQ_PORT_FAIL = 13 ; static const uint8_t P9N2_MCA_MBACALFIRQ_RCD_CAL_PARITY_ERROR = 14 ; static const uint8_t P9N2_MCA_MBACALFIRQ_DEBUG_PARITY_ERROR = 15 ; static const uint8_t P9N2_MCA_MBACALFIRQ_INTERNAL_SCOM_ERROR = 16 ; static const uint8_t P9N2_MCA_MBACALFIRQ_INTERNAL_SCOM_ERROR_COPY = 17 ; static const uint8_t P9N2_MCA_MBACALFIR_ACTION0_FIR = 0 ; static const uint8_t P9N2_MCA_MBACALFIR_ACTION0_FIR_LEN = 18 ; static const uint8_t P9N2_MCA_MBACALFIR_ACTION1_FIR = 0 ; static const uint8_t P9N2_MCA_MBACALFIR_ACTION1_FIR_LEN = 18 ; static const uint8_t P9N2_MCA_MBACALFIR_MASK_MBA_RECOVERABLE_ERROR = 0 ; static const uint8_t P9N2_MCA_MBACALFIR_MASK_MBA_NONRECOVERABLE_ERROR = 1 ; static const uint8_t P9N2_MCA_MBACALFIR_MASK_REFRESH_OVERRUN = 2 ; static const uint8_t P9N2_MCA_MBACALFIR_MASK_WAT_ERROR = 3 ; static const uint8_t P9N2_MCA_MBACALFIR_MASK_RCD_PARITY_ERROR = 4 ; static const uint8_t P9N2_MCA_MBACALFIR_MASK_DDR_CAL_TIMEOUT_ERR = 5 ; static const uint8_t P9N2_MCA_MBACALFIR_MASK_EMERGENCY_THROTTLE = 6 ; static const uint8_t P9N2_MCA_MBACALFIR_MASK_DDR_CAL_RESET_TIMEOUT = 7 ; static const uint8_t P9N2_MCA_MBACALFIR_MASK_DDR_MBA_EVENT_N = 8 ; static const uint8_t P9N2_MCA_MBACALFIR_MASK_WRQ_RRQ_HANG_ERR = 9 ; static const uint8_t P9N2_MCA_MBACALFIR_MASK_SM_1HOT_ERR = 10 ; static const uint8_t P9N2_MCA_MBACALFIR_MASK_ASYNC_IF_ERROR = 11 ; static const uint8_t P9N2_MCA_MBACALFIR_MASK_CMD_PARITY_ERROR = 12 ; static const uint8_t P9N2_MCA_MBACALFIR_MASK_MBACALFIRQ_PORT_FAIL = 13 ; static const uint8_t P9N2_MCA_MBACALFIR_MASK_MBACALFIRQ_RCD_CAL_PARITY_ERROR = 14 ; static const uint8_t P9N2_MCA_MBACALFIR_MASK_MBACALFIRQ_DEBUG_PARITY_ERROR = 15 ; static const uint8_t P9N2_MCA_MBACALFIR_MASK_INTERNAL_SCOM_ERROR = 16 ; static const uint8_t P9N2_MCA_MBACALFIR_MASK_INTERNAL_SCOM_ERROR_COPY = 17 ; static const uint8_t P9N2_MCA_MBAREF0Q_CFG_REFRESH_ENABLE = 0 ; static const uint8_t P9N2_MCA_MBAREF0Q_CFG_REFRESH_INTERVAL_TIMEBASE_SELECT = 1 ; static const uint8_t P9N2_MCA_MBAREF0Q_CFG_REFRESH_INTERVAL_TIMEBASE_SELECT_LEN = 2 ; static const uint8_t P9N2_MCA_MBAREF0Q_CFG_PER_BANK_REFRESH = 3 ; static const uint8_t P9N2_MCA_MBAREF0Q_CFG_REFRESH_DEBUG_SELECT = 4 ; static const uint8_t P9N2_MCA_MBAREF0Q_CFG_REFRESH_PRIORITY_THRESHOLD = 5 ; static const uint8_t P9N2_MCA_MBAREF0Q_CFG_REFRESH_PRIORITY_THRESHOLD_LEN = 3 ; static const uint8_t P9N2_MCA_MBAREF0Q_CFG_REFRESH_INTERVAL = 8 ; static const uint8_t P9N2_MCA_MBAREF0Q_CFG_REFRESH_INTERVAL_LEN = 11 ; static const uint8_t P9N2_MCA_MBAREF0Q_CFG_REFRESH_RESET_INTERVAL = 19 ; static const uint8_t P9N2_MCA_MBAREF0Q_CFG_REFRESH_RESET_INTERVAL_LEN = 11 ; static const uint8_t P9N2_MCA_MBAREF0Q_CFG_TRFC = 30 ; static const uint8_t P9N2_MCA_MBAREF0Q_CFG_TRFC_LEN = 10 ; static const uint8_t P9N2_MCA_MBAREF0Q_CFG_REFR_TSV_STACK = 40 ; static const uint8_t P9N2_MCA_MBAREF0Q_CFG_REFR_TSV_STACK_LEN = 10 ; static const uint8_t P9N2_MCA_MBAREF0Q_CFG_REFR_CHECK_INTERVAL = 50 ; static const uint8_t P9N2_MCA_MBAREF0Q_CFG_REFR_CHECK_INTERVAL_LEN = 11 ; static const uint8_t P9N2_MCA_MBAREF0Q_CFG_TRFC_STACK_GATE_ALL_REF = 61 ; static const uint8_t P9N2_MCA_MBAREF0Q_RESERVED_62_63 = 62 ; static const uint8_t P9N2_MCA_MBAREF0Q_RESERVED_62_63_LEN = 2 ; static const uint8_t P9N2_MCA_MBAREFAQ_CFG_STATIC_IDLE_DLY = 0 ; static const uint8_t P9N2_MCA_MBAREFAQ_CFG_STATIC_IDLE_DLY_LEN = 4 ; static const uint8_t P9N2_MCA_MBAREFAQ_CFG_LP_SUB_CNT = 4 ; static const uint8_t P9N2_MCA_MBAREFAQ_CFG_LP_SUB_CNT_LEN = 2 ; static const uint8_t P9N2_MCA_MBAREFAQ_CFG_REFRESH_HP_RANK_BLOCK_ENABLE = 6 ; static const uint8_t P9N2_MCA_MBAREFAQ_CFG_HP_WR_GATE_LP_REF_DIS = 7 ; static const uint8_t P9N2_MCA_MBAREFAQ_RESERVED_8_9 = 8 ; static const uint8_t P9N2_MCA_MBAREFAQ_RESERVED_8_9_LEN = 2 ; static const uint8_t P9N2_MCA_MBAREFAQ_CFG_REF_BLOCK_STOP_DLY = 10 ; static const uint8_t P9N2_MCA_MBAREFAQ_CFG_REF_BLOCK_STOP_DLY_LEN = 6 ; static const uint8_t P9N2_MCA_MBARPC0Q_RESERVED_0_1 = 0 ; static const uint8_t P9N2_MCA_MBARPC0Q_RESERVED_0_1_LEN = 2 ; static const uint8_t P9N2_MCA_MBARPC0Q_CFG_MIN_MAX_DOMAINS_ENABLE = 2 ; static const uint8_t P9N2_MCA_MBARPC0Q_CFG_MIN_MAX_DOMAINS = 3 ; static const uint8_t P9N2_MCA_MBARPC0Q_CFG_MIN_MAX_DOMAINS_LEN = 3 ; static const uint8_t P9N2_MCA_MBARPC0Q_CFG_PUP_AVAIL = 6 ; static const uint8_t P9N2_MCA_MBARPC0Q_CFG_PUP_AVAIL_LEN = 5 ; static const uint8_t P9N2_MCA_MBARPC0Q_CFG_PDN_PUP = 11 ; static const uint8_t P9N2_MCA_MBARPC0Q_CFG_PDN_PUP_LEN = 5 ; static const uint8_t P9N2_MCA_MBARPC0Q_CFG_PUP_PDN = 16 ; static const uint8_t P9N2_MCA_MBARPC0Q_CFG_PUP_PDN_LEN = 5 ; static const uint8_t P9N2_MCA_MBARPC0Q_CFG_QUAD_RANK_ENC = 21 ; static const uint8_t P9N2_MCA_MBARPC0Q_CFG_MIN_DOMAIN_REDUCTION_ENABLE = 22 ; static const uint8_t P9N2_MCA_MBARPC0Q_CFG_MIN_DOMAIN_REDUCTION_TIME = 23 ; static const uint8_t P9N2_MCA_MBARPC0Q_CFG_MIN_DOMAIN_REDUCTION_TIME_LEN = 10 ; static const uint8_t P9N2_MCA_MBARPC0Q_CFG_PUP_AFTER_ACTIVATE_WAIT_ENABLE = 33 ; static const uint8_t P9N2_MCA_MBARPC0Q_CFG_PUP_AFTER_ACTIVATE_WAIT_TIME = 34 ; static const uint8_t P9N2_MCA_MBARPC0Q_CFG_PUP_AFTER_ACTIVATE_WAIT_TIME_LEN = 8 ; static const uint8_t P9N2_MCA_MBARPC0Q_CFG_FORCE_SPARE_PUP = 42 ; static const uint8_t P9N2_MCA_MBARPC0Q_CFG_MIN_DOMAIN_REDUCTION_CNT_REFR_INT = 43 ; static const uint8_t P9N2_MCA_MBARPC0Q_CFG_EMER_MIN_MAX_DOMAIN = 44 ; static const uint8_t P9N2_MCA_MBARPC0Q_CFG_EMER_MIN_MAX_DOMAIN_LEN = 3 ; static const uint8_t P9N2_MCA_MBARPC0Q_CFG_PUP_ALL_WRITES_PENDING = 47 ; static const uint8_t P9N2_MCA_MBARPC0Q_CFG_ALWAYS_WAIT_ACT_TIME = 48 ; static const uint8_t P9N2_MCA_MBARPC0Q_RESERVED_49_63 = 49 ; static const uint8_t P9N2_MCA_MBARPC0Q_RESERVED_49_63_LEN = 15 ; static const uint8_t P9N2_MCA_MBASTR0Q_CFG_STR_ENABLE = 0 ; static const uint8_t P9N2_MCA_MBASTR0Q_CFG_DIS_CLK_IN_STR = 1 ; static const uint8_t P9N2_MCA_MBASTR0Q_CFG_ENTER_STR_TIME = 2 ; static const uint8_t P9N2_MCA_MBASTR0Q_CFG_ENTER_STR_TIME_LEN = 10 ; static const uint8_t P9N2_MCA_MBASTR0Q_CFG_TCKESR = 12 ; static const uint8_t P9N2_MCA_MBASTR0Q_CFG_TCKESR_LEN = 5 ; static const uint8_t P9N2_MCA_MBASTR0Q_CFG_TCKSRE = 17 ; static const uint8_t P9N2_MCA_MBASTR0Q_CFG_TCKSRE_LEN = 5 ; static const uint8_t P9N2_MCA_MBASTR0Q_CFG_TCKSRX = 22 ; static const uint8_t P9N2_MCA_MBASTR0Q_CFG_TCKSRX_LEN = 5 ; static const uint8_t P9N2_MCA_MBASTR0Q_CFG_TXSDLL = 27 ; static const uint8_t P9N2_MCA_MBASTR0Q_CFG_TXSDLL_LEN = 11 ; static const uint8_t P9N2_MCA_MBASTR0Q_CFG_TRFC_COUNTER_DIS = 38 ; static const uint8_t P9N2_MCA_MBASTR0Q_CFG_TRFC_COUNTER_DIS_LEN = 8 ; static const uint8_t P9N2_MCA_MBASTR0Q_CFG_SAFE_REFRESH_INTERVAL = 46 ; static const uint8_t P9N2_MCA_MBASTR0Q_CFG_SAFE_REFRESH_INTERVAL_LEN = 11 ; static const uint8_t P9N2_MCA_MBASTR0Q_CFG_OCC_DEADMAN_TIMER_SEL = 57 ; static const uint8_t P9N2_MCA_MBASTR0Q_CFG_OCC_DEADMAN_TIMER_SEL_LEN = 4 ; static const uint8_t P9N2_MCA_MBASTR0Q_CFG_OCC_DEADMAN_TB_SEL = 61 ; static const uint8_t P9N2_MCA_MBASTR0Q_RESERVED_62_63 = 62 ; static const uint8_t P9N2_MCA_MBASTR0Q_RESERVED_62_63_LEN = 2 ; static const uint8_t P9N2_MCBIST_MBAUER0Q_PORT_0_MAINLINE_AUE_ADDR_TRAP = 0 ; static const uint8_t P9N2_MCBIST_MBAUER0Q_PORT_0_MAINLINE_AUE_ADDR_TRAP_LEN = 38 ; static const uint8_t P9N2_MCBIST_MBAUER0Q_RESERVED_38_39 = 38 ; static const uint8_t P9N2_MCBIST_MBAUER0Q_RESERVED_38_39_LEN = 2 ; static const uint8_t P9N2_MCBIST_MBAUER1Q_PORT_1_MAINLINE_AUE_ADDR_TRAP = 0 ; static const uint8_t P9N2_MCBIST_MBAUER1Q_PORT_1_MAINLINE_AUE_ADDR_TRAP_LEN = 38 ; static const uint8_t P9N2_MCBIST_MBAUER1Q_RESERVED_38_39 = 38 ; static const uint8_t P9N2_MCBIST_MBAUER1Q_RESERVED_38_39_LEN = 2 ; static const uint8_t P9N2_MCBIST_MBAUER2Q_PORT_2_MAINLINE_AUE_ADDR_TRAP = 0 ; static const uint8_t P9N2_MCBIST_MBAUER2Q_PORT_2_MAINLINE_AUE_ADDR_TRAP_LEN = 38 ; static const uint8_t P9N2_MCBIST_MBAUER2Q_RESERVED_38_39 = 38 ; static const uint8_t P9N2_MCBIST_MBAUER2Q_RESERVED_38_39_LEN = 2 ; static const uint8_t P9N2_MCBIST_MBAUER3Q_PORT_3_MAINLINE_AUE_ADDR_TRAP = 0 ; static const uint8_t P9N2_MCBIST_MBAUER3Q_PORT_3_MAINLINE_AUE_ADDR_TRAP_LEN = 38 ; static const uint8_t P9N2_MCBIST_MBAUER3Q_RESERVED_38_39 = 38 ; static const uint8_t P9N2_MCBIST_MBAUER3Q_RESERVED_38_39_LEN = 2 ; static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_INTERVAL_TMR0_ENABLE = 0 ; static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_TIME_BASE_TMR0 = 1 ; static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_TIME_BASE_TMR0_LEN = 2 ; static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_INTERVAL_COUNTER_TMR0 = 3 ; static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_INTERVAL_COUNTER_TMR0_LEN = 9 ; static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL1_ENABLE = 12 ; static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL1_TYPE = 13 ; static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL1_TYPE_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL1_DDR_DONE = 17 ; static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL2_ENABLE = 18 ; static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL2_TYPE = 19 ; static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL2_TYPE_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL2_DDR_DONE = 23 ; static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL3_ENABLE = 24 ; static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL3_TYPE = 25 ; static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL3_TYPE_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL3_DDR_DONE = 29 ; static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_TMR0_Z_SYNC = 30 ; static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_TMR0_Z_SYNC_LEN = 9 ; static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_TMR0_DDR_RESET_TMR = 39 ; static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_TMR0_DDR_RESET_TMR_LEN = 8 ; static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_TMR0_DDR_RESET_TMR_TB = 47 ; static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_TMR0_DDR_RESET_TMR_TB_LEN = 2 ; static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_TMR0_DDR_RESET_ENABLE = 49 ; static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_TMR0_SINGLE_RANK = 50 ; static const uint8_t P9N2_MCA_MBA_CAL0Q_RESERVED_51 = 51 ; static const uint8_t P9N2_MCA_MBA_CAL0Q_INJECT_1HOT_SM_ERROR = 52 ; static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_SINGLE_PORT_MODE = 53 ; static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_CAL_SINGLE_PORT_MODE_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_CAL0Q_DBG_BUS_BIT = 56 ; static const uint8_t P9N2_MCA_MBA_CAL0Q_RESET_RECOVER = 57 ; static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_RANK_SM_STALL_DISABLE = 58 ; static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_ENABLE_SPEC_ATTN = 59 ; static const uint8_t P9N2_MCA_MBA_CAL0Q_CFG_ENABLE_HOST_ATTN = 60 ; static const uint8_t P9N2_MCA_MBA_CAL0Q_RESERVED_61_63 = 61 ; static const uint8_t P9N2_MCA_MBA_CAL0Q_RESERVED_61_63_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_INTERVAL_TMR1_ENABLE = 0 ; static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_TIME_BASE_TMR1 = 1 ; static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_TIME_BASE_TMR1_LEN = 2 ; static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_INTERVAL_COUNTER_TMR1 = 3 ; static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_INTERVAL_COUNTER_TMR1_LEN = 9 ; static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL1_ENABLE = 12 ; static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL1_TYPE = 13 ; static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL1_TYPE_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL1_DDR_DONE = 17 ; static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL2_ENABLE = 18 ; static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL2_TYPE = 19 ; static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL2_TYPE_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL2_DDR_DONE = 23 ; static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL3_ENABLE = 24 ; static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL3_TYPE = 25 ; static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL3_TYPE_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL3_DDR_DONE = 29 ; static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_TMR1_Z_SYNC = 30 ; static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_TMR1_Z_SYNC_LEN = 9 ; static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_TMR1_SINGLE_RANK = 39 ; static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_RANK_ENABLE = 40 ; static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_RANK_ENABLE_LEN = 8 ; static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_TMR0_WAT_SYNC_ENABLE = 48 ; static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_TMR1_WAT_SYNC_ENABLE = 49 ; static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_TMR2_WAT_SYNC_ENABLE = 50 ; static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_DBG_TMR_SEL0 = 51 ; static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_DBG_TMR_SEL0_LEN = 2 ; static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_DBG_TMR_SEL1 = 53 ; static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_DBG_TMR_INT_SEL = 54 ; static const uint8_t P9N2_MCA_MBA_CAL1Q_CFG_CAL_DBG_TMR_INT_SEL_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_CAL1Q_RESERVED_48_63 = 57 ; static const uint8_t P9N2_MCA_MBA_CAL1Q_RESERVED_48_63_LEN = 7 ; static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_CAL_INTERVAL_TMR2_ENABLE = 0 ; static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_TIME_BASE_TMR2 = 1 ; static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_TIME_BASE_TMR2_LEN = 2 ; static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_INTERVAL_COUNTER_TMR2 = 3 ; static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_INTERVAL_COUNTER_TMR2_LEN = 9 ; static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL1_ENABLE = 12 ; static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL1_TYPE = 13 ; static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL1_TYPE_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL1_DDR_DONE = 17 ; static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL2_ENABLE = 18 ; static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL2_TYPE = 19 ; static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL2_TYPE_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL2_DDR_DONE = 23 ; static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL3_ENABLE = 24 ; static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL3_TYPE = 25 ; static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL3_TYPE_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL3_DDR_DONE = 29 ; static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_CAL_TMR2_Z_SYNC = 30 ; static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_CAL_TMR2_Z_SYNC_LEN = 9 ; static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_CAL_TMR2_SINGLE_RANK = 39 ; static const uint8_t P9N2_MCA_MBA_CAL2Q_CFG_CAL_TMR2_WAT_EVENT_ENABLE = 40 ; static const uint8_t P9N2_MCA_MBA_CAL2Q_RESERVED_41_63 = 41 ; static const uint8_t P9N2_MCA_MBA_CAL2Q_RESERVED_41_63_LEN = 23 ; static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_INTERNAL_ZQ_TB = 0 ; static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_INTERNAL_ZQ_TB_LEN = 2 ; static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_INTERNAL_ZQ_LENGTH = 2 ; static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_INTERNAL_ZQ_LENGTH_LEN = 8 ; static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_EXTERNAL_ZQ_TB = 10 ; static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_EXTERNAL_ZQ_TB_LEN = 2 ; static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_EXTERNAL_ZQ_LENGTH = 12 ; static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_EXTERNAL_ZQ_LENGTH_LEN = 8 ; static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_RDCLK_SYSCLK_TB = 20 ; static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_RDCLK_SYSCLK_TB_LEN = 2 ; static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_RDCLK_SYSCLK_LENGTH = 22 ; static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_RDCLK_SYSCLK_LENGTH_LEN = 8 ; static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_DQS_ALIGNMENT_TB = 30 ; static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_DQS_ALIGNMENT_TB_LEN = 2 ; static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_DQS_ALIGNMENT_LENGTH = 32 ; static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_DQS_ALIGNMENT_LENGTH_LEN = 8 ; static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_MPR_READEYE_TB = 40 ; static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_MPR_READEYE_TB_LEN = 2 ; static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_MPR_READEYE_LENGTH = 42 ; static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_MPR_READEYE_LENGTH_LEN = 8 ; static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_ALL_PERIODIC_TB = 50 ; static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_ALL_PERIODIC_TB_LEN = 2 ; static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_ALL_PERIODIC_LENGTH = 52 ; static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_ALL_PERIODIC_LENGTH_LEN = 8 ; static const uint8_t P9N2_MCA_MBA_CAL3Q_CFG_FREEZE_ON_PARITY_ERROR_DIS = 60 ; static const uint8_t P9N2_MCA_MBA_CAL3Q_RESERVED_61_63 = 61 ; static const uint8_t P9N2_MCA_MBA_CAL3Q_RESERVED_61_63_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_DBG_SRQ_ENABLE = 0 ; static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL0 = 1 ; static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL0_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL1 = 4 ; static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL1_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL2 = 7 ; static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL2_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL3 = 10 ; static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL3_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL4 = 13 ; static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL4_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL5 = 16 ; static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL5_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL6 = 19 ; static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL6_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL7 = 22 ; static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL7_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_DBG0Q_RESERVED_25_33 = 25 ; static const uint8_t P9N2_MCA_MBA_DBG0Q_RESERVED_25_33_LEN = 9 ; static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL_OTHER_SRQ = 34 ; static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL_OTHER_SRQ_LEN = 8 ; static const uint8_t P9N2_MCA_MBA_DBG0Q_RESERVED_42_47 = 42 ; static const uint8_t P9N2_MCA_MBA_DBG0Q_RESERVED_42_47_LEN = 6 ; static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_WAT_FARB_RRQ_GT = 48 ; static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_WAT_FARB_RRQ_GT_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_WAT_FARB_WRQ_GT = 52 ; static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_WAT_FARB_WRQ_GT_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_WAT_FARB_REF_GT = 56 ; static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_WAT_FARB_REF_GT_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_WAT_FARB_CAL_GT = 60 ; static const uint8_t P9N2_MCA_MBA_DBG0Q_CFG_WAT_FARB_CAL_GT_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_FORCE_WR_ENTRY0_HP = 0 ; static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_FORCE_WR_ENTRY0_HP_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_FORCE_RD_ENTRY0_HP = 4 ; static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_FORCE_RD_ENTRY0_HP_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_FP_DIS = 8 ; static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_FP_DIS_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_DIS_RD_PG = 12 ; static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_DIS_RD_PG_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_DIS_WR_PG = 16 ; static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_DIS_WR_PG_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_PUP_ALL = 20 ; static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_PUP_ALL_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_EXIT_STR = 24 ; static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_EXIT_STR_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_REF_HP = 28 ; static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_REF_HP_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_REF_SYNC = 32 ; static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_REF_SYNC_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_REF_SAFE = 36 ; static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_REF_SAFE_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_CAL_SYNC = 40 ; static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_CAL_SYNC_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_RRQ_MNT_GT = 44 ; static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_RRQ_MNT_GT_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_WRQ_MNT_GT = 48 ; static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_WRQ_MNT_GT_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_SET_FIR = 52 ; static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_SET_FIR_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_EMER_TH = 56 ; static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_EMER_TH_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_START_RECOVERY = 60 ; static const uint8_t P9N2_MCA_MBA_DBG1Q_CFG_WAT_START_RECOVERY_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_DSM0Q_CFG_RODT_START_DLY = 0 ; static const uint8_t P9N2_MCA_MBA_DSM0Q_CFG_RODT_START_DLY_LEN = 6 ; static const uint8_t P9N2_MCA_MBA_DSM0Q_CFG_RODT_END_DLY = 6 ; static const uint8_t P9N2_MCA_MBA_DSM0Q_CFG_RODT_END_DLY_LEN = 6 ; static const uint8_t P9N2_MCA_MBA_DSM0Q_CFG_WODT_START_DLY = 12 ; static const uint8_t P9N2_MCA_MBA_DSM0Q_CFG_WODT_START_DLY_LEN = 6 ; static const uint8_t P9N2_MCA_MBA_DSM0Q_CFG_WODT_END_DLY = 18 ; static const uint8_t P9N2_MCA_MBA_DSM0Q_CFG_WODT_END_DLY_LEN = 6 ; static const uint8_t P9N2_MCA_MBA_DSM0Q_CFG_WRDONE_DLY = 24 ; static const uint8_t P9N2_MCA_MBA_DSM0Q_CFG_WRDONE_DLY_LEN = 6 ; static const uint8_t P9N2_MCA_MBA_DSM0Q_CFG_WRDATA_DLY = 30 ; static const uint8_t P9N2_MCA_MBA_DSM0Q_CFG_WRDATA_DLY_LEN = 6 ; static const uint8_t P9N2_MCA_MBA_DSM0Q_CFG_RDTAG_DLY = 36 ; static const uint8_t P9N2_MCA_MBA_DSM0Q_CFG_RDTAG_DLY_LEN = 6 ; static const uint8_t P9N2_MCA_MBA_DSM0Q_CFG_RDTAG_MBX_CYCLE = 42 ; static const uint8_t P9N2_MCA_MBA_DSM0Q_CFG_RODT_BC4_END_DLY = 43 ; static const uint8_t P9N2_MCA_MBA_DSM0Q_CFG_RODT_BC4_END_DLY_LEN = 6 ; static const uint8_t P9N2_MCA_MBA_DSM0Q_CFG_WODT_BC4_END_DLY = 49 ; static const uint8_t P9N2_MCA_MBA_DSM0Q_CFG_WODT_BC4_END_DLY_LEN = 6 ; static const uint8_t P9N2_MCA_MBA_DSM0Q_RESERVED_55_63 = 55 ; static const uint8_t P9N2_MCA_MBA_DSM0Q_RESERVED_55_63_LEN = 9 ; static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_WRQ_HANG = 0 ; static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_RRQ_HANG = 1 ; static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_DSM_PE = 2 ; static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_TMR_PE = 3 ; static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_RRQ_PE = 4 ; static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_WRQ_PE = 5 ; static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_FARB_PE = 6 ; static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_PC_PE = 7 ; static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_CAL0_PE = 8 ; static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_CAL1_PE = 9 ; static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_CAL2_PE = 10 ; static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_CAL3_PE = 11 ; static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_DDR_IF_SM_1HOT = 12 ; static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_CAL_SM_1HOT = 13 ; static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_RANK_SM_1HOT = 14 ; static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_RESERVED_15 = 15 ; static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_PC_CAL_PCFSM_1HOT = 16 ; static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_FARB_CAL_RECVFSM_1HOT = 17 ; static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_RESERVED_18_23 = 18 ; static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_RESERVED_18_23_LEN = 6 ; static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_RCMD_ASYNC_IF = 24 ; static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_PF_PROMOTE_ASYNC_IF = 25 ; static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_CANCEL_ACK_ASYNC_IF = 26 ; static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_FARB_CMD_PE_HOLD_OUT = 27 ; static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_DSM_CMD_PE_HOLD_OUT = 28 ; static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_RESERVED_29_30 = 29 ; static const uint8_t P9N2_MCA_MBA_ERR_REPORTQ_RESERVED_29_30_LEN = 2 ; static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_MISR_BLOCK = 0 ; static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_MISR_BLOCK_LEN = 16 ; static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_MISR_FEEDBACK_ENABLE = 16 ; static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_2N_ADDR = 17 ; static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_ADDR_CLK_EN_ALWAYS_ON = 18 ; static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_ADDR_CLK_EN_SAME_AS_OE = 19 ; static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_ACT_SAME_RANK_HOLD_TIME = 20 ; static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_ACT_SAME_RANK_HOLD_TIME_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_MAX_READS_IN_A_ROW = 24 ; static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_MAX_READS_IN_A_ROW_LEN = 7 ; static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_MAX_WRITES_IN_A_ROW = 31 ; static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_MAX_WRITES_IN_A_ROW_LEN = 7 ; static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_PARITY_AFTER_CMD = 38 ; static const uint8_t P9N2_MCA_MBA_FARB0Q_RESERVED_39 = 39 ; static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_INJECT_PARITY_ERR_ADDR5 = 40 ; static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_BW_WINDOW_SIZE = 41 ; static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_BW_WINDOW_SIZE_LEN = 2 ; static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_PARITY_DETECT_TIME = 43 ; static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_PARITY_DETECT_TIME_LEN = 5 ; static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_RCD_PROTECTION_TIME = 48 ; static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_RCD_PROTECTION_TIME_LEN = 6 ; static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_DISABLE_RCD_RECOVERY = 54 ; static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_OE_ALWAYS_ON = 55 ; static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_FARB_CLOSE_ALL_PAGES = 56 ; static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_PORT_FAIL_DISABLE = 57 ; static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_OE_ALL_CKE_POWERED_DOWN = 58 ; static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_INJECT_PARITY_ERR_CONSTANT = 59 ; static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_FINISH_WR_BEFORE_RD = 60 ; static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_OPT_RD_SIZE = 61 ; static const uint8_t P9N2_MCA_MBA_FARB0Q_CFG_OPT_RD_SIZE_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT0_S0_CID = 0 ; static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT0_S0_CID_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT0_S1_CID = 3 ; static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT0_S1_CID_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT0_S2_CID = 6 ; static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT0_S2_CID_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT0_S3_CID = 9 ; static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT0_S3_CID_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT0_S4_CID = 12 ; static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT0_S4_CID_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT0_S5_CID = 15 ; static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT0_S5_CID_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT0_S6_CID = 18 ; static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT0_S6_CID_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT0_S7_CID = 21 ; static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT0_S7_CID_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT1_S0_CID = 24 ; static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT1_S0_CID_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT1_S1_CID = 27 ; static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT1_S1_CID_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT1_S2_CID = 30 ; static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT1_S2_CID_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT1_S3_CID = 33 ; static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT1_S3_CID_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT1_S4_CID = 36 ; static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT1_S4_CID_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT1_S5_CID = 39 ; static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT1_S5_CID_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT1_S6_CID = 42 ; static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT1_S6_CID_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT1_S7_CID = 45 ; static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_SLOT1_S7_CID_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_DIS_SMDR = 48 ; static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_DDR4_PARITY_ON_CID_DIS = 49 ; static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_RSV0 = 50 ; static const uint8_t P9N2_MCA_MBA_FARB1Q_CFG_RSV0_LEN = 14 ; static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK0_RD_ODT = 0 ; static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK0_RD_ODT_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK1_RD_ODT = 4 ; static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK1_RD_ODT_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK2_RD_ODT = 8 ; static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK2_RD_ODT_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK3_RD_ODT = 12 ; static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK3_RD_ODT_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK4_RD_ODT = 16 ; static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK4_RD_ODT_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK5_RD_ODT = 20 ; static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK5_RD_ODT_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK6_RD_ODT = 24 ; static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK6_RD_ODT_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK7_RD_ODT = 28 ; static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK7_RD_ODT_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK0_WR_ODT = 32 ; static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK0_WR_ODT_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK1_WR_ODT = 36 ; static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK1_WR_ODT_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK2_WR_ODT = 40 ; static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK2_WR_ODT_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK3_WR_ODT = 44 ; static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK3_WR_ODT_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK4_WR_ODT = 48 ; static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK4_WR_ODT_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK5_WR_ODT = 52 ; static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK5_WR_ODT_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK6_WR_ODT = 56 ; static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK6_WR_ODT_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK7_WR_ODT = 60 ; static const uint8_t P9N2_MCA_MBA_FARB2Q_CFG_RANK7_WR_ODT_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_FARB3Q_CFG_NM_N_PER_SLOT = 0 ; static const uint8_t P9N2_MCA_MBA_FARB3Q_CFG_NM_N_PER_SLOT_LEN = 15 ; static const uint8_t P9N2_MCA_MBA_FARB3Q_CFG_NM_N_PER_PORT = 15 ; static const uint8_t P9N2_MCA_MBA_FARB3Q_CFG_NM_N_PER_PORT_LEN = 16 ; static const uint8_t P9N2_MCA_MBA_FARB3Q_CFG_NM_M = 31 ; static const uint8_t P9N2_MCA_MBA_FARB3Q_CFG_NM_M_LEN = 14 ; static const uint8_t P9N2_MCA_MBA_FARB3Q_CFG_NM_RAS_WEIGHT = 45 ; static const uint8_t P9N2_MCA_MBA_FARB3Q_CFG_NM_RAS_WEIGHT_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_FARB3Q_CFG_NM_CAS_WEIGHT = 48 ; static const uint8_t P9N2_MCA_MBA_FARB3Q_CFG_NM_CAS_WEIGHT_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_FARB3Q_RESERVED_51 = 51 ; static const uint8_t P9N2_MCA_MBA_FARB3Q_RESERVED_52 = 52 ; static const uint8_t P9N2_MCA_MBA_FARB3Q_CFG_NM_CHANGE_AFTER_SYNC = 53 ; static const uint8_t P9N2_MCA_MBA_FARB3Q_RESERVED_54_63 = 54 ; static const uint8_t P9N2_MCA_MBA_FARB3Q_RESERVED_54_63_LEN = 10 ; static const uint8_t P9N2_MCA_MBA_FARB4Q_CFG_NOISE_WAIT_TIME = 0 ; static const uint8_t P9N2_MCA_MBA_FARB4Q_CFG_NOISE_WAIT_TIME_LEN = 16 ; static const uint8_t P9N2_MCA_MBA_FARB4Q_CFG_PRECHARGE_WAIT_TIME = 16 ; static const uint8_t P9N2_MCA_MBA_FARB4Q_CFG_PRECHARGE_WAIT_TIME_LEN = 6 ; static const uint8_t P9N2_MCA_MBA_FARB4Q_CFG_SIM_FAST_NOISE_WINDOW = 22 ; static const uint8_t P9N2_MCA_MBA_FARB4Q_RESERVED_23_26 = 23 ; static const uint8_t P9N2_MCA_MBA_FARB4Q_RESERVED_23_26_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_FARB4Q_EMERGENCY_N = 27 ; static const uint8_t P9N2_MCA_MBA_FARB4Q_EMERGENCY_N_LEN = 15 ; static const uint8_t P9N2_MCA_MBA_FARB4Q_EMERGENCY_M = 42 ; static const uint8_t P9N2_MCA_MBA_FARB4Q_EMERGENCY_M_LEN = 14 ; static const uint8_t P9N2_MCA_MBA_FARB4Q_RESERVED_56_63 = 56 ; static const uint8_t P9N2_MCA_MBA_FARB4Q_RESERVED_56_63_LEN = 8 ; static const uint8_t P9N2_MCA_MBA_FARB5Q_CFG_DDR_DPHY_NCLK = 0 ; static const uint8_t P9N2_MCA_MBA_FARB5Q_CFG_DDR_DPHY_NCLK_LEN = 2 ; static const uint8_t P9N2_MCA_MBA_FARB5Q_CFG_DDR_DPHY_PCLK = 2 ; static const uint8_t P9N2_MCA_MBA_FARB5Q_CFG_DDR_DPHY_PCLK_LEN = 2 ; static const uint8_t P9N2_MCA_MBA_FARB5Q_CFG_DDR_RESETN = 4 ; static const uint8_t P9N2_MCA_MBA_FARB5Q_CFG_CCS_ADDR_MUX_SEL = 5 ; static const uint8_t P9N2_MCA_MBA_FARB5Q_CFG_CCS_INST_RESET_ENABLE = 6 ; static const uint8_t P9N2_MCA_MBA_FARB5Q_CFG_GP_BIT_3_ENABLE = 7 ; static const uint8_t P9N2_MCA_MBA_FARB5Q_CFG_FORCE_MCLK_LOW_N = 8 ; static const uint8_t P9N2_MCA_MBA_FARB5Q_RESERVED_56_63 = 9 ; static const uint8_t P9N2_MCA_MBA_FARB5Q_RESERVED_56_63_LEN = 7 ; static const uint8_t P9N2_MCA_MBA_FARB6Q_CFG_BW_SNAPSHOT = 0 ; static const uint8_t P9N2_MCA_MBA_FARB6Q_CFG_BW_SNAPSHOT_LEN = 11 ; static const uint8_t P9N2_MCA_MBA_FARB6Q_CFG_CKE_PUP_STATE = 11 ; static const uint8_t P9N2_MCA_MBA_FARB6Q_CFG_CKE_PUP_STATE_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_FARB6Q_CFG_STR_STATE = 15 ; static const uint8_t P9N2_MCA_MBA_FARB6Q_CFG_RRQ_DEPTH = 16 ; static const uint8_t P9N2_MCA_MBA_FARB6Q_CFG_RRQ_DEPTH_LEN = 5 ; static const uint8_t P9N2_MCA_MBA_FARB6Q_CFG_WRQ_DEPTH = 21 ; static const uint8_t P9N2_MCA_MBA_FARB6Q_CFG_WRQ_DEPTH_LEN = 5 ; static const uint8_t P9N2_MCA_MBA_FARB6Q_CFG_RCD_PARITY_DLY = 26 ; static const uint8_t P9N2_MCA_MBA_FARB6Q_CFG_RCD_PARITY_DLY_LEN = 5 ; static const uint8_t P9N2_MCA_MBA_FARB6Q_CFG_EVENTN = 31 ; static const uint8_t P9N2_MCA_MBA_FARB7Q_EMER_THROTTLE_IP = 0 ; static const uint8_t P9N2_MCA_MBA_FARB8Q_SAFE_REFRESH_MODE = 0 ; static const uint8_t P9N2_MCBIST_MBA_MCBERRPTQ_MCB_FIR_CCS_ERR_HOLD_OUT = 0 ; static const uint8_t P9N2_MCBIST_MBA_MCBERRPTQ_MCB_FIR_MCBFSM_ERR_HOLD_OUT = 1 ; static const uint8_t P9N2_MCBIST_MBA_MCBERRPTQ_MCB_CNTLQ_PE_HOLD_OUT = 2 ; static const uint8_t P9N2_MCBIST_MBA_MCBERRPTQ_CCS_CNTLQ_PE_HOLD_OUT = 3 ; static const uint8_t P9N2_MCBIST_MBA_MCBERRPTQ_MCBCNTL_PE_HOLD_OUT = 4 ; static const uint8_t P9N2_MCBIST_MBA_MCBERRPTQ_MCBAGEN_PE_HOLD_OUT = 5 ; static const uint8_t P9N2_MCBIST_MBA_MCBERRPTQ_MAINT_CCS_PE_HOLD_OUT = 6 ; static const uint8_t P9N2_MCBIST_MBA_MCBERRPTQ_MCBDGEN_PE_HOLD_OUT = 7 ; static const uint8_t P9N2_MCBIST_MBA_MCBERRPTQ_MCBERR_SCOM_PE_HOLD_OUT = 8 ; static const uint8_t P9N2_MCBIST_MBA_MCBERRPTQ_ECC_MCBIST_OUT_OF_SYNC_HOLD_OUT = 9 ; static const uint8_t P9N2_MCBIST_MBA_MCBERRPTQ_SRQ_MCBIST_OUT_OF_SYNC_HOLD_OUT = 10 ; static const uint8_t P9N2_MCBIST_MBA_MCBERRPTQ_WRD_MCBIST_OUT_OF_SYNC_HOLD_OUT = 11 ; static const uint8_t P9N2_MCBIST_MBA_MCBERRPTQ_SRQ_CCS_UNEXPECTED_PORT_ACTIVE_HOLD_OUT = 12 ; static const uint8_t P9N2_MCBIST_MBA_MCBERRPTQ_FATAL_CNFG_HOLD_OUT = 13 ; static const uint8_t P9N2_MCA_MBA_PMU0Q_READ_COUNT = 0 ; static const uint8_t P9N2_MCA_MBA_PMU0Q_READ_COUNT_LEN = 32 ; static const uint8_t P9N2_MCA_MBA_PMU0Q_WRITE_COUNT = 32 ; static const uint8_t P9N2_MCA_MBA_PMU0Q_WRITE_COUNT_LEN = 32 ; static const uint8_t P9N2_MCA_MBA_PMU1Q_ACTIVATE_COUNT = 0 ; static const uint8_t P9N2_MCA_MBA_PMU1Q_ACTIVATE_COUNT_LEN = 32 ; static const uint8_t P9N2_MCA_MBA_PMU1Q_PU_COUNTS = 32 ; static const uint8_t P9N2_MCA_MBA_PMU1Q_PU_COUNTS_LEN = 32 ; static const uint8_t P9N2_MCA_MBA_PMU2Q_FRAME_COUNT = 0 ; static const uint8_t P9N2_MCA_MBA_PMU2Q_FRAME_COUNT_LEN = 32 ; static const uint8_t P9N2_MCA_MBA_PMU3Q_LOW_IDLE_THRESHOLD = 0 ; static const uint8_t P9N2_MCA_MBA_PMU3Q_LOW_IDLE_THRESHOLD_LEN = 16 ; static const uint8_t P9N2_MCA_MBA_PMU3Q_MED_IDLE_THRESHOLD = 16 ; static const uint8_t P9N2_MCA_MBA_PMU3Q_MED_IDLE_THRESHOLD_LEN = 16 ; static const uint8_t P9N2_MCA_MBA_PMU3Q_HIGH_IDLE_THRESHOLD = 32 ; static const uint8_t P9N2_MCA_MBA_PMU3Q_HIGH_IDLE_THRESHOLD_LEN = 32 ; static const uint8_t P9N2_MCA_MBA_PMU4Q_BASE_IDLE_COUNT = 0 ; static const uint8_t P9N2_MCA_MBA_PMU4Q_BASE_IDLE_COUNT_LEN = 32 ; static const uint8_t P9N2_MCA_MBA_PMU4Q_LOW_IDLE_COUNT = 32 ; static const uint8_t P9N2_MCA_MBA_PMU4Q_LOW_IDLE_COUNT_LEN = 32 ; static const uint8_t P9N2_MCA_MBA_PMU5Q_MED_IDLE_COUNT = 0 ; static const uint8_t P9N2_MCA_MBA_PMU5Q_MED_IDLE_COUNT_LEN = 32 ; static const uint8_t P9N2_MCA_MBA_PMU5Q_HIGH_IDLE_COUNT = 32 ; static const uint8_t P9N2_MCA_MBA_PMU5Q_HIGH_IDLE_COUNT_LEN = 32 ; static const uint8_t P9N2_MCA_MBA_PMU6Q_EVENT0_COUNTER = 0 ; static const uint8_t P9N2_MCA_MBA_PMU6Q_EVENT0_COUNTER_LEN = 16 ; static const uint8_t P9N2_MCA_MBA_PMU6Q_EVENT1_COUNTER = 16 ; static const uint8_t P9N2_MCA_MBA_PMU6Q_EVENT1_COUNTER_LEN = 16 ; static const uint8_t P9N2_MCA_MBA_PMU6Q_EVENT2_COUNTER = 32 ; static const uint8_t P9N2_MCA_MBA_PMU6Q_EVENT2_COUNTER_LEN = 16 ; static const uint8_t P9N2_MCA_MBA_PMU6Q_EVENT3_COUNTER = 48 ; static const uint8_t P9N2_MCA_MBA_PMU6Q_EVENT3_COUNTER_LEN = 16 ; static const uint8_t P9N2_MCA_MBA_PMU7Q_CFG_EVENT0_SELECT = 0 ; static const uint8_t P9N2_MCA_MBA_PMU7Q_CFG_EVENT0_SELECT_LEN = 6 ; static const uint8_t P9N2_MCA_MBA_PMU7Q_CFG_EVENT1_SELECT = 6 ; static const uint8_t P9N2_MCA_MBA_PMU7Q_CFG_EVENT1_SELECT_LEN = 6 ; static const uint8_t P9N2_MCA_MBA_PMU7Q_CFG_EVENT2_SELECT = 12 ; static const uint8_t P9N2_MCA_MBA_PMU7Q_CFG_EVENT2_SELECT_LEN = 6 ; static const uint8_t P9N2_MCA_MBA_PMU7Q_CFG_EVENT3_SELECT = 18 ; static const uint8_t P9N2_MCA_MBA_PMU7Q_CFG_EVENT3_SELECT_LEN = 6 ; static const uint8_t P9N2_MCA_MBA_PMU7Q_CFG_PRESCALER_C0 = 24 ; static const uint8_t P9N2_MCA_MBA_PMU7Q_CFG_PRESCALER_C0_LEN = 2 ; static const uint8_t P9N2_MCA_MBA_PMU7Q_CFG_PRESCALER_C1 = 26 ; static const uint8_t P9N2_MCA_MBA_PMU7Q_CFG_PRESCALER_C1_LEN = 2 ; static const uint8_t P9N2_MCA_MBA_PMU7Q_CFG_PRESCALER_C2 = 28 ; static const uint8_t P9N2_MCA_MBA_PMU7Q_CFG_PRESCALER_C2_LEN = 2 ; static const uint8_t P9N2_MCA_MBA_PMU7Q_CFG_PRESCALER_C3 = 30 ; static const uint8_t P9N2_MCA_MBA_PMU7Q_CFG_PRESCALER_C3_LEN = 2 ; static const uint8_t P9N2_MCA_MBA_PMU7Q_CASCADE = 32 ; static const uint8_t P9N2_MCA_MBA_PMU7Q_CASCADE_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_PMU7Q_FREEZE = 35 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD0_TYPE = 0 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD0_TYPE_LEN = 2 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD0_MRANK_MATCH_EN = 2 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD0_SRANK_MATCH_EN = 3 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD0_BG_MATCH_EN = 4 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD0_BANK_MATCH_EN = 5 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD0_MRANK = 6 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD0_MRANK_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD0_SRANK = 9 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD0_SRANK_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD0_BG = 12 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD0_BG_LEN = 2 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD0_BANK = 14 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD0_BANK_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD1_TYPE = 17 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD1_TYPE_LEN = 2 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD1_MRANK_MATCH_EN = 19 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD1_SRANK_MATCH_EN = 20 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD1_BG_MATCH_EN = 21 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD1_BANK_MATCH_EN = 22 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD1_MRANK = 23 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD1_MRANK_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD1_SRANK = 26 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD1_SRANK_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD1_BG = 29 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD1_BG_LEN = 2 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD1_BANK = 31 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD1_BANK_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD2_TYPE = 34 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD2_TYPE_LEN = 2 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD2_MRANK_MATCH_EN = 36 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD2_SRANK_MATCH_EN = 37 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD2_BG_MATCH_EN = 38 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD2_BANK_MATCH_EN = 39 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD2_MRANK = 40 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD2_MRANK_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD2_SRANK = 43 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD2_SRANK_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD2_BG = 46 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD2_BG_LEN = 2 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD2_BANK = 48 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_CFG_CMD2_BANK_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_RESERVED_51_63 = 51 ; static const uint8_t P9N2_MCA_MBA_PMU8Q_RESERVED_51_63_LEN = 13 ; static const uint8_t P9N2_MCA_MBA_RRQ0Q_CFG_RRQ_SKIP_LIMIT = 0 ; static const uint8_t P9N2_MCA_MBA_RRQ0Q_CFG_RRQ_SKIP_LIMIT_LEN = 6 ; static const uint8_t P9N2_MCA_MBA_RRQ0Q_CFG_RRQ_FIFO_MODE = 6 ; static const uint8_t P9N2_MCA_MBA_RRQ0Q_CFG_RRQ_SINGLE_THREAD_MODE = 7 ; static const uint8_t P9N2_MCA_MBA_RRQ0Q_RESERVED_8_10 = 8 ; static const uint8_t P9N2_MCA_MBA_RRQ0Q_RESERVED_8_10_LEN = 3 ; static const uint8_t P9N2_MCA_MBA_RRQ0Q_CFG_DISABLE_RD_PG_MODE = 11 ; static const uint8_t P9N2_MCA_MBA_RRQ0Q_CFG_DISABLE_FAST_PATH = 12 ; static const uint8_t P9N2_MCA_MBA_RRQ0Q_CFG_RD_IDLE_ALLOW_WR = 13 ; static const uint8_t P9N2_MCA_MBA_RRQ0Q_CFG_RD_IDLE_ALLOW_WR_LEN = 11 ; static const uint8_t P9N2_MCA_MBA_RRQ0Q_CFG_RDBUFF_CAPACITY_LIMIT = 24 ; static const uint8_t P9N2_MCA_MBA_RRQ0Q_CFG_RDBUFF_CAPACITY_LIMIT_LEN = 6 ; static const uint8_t P9N2_MCA_MBA_RRQ0Q_CFG_RMWBUFF_CAPACITY_LIMIT = 30 ; static const uint8_t P9N2_MCA_MBA_RRQ0Q_CFG_RMWBUFF_CAPACITY_LIMIT_LEN = 7 ; static const uint8_t P9N2_MCA_MBA_RRQ0Q_RESERVED_37_56 = 37 ; static const uint8_t P9N2_MCA_MBA_RRQ0Q_RESERVED_37_56_LEN = 20 ; static const uint8_t P9N2_MCA_MBA_RRQ0Q_CFG_RRQ_ACT_NUM_READS_PENDING = 57 ; static const uint8_t P9N2_MCA_MBA_RRQ0Q_CFG_RRQ_ACT_NUM_READS_PENDING_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_RRQ0Q_CFG_INJ_CANCEL_ACK_ERR = 61 ; static const uint8_t P9N2_MCA_MBA_RRQ0Q_CFG_RRQ_ENTRY0_ENABLE = 62 ; static const uint8_t P9N2_MCA_MBA_RRQ0Q_RESERVED_63 = 63 ; static const uint8_t P9N2_MCA_MBA_TMR0Q_RRDM_DLY = 0 ; static const uint8_t P9N2_MCA_MBA_TMR0Q_RRDM_DLY_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_TMR0Q_RRSMSR_DLY = 4 ; static const uint8_t P9N2_MCA_MBA_TMR0Q_RRSMSR_DLY_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_TMR0Q_RRSMDR_DLY = 8 ; static const uint8_t P9N2_MCA_MBA_TMR0Q_RRSMDR_DLY_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_TMR0Q_RROP_DLY = 12 ; static const uint8_t P9N2_MCA_MBA_TMR0Q_RROP_DLY_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_TMR0Q_WWDM_DLY = 16 ; static const uint8_t P9N2_MCA_MBA_TMR0Q_WWDM_DLY_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_TMR0Q_WWSMSR_DLY = 20 ; static const uint8_t P9N2_MCA_MBA_TMR0Q_WWSMSR_DLY_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_TMR0Q_WWSMDR_DLY = 24 ; static const uint8_t P9N2_MCA_MBA_TMR0Q_WWSMDR_DLY_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_TMR0Q_WWOP_DLY = 28 ; static const uint8_t P9N2_MCA_MBA_TMR0Q_WWOP_DLY_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_TMR0Q_RWDM_DLY = 32 ; static const uint8_t P9N2_MCA_MBA_TMR0Q_RWDM_DLY_LEN = 5 ; static const uint8_t P9N2_MCA_MBA_TMR0Q_RWSMSR_DLY = 37 ; static const uint8_t P9N2_MCA_MBA_TMR0Q_RWSMSR_DLY_LEN = 5 ; static const uint8_t P9N2_MCA_MBA_TMR0Q_RWSMDR_DLY = 42 ; static const uint8_t P9N2_MCA_MBA_TMR0Q_RWSMDR_DLY_LEN = 5 ; static const uint8_t P9N2_MCA_MBA_TMR0Q_WRDM_DLY = 47 ; static const uint8_t P9N2_MCA_MBA_TMR0Q_WRDM_DLY_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_TMR0Q_WRSMSR_DLY = 51 ; static const uint8_t P9N2_MCA_MBA_TMR0Q_WRSMSR_DLY_LEN = 6 ; static const uint8_t P9N2_MCA_MBA_TMR0Q_WRSMDR_DLY = 57 ; static const uint8_t P9N2_MCA_MBA_TMR0Q_WRSMDR_DLY_LEN = 6 ; static const uint8_t P9N2_MCA_MBA_TMR0Q_RESERVED_63 = 63 ; static const uint8_t P9N2_MCA_MBA_TMR1Q_RRSBG_DLY = 0 ; static const uint8_t P9N2_MCA_MBA_TMR1Q_RRSBG_DLY_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_TMR1Q_WRSBG_DLY = 4 ; static const uint8_t P9N2_MCA_MBA_TMR1Q_WRSBG_DLY_LEN = 6 ; static const uint8_t P9N2_MCA_MBA_TMR1Q_CFG_TFAW = 10 ; static const uint8_t P9N2_MCA_MBA_TMR1Q_CFG_TFAW_LEN = 6 ; static const uint8_t P9N2_MCA_MBA_TMR1Q_CFG_TRCD = 16 ; static const uint8_t P9N2_MCA_MBA_TMR1Q_CFG_TRCD_LEN = 5 ; static const uint8_t P9N2_MCA_MBA_TMR1Q_CFG_TRP = 21 ; static const uint8_t P9N2_MCA_MBA_TMR1Q_CFG_TRP_LEN = 5 ; static const uint8_t P9N2_MCA_MBA_TMR1Q_CFG_TRAS = 26 ; static const uint8_t P9N2_MCA_MBA_TMR1Q_CFG_TRAS_LEN = 6 ; static const uint8_t P9N2_MCA_MBA_TMR1Q_RESERVED_32_40 = 32 ; static const uint8_t P9N2_MCA_MBA_TMR1Q_RESERVED_32_40_LEN = 9 ; static const uint8_t P9N2_MCA_MBA_TMR1Q_CFG_WR2PRE = 41 ; static const uint8_t P9N2_MCA_MBA_TMR1Q_CFG_WR2PRE_LEN = 7 ; static const uint8_t P9N2_MCA_MBA_TMR1Q_CFG_RD2PRE = 48 ; static const uint8_t P9N2_MCA_MBA_TMR1Q_CFG_RD2PRE_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_TMR1Q_TRRD = 52 ; static const uint8_t P9N2_MCA_MBA_TMR1Q_TRRD_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_TMR1Q_TRRD_SBG = 56 ; static const uint8_t P9N2_MCA_MBA_TMR1Q_TRRD_SBG_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_TMR1Q_CFG_ACT_TO_DIFF_RANK_DLY = 60 ; static const uint8_t P9N2_MCA_MBA_TMR1Q_CFG_ACT_TO_DIFF_RANK_DLY_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_TMR2Q_CFG_BANK_BUSY_FSM_DIS = 0 ; static const uint8_t P9N2_MCA_MBA_TMR2Q_CFG_BANK_BUSY_FSM_DIS_LEN = 20 ; static const uint8_t P9N2_MCA_MBA_TMR2Q_CFG_BANK_BUSY_OPEN_PAGE_DIS = 20 ; static const uint8_t P9N2_MCA_MBA_TMR2Q_CFG_BANK_BUSY_OPEN_PAGE_DIS_LEN = 12 ; static const uint8_t P9N2_MCA_MBA_TMR2Q_RESERVED_32_63 = 32 ; static const uint8_t P9N2_MCA_MBA_TMR2Q_RESERVED_32_63_LEN = 32 ; static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_WRITE_HW_MARK = 0 ; static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_WRITE_HW_MARK_LEN = 5 ; static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_WRQ_FIFO_MODE = 5 ; static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_DISABLE_WR_PG_MODE = 6 ; static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_WRQ_ENTRY0_HP_DLY = 7 ; static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_WRQ_ENTRY0_HP_DLY_LEN = 12 ; static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_WRQ_FLUSH_WR_RANK = 19 ; static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_WRQ_ENABLE_NON_HP_WR = 20 ; static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_ENTRY0_MIN_FOR_RRQ_IDLE_WR = 21 ; static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_ENTRY0_MIN_FOR_RRQ_IDLE_WR_LEN = 12 ; static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_WRITE_LW_MARK = 33 ; static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_WRITE_LW_MARK_LEN = 5 ; static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_WRQ_SKIP_LIMIT = 38 ; static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_WRQ_SKIP_LIMIT_LEN = 6 ; static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_WRQ_SINGLE_THREAD_MODE = 44 ; static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_RQ_HANG_THRESHOLD = 45 ; static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_RQ_HANG_THRESHOLD_LEN = 8 ; static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_WRQ_SKIP_RRQ_ENTRIES_DIS = 53 ; static const uint8_t P9N2_MCA_MBA_WRQ0Q_RESERVED_54 = 54 ; static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_WRQ_ACT_NUM_WRITES_PENDING = 55 ; static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_WRQ_ACT_NUM_WRITES_PENDING_LEN = 4 ; static const uint8_t P9N2_MCA_MBA_WRQ0Q_CFG_WRQ_ALLOW_NEW_PAGE_COMMIT = 59 ; static const uint8_t P9N2_MCA_MBA_WRQ0Q_RESERVED_60_63 = 60 ; static const uint8_t P9N2_MCA_MBA_WRQ0Q_RESERVED_60_63_LEN = 4 ; static const uint8_t P9N2_MCBIST_MBECTLQ_ATOMIC_ALT_CE_INJ = 0 ; static const uint8_t P9N2_MCBIST_MBECTLQ_ATOMIC_ALT_CHIP_KILL_INJ = 1 ; static const uint8_t P9N2_MCBIST_MBECTLQ_ATOMIC_ALT_UE_INJ = 2 ; static const uint8_t P9N2_MCBIST_MBECTLQ_ATOMIC_ALT_SUE_INJ = 3 ; static const uint8_t P9N2_MCBIST_MBECTLQ_ATOMIC_ALT_INJ_SYM_SEL = 4 ; static const uint8_t P9N2_MCBIST_MBECTLQ_ATOMIC_ALT_INJ_SYM_SEL_LEN = 7 ; static const uint8_t P9N2_MCBIST_MBECTLQ_RESERVE_11 = 11 ; static const uint8_t P9N2_MCBIST_MBECTLQ_SCOM_CMD_REG_INJ_MODE = 12 ; static const uint8_t P9N2_MCBIST_MBECTLQ_SCOM_CMD_REG_INJ = 13 ; static const uint8_t P9N2_MCBIST_MBECTLQ_MCBIST_FSM_INJ_MODE = 14 ; static const uint8_t P9N2_MCBIST_MBECTLQ_MCBIST_FSM_INJ_REG = 15 ; static const uint8_t P9N2_MCBIST_MBECTLQ_CCS_FSM_INJ_MODE = 16 ; static const uint8_t P9N2_MCBIST_MBECTLQ_CCS_FSM_INJ_REG = 17 ; static const uint8_t P9N2_MCBIST_MBECTLQ_RESERVED_18_31 = 18 ; static const uint8_t P9N2_MCBIST_MBECTLQ_RESERVED_18_31_LEN = 14 ; static const uint8_t P9N2_MCA_MBMDI_MDI_0 = 0 ; static const uint8_t P9N2_MCA_MBMDI_SUE_0 = 1 ; static const uint8_t P9N2_MCA_MBMDI_MDI_1 = 2 ; static const uint8_t P9N2_MCA_MBMDI_SUE_1 = 3 ; static const uint8_t P9N2_MCBIST_MBMPER0Q_PORT_0_MAINLINE_MPE_ADDR_TRAP = 0 ; static const uint8_t P9N2_MCBIST_MBMPER0Q_PORT_0_MAINLINE_MPE_ADDR_TRAP_LEN = 38 ; static const uint8_t P9N2_MCBIST_MBMPER0Q_PORT_0_MAINLINE_MPE_ON_RCE = 38 ; static const uint8_t P9N2_MCBIST_MBMPER0Q_RESERVED_39 = 39 ; static const uint8_t P9N2_MCBIST_MBMPER1Q_PORT_1_MAINLINE_MPE_ADDR_TRAP = 0 ; static const uint8_t P9N2_MCBIST_MBMPER1Q_PORT_1_MAINLINE_MPE_ADDR_TRAP_LEN = 38 ; static const uint8_t P9N2_MCBIST_MBMPER1Q_PORT_1_MAINLINE_MPE_ON_RCE = 38 ; static const uint8_t P9N2_MCBIST_MBMPER1Q_RESERVED_39 = 39 ; static const uint8_t P9N2_MCBIST_MBMPER2Q_PORT_2_MAINLINE_MPE_ADDR_TRAP = 0 ; static const uint8_t P9N2_MCBIST_MBMPER2Q_PORT_2_MAINLINE_MPE_ADDR_TRAP_LEN = 38 ; static const uint8_t P9N2_MCBIST_MBMPER2Q_PORT_2_MAINLINE_MPE_ON_RCE = 38 ; static const uint8_t P9N2_MCBIST_MBMPER2Q_RESERVED_39 = 39 ; static const uint8_t P9N2_MCBIST_MBMPER3Q_PORT_3_MAINLINE_MPE_ADDR_TRAP = 0 ; static const uint8_t P9N2_MCBIST_MBMPER3Q_PORT_3_MAINLINE_MPE_ADDR_TRAP_LEN = 38 ; static const uint8_t P9N2_MCBIST_MBMPER3Q_PORT_3_MAINLINE_MPE_ON_RCE = 38 ; static const uint8_t P9N2_MCBIST_MBMPER3Q_RESERVED_39 = 39 ; static const uint8_t P9N2_MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_ADDR_TRAP = 0 ; static const uint8_t P9N2_MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_ADDR_TRAP_LEN = 38 ; static const uint8_t P9N2_MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_ON_RCE = 38 ; static const uint8_t P9N2_MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_IS_TCE = 39 ; static const uint8_t P9N2_MCBIST_MBNCER1Q_PORT_1_MAINLINE_NCE_ADDR_TRAP = 0 ; static const uint8_t P9N2_MCBIST_MBNCER1Q_PORT_1_MAINLINE_NCE_ADDR_TRAP_LEN = 38 ; static const uint8_t P9N2_MCBIST_MBNCER1Q_PORT_1_MAINLINE_NCE_ON_RCE = 38 ; static const uint8_t P9N2_MCBIST_MBNCER1Q_PORT_1_MAINLINE_NCE_IS_TCE = 39 ; static const uint8_t P9N2_MCBIST_MBNCER2Q_PORT_2_MAINLINE_NCE_ADDR_TRAP = 0 ; static const uint8_t P9N2_MCBIST_MBNCER2Q_PORT_2_MAINLINE_NCE_ADDR_TRAP_LEN = 38 ; static const uint8_t P9N2_MCBIST_MBNCER2Q_PORT_2_MAINLINE_NCE_ON_RCE = 38 ; static const uint8_t P9N2_MCBIST_MBNCER2Q_PORT_2_MAINLINE_NCE_IS_TCE = 39 ; static const uint8_t P9N2_MCBIST_MBNCER3Q_PORT_3_MAINLINE_NCE_ADDR_TRAP = 0 ; static const uint8_t P9N2_MCBIST_MBNCER3Q_PORT_3_MAINLINE_NCE_ADDR_TRAP_LEN = 38 ; static const uint8_t P9N2_MCBIST_MBNCER3Q_PORT_3_MAINLINE_NCE_ON_RCE = 38 ; static const uint8_t P9N2_MCBIST_MBNCER3Q_PORT_3_MAINLINE_NCE_IS_TCE = 39 ; static const uint8_t P9N2_MCBIST_MBRCER0Q_PORT_0_MAINLINE_RCE_ADDR_TRAP = 0 ; static const uint8_t P9N2_MCBIST_MBRCER0Q_PORT_0_MAINLINE_RCE_ADDR_TRAP_LEN = 38 ; static const uint8_t P9N2_MCBIST_MBRCER0Q_RESERVED_38_39 = 38 ; static const uint8_t P9N2_MCBIST_MBRCER0Q_RESERVED_38_39_LEN = 2 ; static const uint8_t P9N2_MCBIST_MBRCER1Q_PORT_1_MAINLINE_RCE_ADDR_TRAP = 0 ; static const uint8_t P9N2_MCBIST_MBRCER1Q_PORT_1_MAINLINE_RCE_ADDR_TRAP_LEN = 38 ; static const uint8_t P9N2_MCBIST_MBRCER1Q_RESERVED_38_39 = 38 ; static const uint8_t P9N2_MCBIST_MBRCER1Q_RESERVED_38_39_LEN = 2 ; static const uint8_t P9N2_MCBIST_MBRCER2Q_PORT_2_MAINLINE_RCE_ADDR_TRAP = 0 ; static const uint8_t P9N2_MCBIST_MBRCER2Q_PORT_2_MAINLINE_RCE_ADDR_TRAP_LEN = 38 ; static const uint8_t P9N2_MCBIST_MBRCER2Q_RESERVED_38_39 = 38 ; static const uint8_t P9N2_MCBIST_MBRCER2Q_RESERVED_38_39_LEN = 2 ; static const uint8_t P9N2_MCBIST_MBRCER3Q_PORT_3_MAINLINE_RCE_ADDR_TRAP = 0 ; static const uint8_t P9N2_MCBIST_MBRCER3Q_PORT_3_MAINLINE_RCE_ADDR_TRAP_LEN = 38 ; static const uint8_t P9N2_MCBIST_MBRCER3Q_RESERVED_38_39 = 38 ; static const uint8_t P9N2_MCBIST_MBRCER3Q_RESERVED_38_39_LEN = 2 ; static const uint8_t P9N2_MCBIST_MBSEC0Q_INTERMITTENT_CE_COUNT = 0 ; static const uint8_t P9N2_MCBIST_MBSEC0Q_INTERMITTENT_CE_COUNT_LEN = 12 ; static const uint8_t P9N2_MCBIST_MBSEC0Q_SOFT_CE_COUNT = 12 ; static const uint8_t P9N2_MCBIST_MBSEC0Q_SOFT_CE_COUNT_LEN = 12 ; static const uint8_t P9N2_MCBIST_MBSEC0Q_HARD_CE_COUNT = 24 ; static const uint8_t P9N2_MCBIST_MBSEC0Q_HARD_CE_COUNT_LEN = 12 ; static const uint8_t P9N2_MCBIST_MBSEC0Q_INTERMITTENT_MCE_COUNT = 36 ; static const uint8_t P9N2_MCBIST_MBSEC0Q_INTERMITTENT_MCE_COUNT_LEN = 12 ; static const uint8_t P9N2_MCBIST_MBSEC0Q_SOFT_MCE_COUNT = 48 ; static const uint8_t P9N2_MCBIST_MBSEC0Q_SOFT_MCE_COUNT_LEN = 12 ; static const uint8_t P9N2_MCBIST_MBSEC1Q_HARD_MCE_COUNT = 0 ; static const uint8_t P9N2_MCBIST_MBSEC1Q_HARD_MCE_COUNT_LEN = 12 ; static const uint8_t P9N2_MCBIST_MBSEC1Q_ICE_COUNT = 12 ; static const uint8_t P9N2_MCBIST_MBSEC1Q_ICE_COUNT_LEN = 12 ; static const uint8_t P9N2_MCBIST_MBSEC1Q_UE_COUNT = 24 ; static const uint8_t P9N2_MCBIST_MBSEC1Q_UE_COUNT_LEN = 12 ; static const uint8_t P9N2_MCBIST_MBSEC1Q_AUE = 36 ; static const uint8_t P9N2_MCBIST_MBSEC1Q_AUE_LEN = 12 ; static const uint8_t P9N2_MCBIST_MBSEC1Q_RCE_COUNT = 48 ; static const uint8_t P9N2_MCBIST_MBSEC1Q_RCE_COUNT_LEN = 12 ; static const uint8_t P9N2_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_GALOIS_FIELD = 0 ; static const uint8_t P9N2_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_GALOIS_FIELD_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_MAGNITUDE_FIELD = 8 ; static const uint8_t P9N2_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_MAGNITUDE_FIELD_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_GALOIS_FIELD = 16 ; static const uint8_t P9N2_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_GALOIS_FIELD_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_MAGNITUDE_FIELD = 24 ; static const uint8_t P9N2_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_MAGNITUDE_FIELD_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSEVR0Q_PORT_1_MAINLINE_NCE_GALOIS_FIELD = 32 ; static const uint8_t P9N2_MCBIST_MBSEVR0Q_PORT_1_MAINLINE_NCE_GALOIS_FIELD_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSEVR0Q_PORT_1_MAINLINE_NCE_MAGNITUDE_FIELD = 40 ; static const uint8_t P9N2_MCBIST_MBSEVR0Q_PORT_1_MAINLINE_NCE_MAGNITUDE_FIELD_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSEVR0Q_PORT_1_MAINLINE_TCE_GALOIS_FIELD = 48 ; static const uint8_t P9N2_MCBIST_MBSEVR0Q_PORT_1_MAINLINE_TCE_GALOIS_FIELD_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSEVR0Q_PORT_1_MAINLINE_TCE_MAGNITUDE_FIELD = 56 ; static const uint8_t P9N2_MCBIST_MBSEVR0Q_PORT_1_MAINLINE_TCE_MAGNITUDE_FIELD_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSEVR1Q_PORT_2_MAINLINE_NCE_GALOIS_FIELD = 0 ; static const uint8_t P9N2_MCBIST_MBSEVR1Q_PORT_2_MAINLINE_NCE_GALOIS_FIELD_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSEVR1Q_PORT_2_MAINLINE_NCE_MAGNITUDE_FIELD = 8 ; static const uint8_t P9N2_MCBIST_MBSEVR1Q_PORT_2_MAINLINE_NCE_MAGNITUDE_FIELD_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSEVR1Q_PORT_2_MAINLINE_TCE_GALOIS_FIELD = 16 ; static const uint8_t P9N2_MCBIST_MBSEVR1Q_PORT_2_MAINLINE_TCE_GALOIS_FIELD_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSEVR1Q_PORT_2_MAINLINE_TCE_MAGNITUDE_FIELD = 24 ; static const uint8_t P9N2_MCBIST_MBSEVR1Q_PORT_2_MAINLINE_TCE_MAGNITUDE_FIELD_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSEVR1Q_PORT_3_MAINLINE_NCE_GALOIS_FIELD = 32 ; static const uint8_t P9N2_MCBIST_MBSEVR1Q_PORT_3_MAINLINE_NCE_GALOIS_FIELD_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSEVR1Q_PORT_3_MAINLINE_NCE_MAGNITUDE_FIELD = 40 ; static const uint8_t P9N2_MCBIST_MBSEVR1Q_PORT_3_MAINLINE_NCE_MAGNITUDE_FIELD_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSEVR1Q_PORT_3_MAINLINE_TCE_GALOIS_FIELD = 48 ; static const uint8_t P9N2_MCBIST_MBSEVR1Q_PORT_3_MAINLINE_TCE_GALOIS_FIELD_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSEVR1Q_PORT_3_MAINLINE_TCE_MAGNITUDE_FIELD = 56 ; static const uint8_t P9N2_MCBIST_MBSEVR1Q_PORT_3_MAINLINE_TCE_MAGNITUDE_FIELD_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSMODESQ_CFG_DDR4E_BLIND_STEER_MODE = 0 ; static const uint8_t P9N2_MCBIST_MBSMODESQ_CFG_MCB_NIB_CNT_PORT_AGNOSTIC_MASK_DIS = 1 ; static const uint8_t P9N2_MCBIST_MBSMODESQ_CFG_MCB_NIB_CNT_PORT_AGNOSTIC_MASK_DIS_LEN = 4 ; static const uint8_t P9N2_MCBIST_MBSMODESQ_RESERVE_5_15 = 5 ; static const uint8_t P9N2_MCBIST_MBSMODESQ_RESERVE_5_15_LEN = 11 ; static const uint8_t P9N2_MCBIST_MBSMSECQ_MCE_SYMBOL0_COUNT = 0 ; static const uint8_t P9N2_MCBIST_MBSMSECQ_MCE_SYMBOL0_COUNT_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSMSECQ_MCE_SYMBOL1_COUNT = 8 ; static const uint8_t P9N2_MCBIST_MBSMSECQ_MCE_SYMBOL1_COUNT_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSMSECQ_MCE_SYMBOL2_COUNT = 16 ; static const uint8_t P9N2_MCBIST_MBSMSECQ_MCE_SYMBOL2_COUNT_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSMSECQ_MCE_SYMBOL3_COUNT = 24 ; static const uint8_t P9N2_MCBIST_MBSMSECQ_MCE_SYMBOL3_COUNT_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_00 = 0 ; static const uint8_t P9N2_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_00_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_01 = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_01_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_02 = 16 ; static const uint8_t P9N2_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_02_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_03 = 24 ; static const uint8_t P9N2_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_03_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_04 = 32 ; static const uint8_t P9N2_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_04_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_05 = 40 ; static const uint8_t P9N2_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_05_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_06 = 48 ; static const uint8_t P9N2_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_06_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_07 = 56 ; static const uint8_t P9N2_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_07_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_08 = 0 ; static const uint8_t P9N2_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_08_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_09 = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_09_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_10 = 16 ; static const uint8_t P9N2_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_10_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_11 = 24 ; static const uint8_t P9N2_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_11_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_12 = 32 ; static const uint8_t P9N2_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_12_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_13 = 40 ; static const uint8_t P9N2_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_13_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_14 = 48 ; static const uint8_t P9N2_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_14_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_15 = 56 ; static const uint8_t P9N2_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_15_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_16 = 0 ; static const uint8_t P9N2_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_16_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_17 = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_17_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_18 = 16 ; static const uint8_t P9N2_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_18_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_19 = 24 ; static const uint8_t P9N2_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_19_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_20 = 32 ; static const uint8_t P9N2_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_20_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_21 = 40 ; static const uint8_t P9N2_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_21_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_22 = 48 ; static const uint8_t P9N2_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_22_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_23 = 56 ; static const uint8_t P9N2_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_23_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_24 = 0 ; static const uint8_t P9N2_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_24_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_25 = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_25_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_26 = 16 ; static const uint8_t P9N2_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_26_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_27 = 24 ; static const uint8_t P9N2_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_27_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_28 = 32 ; static const uint8_t P9N2_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_28_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_29 = 40 ; static const uint8_t P9N2_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_29_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_30 = 48 ; static const uint8_t P9N2_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_30_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_31 = 56 ; static const uint8_t P9N2_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_31_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_32 = 0 ; static const uint8_t P9N2_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_32_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_33 = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_33_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_34 = 16 ; static const uint8_t P9N2_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_34_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_35 = 24 ; static const uint8_t P9N2_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_35_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_36 = 32 ; static const uint8_t P9N2_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_36_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_37 = 40 ; static const uint8_t P9N2_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_37_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_38 = 48 ; static const uint8_t P9N2_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_38_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_39 = 56 ; static const uint8_t P9N2_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_39_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_40 = 0 ; static const uint8_t P9N2_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_40_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_41 = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_41_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_42 = 16 ; static const uint8_t P9N2_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_42_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_43 = 24 ; static const uint8_t P9N2_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_43_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_44 = 32 ; static const uint8_t P9N2_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_44_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_45 = 40 ; static const uint8_t P9N2_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_45_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_46 = 48 ; static const uint8_t P9N2_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_46_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_47 = 56 ; static const uint8_t P9N2_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_47_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_48 = 0 ; static const uint8_t P9N2_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_48_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_49 = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_49_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_50 = 16 ; static const uint8_t P9N2_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_50_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_51 = 24 ; static const uint8_t P9N2_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_51_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_52 = 32 ; static const uint8_t P9N2_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_52_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_53 = 40 ; static const uint8_t P9N2_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_53_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_54 = 48 ; static const uint8_t P9N2_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_54_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_55 = 56 ; static const uint8_t P9N2_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_55_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_56 = 0 ; static const uint8_t P9N2_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_56_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_57 = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_57_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_58 = 16 ; static const uint8_t P9N2_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_58_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_59 = 24 ; static const uint8_t P9N2_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_59_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_60 = 32 ; static const uint8_t P9N2_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_60_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_61 = 40 ; static const uint8_t P9N2_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_61_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_62 = 48 ; static const uint8_t P9N2_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_62_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_63 = 56 ; static const uint8_t P9N2_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_63_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_64 = 0 ; static const uint8_t P9N2_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_64_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_65 = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_65_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_66 = 16 ; static const uint8_t P9N2_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_66_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_67 = 24 ; static const uint8_t P9N2_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_67_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_68 = 32 ; static const uint8_t P9N2_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_68_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_69 = 40 ; static const uint8_t P9N2_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_69_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_70 = 48 ; static const uint8_t P9N2_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_70_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_71 = 56 ; static const uint8_t P9N2_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_71_LEN = 8 ; static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_INT = 0 ; static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_INT_LEN = 4 ; static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_SOFT = 4 ; static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_SOFT_LEN = 4 ; static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_HARD = 8 ; static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_HARD_LEN = 4 ; static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_THRESH_MAG_RCE = 12 ; static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_THRESH_MAG_RCE_LEN = 4 ; static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_THRESH_MAG_ICE = 16 ; static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_THRESH_MAG_ICE_LEN = 4 ; static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_INT = 20 ; static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_INT_LEN = 4 ; static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_SOFT = 24 ; static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_SOFT_LEN = 4 ; static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_HARD = 28 ; static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_HARD_LEN = 4 ; static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_PAUSE_ON_SCE = 32 ; static const uint8_t P9N2_MCBIST_MBSTRQ_RESERVED_33 = 33 ; static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_PAUSE_ON_MPE = 34 ; static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_PAUSE_ON_UE = 35 ; static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_PAUSE_ON_SUE = 36 ; static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_PAUSE_ON_AUE = 37 ; static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_PAUSE_ON_RCD = 38 ; static const uint8_t P9N2_MCBIST_MBSTRQ_RESERVE_39_52 = 39 ; static const uint8_t P9N2_MCBIST_MBSTRQ_RESERVE_39_52_LEN = 14 ; static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_SYMBOL_COUNTER_MODE = 53 ; static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_SYMBOL_COUNTER_MODE_LEN = 2 ; static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_NCE_SOFT_SYMBOL_COUNT_ENABLE = 55 ; static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_NCE_INTER_SYMBOL_COUNT_ENABLE = 56 ; static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_NCE_HARD_SYMBOL_COUNT_ENABLE = 57 ; static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_PAUSE_MCB_ERROR = 58 ; static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_PAUSE_MCB_LOG_FULL = 59 ; static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_MAINT_RCE_WITH_CE = 60 ; static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_MCE_SOFT_SYMBOL_COUNT_ENABLE = 61 ; static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_MCE_INTER_SYMBOL_COUNT_ENABLE = 62 ; static const uint8_t P9N2_MCBIST_MBSTRQ_CFG_MCE_HARD_SYMBOL_COUNT_ENABLE = 63 ; static const uint8_t P9N2_MCBIST_MBUER0Q_PORT_0_MAINLINE_UE_ADDR_TRAP = 0 ; static const uint8_t P9N2_MCBIST_MBUER0Q_PORT_0_MAINLINE_UE_ADDR_TRAP_LEN = 38 ; static const uint8_t P9N2_MCBIST_MBUER0Q_RESERVED_38_39 = 38 ; static const uint8_t P9N2_MCBIST_MBUER0Q_RESERVED_38_39_LEN = 2 ; static const uint8_t P9N2_MCBIST_MBUER1Q_PORT_1_MAINLINE_UE_ADDR_TRAP = 0 ; static const uint8_t P9N2_MCBIST_MBUER1Q_PORT_1_MAINLINE_UE_ADDR_TRAP_LEN = 38 ; static const uint8_t P9N2_MCBIST_MBUER1Q_RESERVED_38_39 = 38 ; static const uint8_t P9N2_MCBIST_MBUER1Q_RESERVED_38_39_LEN = 2 ; static const uint8_t P9N2_MCBIST_MBUER2Q_PORT_2_MAINLINE_UE_ADDR_TRAP = 0 ; static const uint8_t P9N2_MCBIST_MBUER2Q_PORT_2_MAINLINE_UE_ADDR_TRAP_LEN = 38 ; static const uint8_t P9N2_MCBIST_MBUER2Q_RESERVED_38_39 = 38 ; static const uint8_t P9N2_MCBIST_MBUER2Q_RESERVED_38_39_LEN = 2 ; static const uint8_t P9N2_MCBIST_MBUER3Q_PORT_3_MAINLINE_UE_ADDR_TRAP = 0 ; static const uint8_t P9N2_MCBIST_MBUER3Q_PORT_3_MAINLINE_UE_ADDR_TRAP_LEN = 38 ; static const uint8_t P9N2_MCBIST_MBUER3Q_RESERVED_38_39 = 38 ; static const uint8_t P9N2_MCBIST_MBUER3Q_RESERVED_38_39_LEN = 2 ; static const uint8_t P9N2_MCS_PORT02_MCAMOC_ENABLE_CLEAN = 0 ; static const uint8_t P9N2_MCS_PORT02_MCAMOC_FORCE_PF_DROP0 = 1 ; static const uint8_t P9N2_MCS_PORT02_MCAMOC_FORCE_PF_DROP1 = 2 ; static const uint8_t P9N2_MCS_PORT02_MCAMOC_EN_RD_FROM_AMOC = 3 ; static const uint8_t P9N2_MCS_PORT02_MCAMOC_WRTO_AMO_COLLISION_RULES = 4 ; static const uint8_t P9N2_MCS_PORT02_MCAMOC_WRTO_AMO_COLLISION_RULES_LEN = 25 ; static const uint8_t P9N2_MCS_PORT02_MCAMOC_AMO_SIZE_SELECT = 29 ; static const uint8_t P9N2_MCS_PORT02_MCAMOC_AMO_SIZE_SELECT_LEN = 3 ; static const uint8_t P9N2_MCS_PORT13_MCAMOC_ENABLE_CLEAN = 0 ; static const uint8_t P9N2_MCS_PORT13_MCAMOC_FORCE_PF_DROP0 = 1 ; static const uint8_t P9N2_MCS_PORT13_MCAMOC_FORCE_PF_DROP1 = 2 ; static const uint8_t P9N2_MCS_PORT13_MCAMOC_EN_RD_FROM_AMOC = 3 ; static const uint8_t P9N2_MCS_PORT13_MCAMOC_WRTO_AMO_COLLISION_RULES = 4 ; static const uint8_t P9N2_MCS_PORT13_MCAMOC_WRTO_AMO_COLLISION_RULES_LEN = 25 ; static const uint8_t P9N2_MCS_PORT13_MCAMOC_AMO_SIZE_SELECT = 29 ; static const uint8_t P9N2_MCS_PORT13_MCAMOC_AMO_SIZE_SELECT_LEN = 3 ; static const uint8_t P9N2_MCBIST_MCBACQ_CFG_ADDRESS_COUNTER = 0 ; static const uint8_t P9N2_MCBIST_MCBACQ_CFG_ADDRESS_COUNTER_LEN = 38 ; static const uint8_t P9N2_MCBIST_MCBAGRAQ_CFG_FIXED_WIDTH = 0 ; static const uint8_t P9N2_MCBIST_MCBAGRAQ_CFG_FIXED_WIDTH_LEN = 6 ; static const uint8_t P9N2_MCBIST_MCBAGRAQ_CFG_ADDR_COUNTER_MODE = 6 ; static const uint8_t P9N2_MCBIST_MCBAGRAQ_CFG_ADDR_COUNTER_MODE_LEN = 4 ; static const uint8_t P9N2_MCBIST_MCBAGRAQ_CFG_MAINT_ADDR_MODE_EN = 10 ; static const uint8_t P9N2_MCBIST_MCBAGRAQ_CFG_MAINT_BROADCAST_MODE_EN = 11 ; static const uint8_t P9N2_MCBIST_MCBAGRAQ_CFG_MAINT_DETECT_SRANK_BOUNDARIES = 12 ; static const uint8_t P9N2_MCBIST_MCBAGRAQ_RESERVED_13_31 = 13 ; static const uint8_t P9N2_MCBIST_MCBAGRAQ_RESERVED_13_31_LEN = 19 ; static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_CFG_AMAP_DIMM_SELECT = 0 ; static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_CFG_AMAP_DIMM_SELECT_LEN = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_CFG_AMAP_MRANK0 = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_CFG_AMAP_MRANK0_LEN = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_CFG_AMAP_MRANK1 = 12 ; static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_CFG_AMAP_MRANK1_LEN = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_RESERVED_18_23 = 18 ; static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_RESERVED_18_23_LEN = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK0 = 24 ; static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK0_LEN = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK1 = 30 ; static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK1_LEN = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK2 = 36 ; static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK2_LEN = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK2 = 42 ; static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK2_LEN = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK1 = 48 ; static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK1_LEN = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK0 = 54 ; static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK0_LEN = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_RESERVED_60_63 = 60 ; static const uint8_t P9N2_MCBIST_MCBAMR0A0Q_RESERVED_60_63_LEN = 4 ; static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_CFG_AMAP_BANK_GROUP1 = 0 ; static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_CFG_AMAP_BANK_GROUP1_LEN = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_CFG_AMAP_BANK_GROUP0 = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_CFG_AMAP_BANK_GROUP0_LEN = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW17 = 12 ; static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW17_LEN = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW16 = 18 ; static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW16_LEN = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW15 = 24 ; static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW15_LEN = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW14 = 30 ; static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW14_LEN = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW13 = 36 ; static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW13_LEN = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW12 = 42 ; static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW12_LEN = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW11 = 48 ; static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW11_LEN = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW10 = 54 ; static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW10_LEN = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_RESERVED_60_63 = 60 ; static const uint8_t P9N2_MCBIST_MCBAMR1A0Q_RESERVED_60_63_LEN = 4 ; static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW9 = 0 ; static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW9_LEN = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW8 = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW8_LEN = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW7 = 12 ; static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW7_LEN = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW6 = 18 ; static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW6_LEN = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW5 = 24 ; static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW5_LEN = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW4 = 30 ; static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW4_LEN = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW3 = 36 ; static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW3_LEN = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW2 = 42 ; static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW2_LEN = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW1 = 48 ; static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW1_LEN = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW0 = 54 ; static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW0_LEN = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_RESERVED_60_63 = 60 ; static const uint8_t P9N2_MCBIST_MCBAMR2A0Q_RESERVED_60_63_LEN = 4 ; static const uint8_t P9N2_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL9 = 0 ; static const uint8_t P9N2_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL9_LEN = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL8 = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL8_LEN = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL7 = 12 ; static const uint8_t P9N2_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL7_LEN = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL6 = 18 ; static const uint8_t P9N2_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL6_LEN = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL5 = 24 ; static const uint8_t P9N2_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL5_LEN = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL4 = 30 ; static const uint8_t P9N2_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL4_LEN = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL3 = 36 ; static const uint8_t P9N2_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL3_LEN = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL2 = 42 ; static const uint8_t P9N2_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL2_LEN = 6 ; static const uint8_t P9N2_MCBIST_MCBAMR3A0Q_RESERVED_48_63 = 48 ; static const uint8_t P9N2_MCBIST_MCBAMR3A0Q_RESERVED_48_63_LEN = 16 ; static const uint8_t P9N2_MCBIST_MCBCFGQ_BROADCAST_SYNC_EN = 0 ; static const uint8_t P9N2_MCBIST_MCBCFGQ_BROADCAST_SYNC_WAIT = 1 ; static const uint8_t P9N2_MCBIST_MCBCFGQ_BROADCAST_SYNC_WAIT_LEN = 7 ; static const uint8_t P9N2_MCBIST_MCBCFGQ_CFG_CMD_TIMEOUT_MODE = 8 ; static const uint8_t P9N2_MCBIST_MCBCFGQ_CFG_CMD_TIMEOUT_MODE_LEN = 2 ; static const uint8_t P9N2_MCBIST_MCBCFGQ_RESET_KEEPER = 10 ; static const uint8_t P9N2_MCBIST_MCBCFGQ_CFG_CURRENT_ADDR_TRAP_UPDATE_DIS = 11 ; static const uint8_t P9N2_MCBIST_MCBCFGQ_CFG_CCS_RETRY_DIS = 12 ; static const uint8_t P9N2_MCBIST_MCBCFGQ_RESERVED_13_33 = 13 ; static const uint8_t P9N2_MCBIST_MCBCFGQ_RESERVED_13_33_LEN = 21 ; static const uint8_t P9N2_MCBIST_MCBCFGQ_MCBIST_CFG_FORCE_PAUSE_AFTER_RANK = 34 ; static const uint8_t P9N2_MCBIST_MCBCFGQ_CFG_RESET_CNTS_START_OF_RANK = 35 ; static const uint8_t P9N2_MCBIST_MCBCFGQ_CFG_LOG_COUNTS_IN_TRACE = 36 ; static const uint8_t P9N2_MCBIST_MCBCFGQ_SKIP_INVALID_ADDR_DIMM_DIS = 37 ; static const uint8_t P9N2_MCBIST_MCBCFGQ_REFRESH_ONLY_SUBTEST_EN = 38 ; static const uint8_t P9N2_MCBIST_MCBCFGQ_REFRESH_ONLY_SUBTEST_TIMEBASE_SEL = 39 ; static const uint8_t P9N2_MCBIST_MCBCFGQ_REFRESH_ONLY_SUBTEST_TIMEBASE_SEL_LEN = 2 ; static const uint8_t P9N2_MCBIST_MCBCFGQ_RAND_ADDR_ALL_ADDR_MODE_EN = 41 ; static const uint8_t P9N2_MCBIST_MCBCFGQ_MCBIST_CFG_REF_WAIT_TIME = 42 ; static const uint8_t P9N2_MCBIST_MCBCFGQ_MCBIST_CFG_REF_WAIT_TIME_LEN = 14 ; static const uint8_t P9N2_MCBIST_MCBCFGQ_CFG_MCB_LEN64 = 56 ; static const uint8_t P9N2_MCBIST_MCBCFGQ_CFG_PAUSE_ON_ERROR_MODE = 57 ; static const uint8_t P9N2_MCBIST_MCBCFGQ_CFG_PAUSE_ON_ERROR_MODE_LEN = 2 ; static const uint8_t P9N2_MCBIST_MCBCFGQ_MCBIST_CFG_PAUSE_AFTER_CCS_SUBTEST = 59 ; static const uint8_t P9N2_MCBIST_MCBCFGQ_MCBIST_CFG_FORCE_PAUSE_AFTER_ADDR = 60 ; static const uint8_t P9N2_MCBIST_MCBCFGQ_MCBIST_CFG_FORCE_PAUSE_AFTER_SUBTEST = 61 ; static const uint8_t P9N2_MCBIST_MCBCFGQ_CFG_ENABLE_SPEC_ATTN = 62 ; static const uint8_t P9N2_MCBIST_MCBCFGQ_CFG_ENABLE_HOST_ATTN = 63 ; static const uint8_t P9N2_MCA_MCBCM_MCBIST_HALF_COMPARE_MASK = 0 ; static const uint8_t P9N2_MCA_MCBCM_MCBIST_HALF_COMPARE_MASK_LEN = 40 ; static const uint8_t P9N2_MCA_MCBCM_MCBIST_MASK_COVERAGE_SELECTOR = 40 ; static const uint8_t P9N2_MCA_MCBCM_MCBIST_TRAP_NONSTOP = 41 ; static const uint8_t P9N2_MCA_MCBCM_MCBIST_TRAP_CE_ENABLE = 42 ; static const uint8_t P9N2_MCA_MCBCM_MCBIST_TRAP_MPE_ENABLE = 43 ; static const uint8_t P9N2_MCA_MCBCM_MCBIST_TRAP_UE_ENABLE = 44 ; static const uint8_t P9N2_MCBIST_MCBDRCRQ_CFG_DATA_ROT = 0 ; static const uint8_t P9N2_MCBIST_MCBDRCRQ_CFG_DATA_ROT_LEN = 4 ; static const uint8_t P9N2_MCBIST_MCBDRCRQ_CFG_DATA_ROT_SEED = 4 ; static const uint8_t P9N2_MCBIST_MCBDRCRQ_CFG_DATA_ROT_SEED_LEN = 16 ; static const uint8_t P9N2_MCBIST_MCBDRCRQ_RESERVED_20 = 20 ; static const uint8_t P9N2_MCBIST_MCBDRCRQ_CFG_DATA_SEED_MODE = 21 ; static const uint8_t P9N2_MCBIST_MCBDRCRQ_CFG_DATA_SEED_MODE_LEN = 2 ; static const uint8_t P9N2_MCBIST_MCBDRCRQ_RESERVED_23_63 = 23 ; static const uint8_t P9N2_MCBIST_MCBDRCRQ_RESERVED_23_63_LEN = 41 ; static const uint8_t P9N2_MCBIST_MCBDRSRQ_CFG_DATA_ROT_SEED = 0 ; static const uint8_t P9N2_MCBIST_MCBDRSRQ_CFG_DATA_ROT_SEED_LEN = 64 ; static const uint8_t P9N2_MCBIST_MCBEA0Q_CFG_END_ADDR_0 = 0 ; static const uint8_t P9N2_MCBIST_MCBEA0Q_CFG_END_ADDR_0_LEN = 38 ; static const uint8_t P9N2_MCBIST_MCBEA1Q_CFG_END_ADDR_1 = 0 ; static const uint8_t P9N2_MCBIST_MCBEA1Q_CFG_END_ADDR_1_LEN = 38 ; static const uint8_t P9N2_MCBIST_MCBEA2Q_CFG_END_ADDR_2 = 0 ; static const uint8_t P9N2_MCBIST_MCBEA2Q_CFG_END_ADDR_2_LEN = 38 ; static const uint8_t P9N2_MCBIST_MCBEA3Q_CFG_END_ADDR_3 = 0 ; static const uint8_t P9N2_MCBIST_MCBEA3Q_CFG_END_ADDR_3_LEN = 38 ; static const uint8_t P9N2_MCBIST_MCBFD0Q_CFG_FIXED_SEED = 0 ; static const uint8_t P9N2_MCBIST_MCBFD0Q_CFG_FIXED_SEED_LEN = 64 ; static const uint8_t P9N2_MCBIST_MCBFD1Q_CFG_FIXED_SEED = 0 ; static const uint8_t P9N2_MCBIST_MCBFD1Q_CFG_FIXED_SEED_LEN = 64 ; static const uint8_t P9N2_MCBIST_MCBFD2Q_CFG_FIXED_SEED = 0 ; static const uint8_t P9N2_MCBIST_MCBFD2Q_CFG_FIXED_SEED_LEN = 64 ; static const uint8_t P9N2_MCBIST_MCBFD3Q_CFG_FIXED_SEED = 0 ; static const uint8_t P9N2_MCBIST_MCBFD3Q_CFG_FIXED_SEED_LEN = 64 ; static const uint8_t P9N2_MCBIST_MCBFD4Q_CFG_FIXED_SEED = 0 ; static const uint8_t P9N2_MCBIST_MCBFD4Q_CFG_FIXED_SEED_LEN = 64 ; static const uint8_t P9N2_MCBIST_MCBFD5Q_CFG_FIXED_SEED = 0 ; static const uint8_t P9N2_MCBIST_MCBFD5Q_CFG_FIXED_SEED_LEN = 64 ; static const uint8_t P9N2_MCBIST_MCBFD6Q_CFG_FIXED_SEED = 0 ; static const uint8_t P9N2_MCBIST_MCBFD6Q_CFG_FIXED_SEED_LEN = 64 ; static const uint8_t P9N2_MCBIST_MCBFD7Q_CFG_FIXED_SEED = 0 ; static const uint8_t P9N2_MCBIST_MCBFD7Q_CFG_FIXED_SEED_LEN = 64 ; static const uint8_t P9N2_MCBIST_MCBFDQ_CFG_FIXED_SEED1 = 0 ; static const uint8_t P9N2_MCBIST_MCBFDQ_CFG_FIXED_SEED1_LEN = 8 ; static const uint8_t P9N2_MCBIST_MCBFDQ_CFG_FIXED_SEED2 = 8 ; static const uint8_t P9N2_MCBIST_MCBFDQ_CFG_FIXED_SEED2_LEN = 8 ; static const uint8_t P9N2_MCBIST_MCBFDQ_CFG_FIXED_SEED3 = 16 ; static const uint8_t P9N2_MCBIST_MCBFDQ_CFG_FIXED_SEED3_LEN = 8 ; static const uint8_t P9N2_MCBIST_MCBFDQ_CFG_FIXED_SEED4 = 24 ; static const uint8_t P9N2_MCBIST_MCBFDQ_CFG_FIXED_SEED4_LEN = 8 ; static const uint8_t P9N2_MCBIST_MCBFDQ_CFG_FIXED_SEED5 = 32 ; static const uint8_t P9N2_MCBIST_MCBFDQ_CFG_FIXED_SEED5_LEN = 8 ; static const uint8_t P9N2_MCBIST_MCBFDQ_CFG_FIXED_SEED6 = 40 ; static const uint8_t P9N2_MCBIST_MCBFDQ_CFG_FIXED_SEED6_LEN = 8 ; static const uint8_t P9N2_MCBIST_MCBFDQ_CFG_FIXED_SEED7 = 48 ; static const uint8_t P9N2_MCBIST_MCBFDQ_CFG_FIXED_SEED7_LEN = 8 ; static const uint8_t P9N2_MCBIST_MCBFDQ_CFG_FIXED_SEED8 = 56 ; static const uint8_t P9N2_MCBIST_MCBFDQ_CFG_FIXED_SEED8_LEN = 8 ; static const uint8_t P9N2_MCBIST_MCBISTFIRACT0_FIR_ACTION0 = 0 ; static const uint8_t P9N2_MCBIST_MCBISTFIRACT0_FIR_ACTION0_LEN = 20 ; static const uint8_t P9N2_MCBIST_MCBISTFIRACT1_FIR_ACTION1 = 0 ; static const uint8_t P9N2_MCBIST_MCBISTFIRACT1_FIR_ACTION1_LEN = 20 ; static const uint8_t P9N2_MCBIST_MCBISTFIRMASK_FIR_MASK = 0 ; static const uint8_t P9N2_MCBIST_MCBISTFIRMASK_FIR_MASK_LEN = 20 ; static const uint8_t P9N2_MCBIST_MCBISTFIRQ_INVALID_MAINT_ADDRESS = 0 ; static const uint8_t P9N2_MCBIST_MCBISTFIRQ_COMMAND_ADDRESS_TIMEOUT = 1 ; static const uint8_t P9N2_MCBIST_MCBISTFIRQ_INTERNAL_FSM_ERROR = 2 ; static const uint8_t P9N2_MCBIST_MCBISTFIRQ_MCBIST_BRODCAST_OUT_OF_SYNC = 3 ; static const uint8_t P9N2_MCBIST_MCBISTFIRQ_MCBIST_DATA_ERROR = 4 ; static const uint8_t P9N2_MCBIST_MCBISTFIRQ_HARD_NCE_ETE_ATTN = 5 ; static const uint8_t P9N2_MCBIST_MCBISTFIRQ_SOFT_NCE_ETE_ATTN = 6 ; static const uint8_t P9N2_MCBIST_MCBISTFIRQ_INT_NCE_ETE_ATTN = 7 ; static const uint8_t P9N2_MCBIST_MCBISTFIRQ_RCE_ETE_ATTN = 8 ; static const uint8_t P9N2_MCBIST_MCBISTFIRQ_ICE_ETE_ATTN = 9 ; static const uint8_t P9N2_MCBIST_MCBISTFIRQ_MCBIST_PROGRAM_COMPLETE = 10 ; static const uint8_t P9N2_MCBIST_MCBISTFIRQ_MCBIST_CCS_SUBTEST_DONE = 11 ; static const uint8_t P9N2_MCBIST_MCBISTFIRQ_WAT_DEBUG_ATTN = 12 ; static const uint8_t P9N2_MCBIST_MCBISTFIRQ_SCOM_RECOVERABLE_REG_PE = 13 ; static const uint8_t P9N2_MCBIST_MCBISTFIRQ_SCOM_FATAL_REG_PE = 14 ; static const uint8_t P9N2_MCBIST_MCBISTFIRQ_WAT_DEBUG_REG_PE = 15 ; static const uint8_t P9N2_MCBIST_MCBISTFIRQ_RESERVED_16 = 16 ; static const uint8_t P9N2_MCBIST_MCBISTFIRQ_RESERVED_17 = 17 ; static const uint8_t P9N2_MCBIST_MCBISTFIRQ_INTERNAL_SCOM_ERROR = 18 ; static const uint8_t P9N2_MCBIST_MCBISTFIRQ_INTERNAL_SCOM_ERROR_CLONE = 19 ; static const uint8_t P9N2_MCBIST_MCBISTFIRWOF_INVALID_MAINT_ADDRESS = 0 ; static const uint8_t P9N2_MCBIST_MCBISTFIRWOF_INVALID_MAINT_ADDRESS_LEN = 20 ; static const uint8_t P9N2_MCBIST_MCBLFSRA0Q_CFG_LFSR_MASK_A0 = 0 ; static const uint8_t P9N2_MCBIST_MCBLFSRA0Q_CFG_LFSR_MASK_A0_LEN = 38 ; static const uint8_t P9N2_MCBIST_MCBLFSRA0Q_RESERVED_38_63 = 38 ; static const uint8_t P9N2_MCBIST_MCBLFSRA0Q_RESERVED_38_63_LEN = 26 ; static const uint8_t P9N2_MCBIST_MCBMCATQ_CFG_CURRENT_ADDR_TRAP = 0 ; static const uint8_t P9N2_MCBIST_MCBMCATQ_CFG_CURRENT_ADDR_TRAP_LEN = 38 ; static const uint8_t P9N2_MCBIST_MCBMCATQ_CFG_CURRENT_PORT_TRAP = 38 ; static const uint8_t P9N2_MCBIST_MCBMCATQ_CFG_CURRENT_PORT_TRAP_LEN = 2 ; static const uint8_t P9N2_MCBIST_MCBMCATQ_CFG_CURRENT_DIMM_TRAP = 40 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_OP_TYPE = 0 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_OP_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_1ST_CMD = 4 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_2ND_CMD = 5 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_3RD_CMD = 6 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_REV_MODE = 7 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_RAND_MODE = 8 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_DATA_MODE = 9 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_DATA_MODE_LEN = 3 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ECC_MODE = 12 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_DONE = 13 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_SEL = 14 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_SEL_LEN = 2 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_OP_TYPE = 16 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_OP_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_COMPL_1ST_CMD = 20 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_COMPL_2ND_CMD = 21 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_COMPL_3RD_CMD = 22 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_ADDR_REV_MODE = 23 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_ADDR_RAND_MODE = 24 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_DATA_MODE = 25 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_DATA_MODE_LEN = 3 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_ECC_MODE = 28 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_DONE = 29 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_ADDR_SEL = 30 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_ADDR_SEL_LEN = 2 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_OP_TYPE = 32 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_OP_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_COMPL_1ST_CMD = 36 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_COMPL_2ND_CMD = 37 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_COMPL_3RD_CMD = 38 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_ADDR_REV_MODE = 39 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_ADDR_RAND_MODE = 40 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_DATA_MODE = 41 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_DATA_MODE_LEN = 3 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_ECC_MODE = 44 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_DONE = 45 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_ADDR_SEL = 46 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_ADDR_SEL_LEN = 2 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_OP_TYPE = 48 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_OP_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_COMPL_1ST_CMD = 52 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_COMPL_2ND_CMD = 53 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_COMPL_3RD_CMD = 54 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_ADDR_REV_MODE = 55 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_ADDR_RAND_MODE = 56 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_DATA_MODE = 57 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_DATA_MODE_LEN = 3 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_ECC_MODE = 60 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_DONE = 61 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_ADDR_SEL = 62 ; static const uint8_t P9N2_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_ADDR_SEL_LEN = 2 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_OP_TYPE = 0 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_OP_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_COMPL_1ST_CMD = 4 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_COMPL_2ND_CMD = 5 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_COMPL_3RD_CMD = 6 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_ADDR_REV_MODE = 7 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_ADDR_RAND_MODE = 8 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_DATA_MODE = 9 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_DATA_MODE_LEN = 3 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_ECC_MODE = 12 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_DONE = 13 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_ADDR_SEL = 14 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_ADDR_SEL_LEN = 2 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_OP_TYPE = 16 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_OP_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_COMPL_1ST_CMD = 20 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_COMPL_2ND_CMD = 21 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_COMPL_3RD_CMD = 22 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_ADDR_REV_MODE = 23 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_ADDR_RAND_MODE = 24 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_DATA_MODE = 25 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_DATA_MODE_LEN = 3 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_ECC_MODE = 28 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_DONE = 29 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_ADDR_SEL = 30 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_ADDR_SEL_LEN = 2 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_OP_TYPE = 32 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_OP_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_COMPL_1ST_CMD = 36 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_COMPL_2ND_CMD = 37 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_COMPL_3RD_CMD = 38 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_ADDR_REV_MODE = 39 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_ADDR_RAND_MODE = 40 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_DATA_MODE = 41 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_DATA_MODE_LEN = 3 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_ECC_MODE = 44 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_DONE = 45 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_ADDR_SEL = 46 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_ADDR_SEL_LEN = 2 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_OP_TYPE = 48 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_OP_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_COMPL_1ST_CMD = 52 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_COMPL_2ND_CMD = 53 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_COMPL_3RD_CMD = 54 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_ADDR_REV_MODE = 55 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_ADDR_RAND_MODE = 56 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_DATA_MODE = 57 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_DATA_MODE_LEN = 3 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_ECC_MODE = 60 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_DONE = 61 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_ADDR_SEL = 62 ; static const uint8_t P9N2_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_ADDR_SEL_LEN = 2 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_OP_TYPE = 0 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_OP_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_COMPL_1ST_CMD = 4 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_COMPL_2ND_CMD = 5 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_COMPL_3RD_CMD = 6 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_ADDR_REV_MODE = 7 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_ADDR_RAND_MODE = 8 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_DATA_MODE = 9 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_DATA_MODE_LEN = 3 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_ECC_MODE = 12 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_DONE = 13 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_ADDR_SEL = 14 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_ADDR_SEL_LEN = 2 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_OP_TYPE = 16 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_OP_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_COMPL_1ST_CMD = 20 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_COMPL_2ND_CMD = 21 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_COMPL_3RD_CMD = 22 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_ADDR_REV_MODE = 23 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_ADDR_RAND_MODE = 24 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_DATA_MODE = 25 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_DATA_MODE_LEN = 3 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_ECC_MODE = 28 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_DONE = 29 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_ADDR_SEL = 30 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_ADDR_SEL_LEN = 2 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_OP_TYPE = 32 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_OP_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_COMPL_1ST_CMD = 36 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_COMPL_2ND_CMD = 37 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_COMPL_3RD_CMD = 38 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_ADDR_REV_MODE = 39 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_ADDR_RAND_MODE = 40 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_DATA_MODE = 41 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_DATA_MODE_LEN = 3 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_ECC_MODE = 44 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_DONE = 45 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_ADDR_SEL = 46 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_ADDR_SEL_LEN = 2 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_OP_TYPE = 48 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_OP_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_COMPL_1ST_CMD = 52 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_COMPL_2ND_CMD = 53 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_COMPL_3RD_CMD = 54 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_ADDR_REV_MODE = 55 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_ADDR_RAND_MODE = 56 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_DATA_MODE = 57 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_DATA_MODE_LEN = 3 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_ECC_MODE = 60 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_DONE = 61 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_ADDR_SEL = 62 ; static const uint8_t P9N2_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_ADDR_SEL_LEN = 2 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_OP_TYPE = 0 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_OP_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_COMPL_1ST_CMD = 4 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_COMPL_2ND_CMD = 5 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_COMPL_3RD_CMD = 6 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_ADDR_REV_MODE = 7 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_ADDR_RAND_MODE = 8 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_DATA_MODE = 9 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_DATA_MODE_LEN = 3 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_ECC_MODE = 12 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_DONE = 13 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_ADDR_SEL = 14 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_ADDR_SEL_LEN = 2 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_OP_TYPE = 16 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_OP_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_COMPL_1ST_CMD = 20 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_COMPL_2ND_CMD = 21 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_COMPL_3RD_CMD = 22 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_ADDR_REV_MODE = 23 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_ADDR_RAND_MODE = 24 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_DATA_MODE = 25 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_DATA_MODE_LEN = 3 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_ECC_MODE = 28 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_DONE = 29 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_ADDR_SEL = 30 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_ADDR_SEL_LEN = 2 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_OP_TYPE = 32 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_OP_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_COMPL_1ST_CMD = 36 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_COMPL_2ND_CMD = 37 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_COMPL_3RD_CMD = 38 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_ADDR_REV_MODE = 39 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_ADDR_RAND_MODE = 40 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_DATA_MODE = 41 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_DATA_MODE_LEN = 3 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_ECC_MODE = 44 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_DONE = 45 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_ADDR_SEL = 46 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_ADDR_SEL_LEN = 2 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_OP_TYPE = 48 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_OP_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_COMPL_1ST_CMD = 52 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_COMPL_2ND_CMD = 53 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_COMPL_3RD_CMD = 54 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_ADDR_REV_MODE = 55 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_ADDR_RAND_MODE = 56 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_DATA_MODE = 57 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_DATA_MODE_LEN = 3 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_ECC_MODE = 60 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_DONE = 61 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_ADDR_SEL = 62 ; static const uint8_t P9N2_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_ADDR_SEL_LEN = 2 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_OP_TYPE = 0 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_OP_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_COMPL_1ST_CMD = 4 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_COMPL_2ND_CMD = 5 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_COMPL_3RD_CMD = 6 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_ADDR_REV_MODE = 7 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_ADDR_RAND_MODE = 8 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_DATA_MODE = 9 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_DATA_MODE_LEN = 3 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_ECC_MODE = 12 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_DONE = 13 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_ADDR_SEL = 14 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_ADDR_SEL_LEN = 2 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_OP_TYPE = 16 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_OP_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_COMPL_1ST_CMD = 20 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_COMPL_2ND_CMD = 21 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_COMPL_3RD_CMD = 22 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_ADDR_REV_MODE = 23 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_ADDR_RAND_MODE = 24 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_DATA_MODE = 25 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_DATA_MODE_LEN = 3 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_ECC_MODE = 28 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_DONE = 29 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_ADDR_SEL = 30 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_ADDR_SEL_LEN = 2 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_OP_TYPE = 32 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_OP_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_COMPL_1ST_CMD = 36 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_COMPL_2ND_CMD = 37 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_COMPL_3RD_CMD = 38 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_ADDR_REV_MODE = 39 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_ADDR_RAND_MODE = 40 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_DATA_MODE = 41 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_DATA_MODE_LEN = 3 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_ECC_MODE = 44 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_DONE = 45 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_ADDR_SEL = 46 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_ADDR_SEL_LEN = 2 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_OP_TYPE = 48 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_OP_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_COMPL_1ST_CMD = 52 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_COMPL_2ND_CMD = 53 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_COMPL_3RD_CMD = 54 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_ADDR_REV_MODE = 55 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_ADDR_RAND_MODE = 56 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_DATA_MODE = 57 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_DATA_MODE_LEN = 3 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_ECC_MODE = 60 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_DONE = 61 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_ADDR_SEL = 62 ; static const uint8_t P9N2_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_ADDR_SEL_LEN = 2 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_OP_TYPE = 0 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_OP_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_COMPL_1ST_CMD = 4 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_COMPL_2ND_CMD = 5 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_COMPL_3RD_CMD = 6 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_ADDR_REV_MODE = 7 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_ADDR_RAND_MODE = 8 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_DATA_MODE = 9 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_DATA_MODE_LEN = 3 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_ECC_MODE = 12 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_DONE = 13 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_ADDR_SEL = 14 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_ADDR_SEL_LEN = 2 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_OP_TYPE = 16 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_OP_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_COMPL_1ST_CMD = 20 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_COMPL_2ND_CMD = 21 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_COMPL_3RD_CMD = 22 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_ADDR_REV_MODE = 23 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_ADDR_RAND_MODE = 24 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_DATA_MODE = 25 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_DATA_MODE_LEN = 3 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_ECC_MODE = 28 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_DONE = 29 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_ADDR_SEL = 30 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_ADDR_SEL_LEN = 2 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_OP_TYPE = 32 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_OP_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_COMPL_1ST_CMD = 36 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_COMPL_2ND_CMD = 37 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_COMPL_3RD_CMD = 38 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_ADDR_REV_MODE = 39 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_ADDR_RAND_MODE = 40 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_DATA_MODE = 41 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_DATA_MODE_LEN = 3 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_ECC_MODE = 44 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_DONE = 45 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_ADDR_SEL = 46 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_ADDR_SEL_LEN = 2 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_OP_TYPE = 48 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_OP_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_COMPL_1ST_CMD = 52 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_COMPL_2ND_CMD = 53 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_COMPL_3RD_CMD = 54 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_ADDR_REV_MODE = 55 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_ADDR_RAND_MODE = 56 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_DATA_MODE = 57 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_DATA_MODE_LEN = 3 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_ECC_MODE = 60 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_DONE = 61 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_ADDR_SEL = 62 ; static const uint8_t P9N2_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_ADDR_SEL_LEN = 2 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_OP_TYPE = 0 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_OP_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_COMPL_1ST_CMD = 4 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_COMPL_2ND_CMD = 5 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_COMPL_3RD_CMD = 6 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_ADDR_REV_MODE = 7 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_ADDR_RAND_MODE = 8 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_DATA_MODE = 9 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_DATA_MODE_LEN = 3 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_ECC_MODE = 12 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_DONE = 13 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_ADDR_SEL = 14 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_ADDR_SEL_LEN = 2 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_OP_TYPE = 16 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_OP_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_COMPL_1ST_CMD = 20 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_COMPL_2ND_CMD = 21 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_COMPL_3RD_CMD = 22 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_ADDR_REV_MODE = 23 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_ADDR_RAND_MODE = 24 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_DATA_MODE = 25 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_DATA_MODE_LEN = 3 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_ECC_MODE = 28 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_DONE = 29 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_ADDR_SEL = 30 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_ADDR_SEL_LEN = 2 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_OP_TYPE = 32 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_OP_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_COMPL_1ST_CMD = 36 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_COMPL_2ND_CMD = 37 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_COMPL_3RD_CMD = 38 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_ADDR_REV_MODE = 39 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_ADDR_RAND_MODE = 40 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_DATA_MODE = 41 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_DATA_MODE_LEN = 3 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_ECC_MODE = 44 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_DONE = 45 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_ADDR_SEL = 46 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_ADDR_SEL_LEN = 2 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_OP_TYPE = 48 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_OP_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_COMPL_1ST_CMD = 52 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_COMPL_2ND_CMD = 53 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_COMPL_3RD_CMD = 54 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_ADDR_REV_MODE = 55 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_ADDR_RAND_MODE = 56 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_DATA_MODE = 57 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_DATA_MODE_LEN = 3 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_ECC_MODE = 60 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_DONE = 61 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_ADDR_SEL = 62 ; static const uint8_t P9N2_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_ADDR_SEL_LEN = 2 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_OP_TYPE = 0 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_OP_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_COMPL_1ST_CMD = 4 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_COMPL_2ND_CMD = 5 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_COMPL_3RD_CMD = 6 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_ADDR_REV_MODE = 7 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_ADDR_RAND_MODE = 8 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_DATA_MODE = 9 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_DATA_MODE_LEN = 3 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_ECC_MODE = 12 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_DONE = 13 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_ADDR_SEL = 14 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_ADDR_SEL_LEN = 2 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_OP_TYPE = 16 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_OP_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_COMPL_1ST_CMD = 20 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_COMPL_2ND_CMD = 21 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_COMPL_3RD_CMD = 22 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_ADDR_REV_MODE = 23 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_ADDR_RAND_MODE = 24 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_DATA_MODE = 25 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_DATA_MODE_LEN = 3 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_ECC_MODE = 28 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_DONE = 29 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_ADDR_SEL = 30 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_ADDR_SEL_LEN = 2 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_OP_TYPE = 32 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_OP_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_COMPL_1ST_CMD = 36 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_COMPL_2ND_CMD = 37 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_COMPL_3RD_CMD = 38 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_ADDR_REV_MODE = 39 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_ADDR_RAND_MODE = 40 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_DATA_MODE = 41 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_DATA_MODE_LEN = 3 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_ECC_MODE = 44 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_DONE = 45 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_ADDR_SEL = 46 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_ADDR_SEL_LEN = 2 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_OP_TYPE = 48 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_OP_TYPE_LEN = 4 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_COMPL_1ST_CMD = 52 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_COMPL_2ND_CMD = 53 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_COMPL_3RD_CMD = 54 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_ADDR_REV_MODE = 55 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_ADDR_RAND_MODE = 56 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_DATA_MODE = 57 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_DATA_MODE_LEN = 3 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_ECC_MODE = 60 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_DONE = 61 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_ADDR_SEL = 62 ; static const uint8_t P9N2_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_ADDR_SEL_LEN = 2 ; static const uint8_t P9N2_MCBIST_MCBPARMQ_CFG_MIN_CMD_GAP = 0 ; static const uint8_t P9N2_MCBIST_MCBPARMQ_CFG_MIN_CMD_GAP_LEN = 12 ; static const uint8_t P9N2_MCBIST_MCBPARMQ_CFG_MIN_GAP_TIMEBASE = 12 ; static const uint8_t P9N2_MCBIST_MCBPARMQ_CFG_MIN_CMD_GAP_BLIND_STEER = 13 ; static const uint8_t P9N2_MCBIST_MCBPARMQ_CFG_MIN_CMD_GAP_BLIND_STEER_LEN = 12 ; static const uint8_t P9N2_MCBIST_MCBPARMQ_CFG_MIN_GAP_TIMEBASE_BLIND_STEER = 25 ; static const uint8_t P9N2_MCBIST_MCBPARMQ_RESERVED_26_49 = 26 ; static const uint8_t P9N2_MCBIST_MCBPARMQ_RESERVED_26_49_LEN = 24 ; static const uint8_t P9N2_MCBIST_MCBPARMQ_CFG_RANDCMD_WGT = 50 ; static const uint8_t P9N2_MCBIST_MCBPARMQ_CFG_RANDCMD_WGT_LEN = 3 ; static const uint8_t P9N2_MCBIST_MCBPARMQ_RESERVED_53_58 = 53 ; static const uint8_t P9N2_MCBIST_MCBPARMQ_RESERVED_53_58_LEN = 6 ; static const uint8_t P9N2_MCBIST_MCBPARMQ_CFG_CLOCK_MONITOR_EN = 59 ; static const uint8_t P9N2_MCBIST_MCBPARMQ_CFG_EN_RANDCMD_GAP = 60 ; static const uint8_t P9N2_MCBIST_MCBPARMQ_CFG_RANDGAP_WGT = 61 ; static const uint8_t P9N2_MCBIST_MCBPARMQ_CFG_RANDGAP_WGT_LEN = 2 ; static const uint8_t P9N2_MCBIST_MCBPARMQ_CFG_BC4_EN = 63 ; static const uint8_t P9N2_MCBIST_MCBRCRQ_RESERVED_0_31 = 0 ; static const uint8_t P9N2_MCBIST_MCBRCRQ_RESERVED_0_31_LEN = 32 ; static const uint8_t P9N2_MCBIST_MCBRCRQ_CFG_RUNTIME_MCBALL = 32 ; static const uint8_t P9N2_MCBIST_MCBRCRQ_CFG_RUNTIME_SUBTEST = 33 ; static const uint8_t P9N2_MCBIST_MCBRCRQ_CFG_RUNTIME_SUBTEST_LEN = 5 ; static const uint8_t P9N2_MCBIST_MCBRCRQ_CFG_RUNTIME_OVERHEAD = 38 ; static const uint8_t P9N2_MCBIST_MCBRCRQ_RESERVED_39 = 39 ; static const uint8_t P9N2_MCBIST_MCBRDS0Q_DGEN_RNDD_SEED0 = 0 ; static const uint8_t P9N2_MCBIST_MCBRDS0Q_DGEN_RNDD_SEED0_LEN = 24 ; static const uint8_t P9N2_MCBIST_MCBRDS0Q_DGEN_RNDD_SEED1 = 24 ; static const uint8_t P9N2_MCBIST_MCBRDS0Q_DGEN_RNDD_SEED1_LEN = 24 ; static const uint8_t P9N2_MCBIST_MCBRDS1Q_DGEN_RNDD_SEED2 = 0 ; static const uint8_t P9N2_MCBIST_MCBRDS1Q_DGEN_RNDD_SEED2_LEN = 24 ; static const uint8_t P9N2_MCBIST_MCBRDS1Q_DGEN_RNDD_DATA_MAPPING = 24 ; static const uint8_t P9N2_MCBIST_MCBRDS1Q_DGEN_RNDD_DATA_MAPPING_LEN = 40 ; static const uint8_t P9N2_MCBIST_MCBSA0Q_CFG_START_ADDR_0 = 0 ; static const uint8_t P9N2_MCBIST_MCBSA0Q_CFG_START_ADDR_0_LEN = 38 ; static const uint8_t P9N2_MCBIST_MCBSA1Q_CFG_START_ADDR_1 = 0 ; static const uint8_t P9N2_MCBIST_MCBSA1Q_CFG_START_ADDR_1_LEN = 38 ; static const uint8_t P9N2_MCBIST_MCBSA2Q_CFG_START_ADDR_2 = 0 ; static const uint8_t P9N2_MCBIST_MCBSA2Q_CFG_START_ADDR_2_LEN = 38 ; static const uint8_t P9N2_MCBIST_MCBSA3Q_CFG_START_ADDR_3 = 0 ; static const uint8_t P9N2_MCBIST_MCBSA3Q_CFG_START_ADDR_3_LEN = 38 ; static const uint8_t P9N2_MCBIST_MCBSTATQ_MCBIST_LOGGED_ERROR_ON_PORT_INDICATOR = 0 ; static const uint8_t P9N2_MCBIST_MCBSTATQ_MCBIST_LOGGED_ERROR_ON_PORT_INDICATOR_LEN = 4 ; static const uint8_t P9N2_MCBIST_MCBSTATQ_MCBIST_SUBTEST_NUM_INDICATOR = 4 ; static const uint8_t P9N2_MCBIST_MCBSTATQ_MCBIST_SUBTEST_NUM_INDICATOR_LEN = 5 ; static const uint8_t P9N2_MCBIST_MCBSTATQ_RESERVED_9_15 = 9 ; static const uint8_t P9N2_MCBIST_MCBSTATQ_RESERVED_9_15_LEN = 7 ; static const uint8_t P9N2_MCS_PORT02_MCBUSYQ_ENABLE_BUSY_COUNTERS = 0 ; static const uint8_t P9N2_MCS_PORT02_MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT = 1 ; static const uint8_t P9N2_MCS_PORT02_MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT_LEN = 3 ; static const uint8_t P9N2_MCS_PORT02_MCBUSYQ_BUSY_COUNTER_THRESHOLD0 = 4 ; static const uint8_t P9N2_MCS_PORT02_MCBUSYQ_BUSY_COUNTER_THRESHOLD0_LEN = 10 ; static const uint8_t P9N2_MCS_PORT02_MCBUSYQ_BUSY_COUNTER_THRESHOLD1 = 14 ; static const uint8_t P9N2_MCS_PORT02_MCBUSYQ_BUSY_COUNTER_THRESHOLD1_LEN = 10 ; static const uint8_t P9N2_MCS_PORT02_MCBUSYQ_BUSY_COUNTER_THRESHOLD2 = 24 ; static const uint8_t P9N2_MCS_PORT02_MCBUSYQ_BUSY_COUNTER_THRESHOLD2_LEN = 10 ; static const uint8_t P9N2_MCS_PORT02_MCBUSYQ_ENABLE_AGGRESSIVE_BUSY = 34 ; static const uint8_t P9N2_MCS_PORT02_MCBUSYQ_RSVD_35_43 = 35 ; static const uint8_t P9N2_MCS_PORT02_MCBUSYQ_RSVD_35_43_LEN = 9 ; static const uint8_t P9N2_MCS_PORT13_MCBUSYQ_ENABLE_BUSY_COUNTERS = 0 ; static const uint8_t P9N2_MCS_PORT13_MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT = 1 ; static const uint8_t P9N2_MCS_PORT13_MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT_LEN = 3 ; static const uint8_t P9N2_MCS_PORT13_MCBUSYQ_BUSY_COUNTER_THRESHOLD0 = 4 ; static const uint8_t P9N2_MCS_PORT13_MCBUSYQ_BUSY_COUNTER_THRESHOLD0_LEN = 10 ; static const uint8_t P9N2_MCS_PORT13_MCBUSYQ_BUSY_COUNTER_THRESHOLD1 = 14 ; static const uint8_t P9N2_MCS_PORT13_MCBUSYQ_BUSY_COUNTER_THRESHOLD1_LEN = 10 ; static const uint8_t P9N2_MCS_PORT13_MCBUSYQ_BUSY_COUNTER_THRESHOLD2 = 24 ; static const uint8_t P9N2_MCS_PORT13_MCBUSYQ_BUSY_COUNTER_THRESHOLD2_LEN = 10 ; static const uint8_t P9N2_MCS_PORT13_MCBUSYQ_ENABLE_AGGRESSIVE_BUSY = 34 ; static const uint8_t P9N2_MCS_PORT13_MCBUSYQ_RSVD_35_43 = 35 ; static const uint8_t P9N2_MCS_PORT13_MCBUSYQ_RSVD_35_43_LEN = 9 ; static const uint8_t P9N2_MCBIST_MCB_CNTLQ_START = 0 ; static const uint8_t P9N2_MCBIST_MCB_CNTLQ_STOP = 1 ; static const uint8_t P9N2_MCBIST_MCB_CNTLQ_MCBCNTL_PORT_SEL = 2 ; static const uint8_t P9N2_MCBIST_MCB_CNTLQ_MCBCNTL_PORT_SEL_LEN = 4 ; static const uint8_t P9N2_MCBIST_MCB_CNTLQ_RESET_TRAP_CNFG = 6 ; static const uint8_t P9N2_MCBIST_MCB_CNTLQ_RESET_ERROR_LOGS = 7 ; static const uint8_t P9N2_MCBIST_MCB_CNTLQ_RESUME_FROM_PAUSE = 8 ; static const uint8_t P9N2_MCBIST_MCB_CNTLSTATQ_IP = 0 ; static const uint8_t P9N2_MCBIST_MCB_CNTLSTATQ_DONE = 1 ; static const uint8_t P9N2_MCBIST_MCB_CNTLSTATQ_FAIL = 2 ; static const uint8_t P9N2_MCS_MCDBG0_DEBUG_BUS_0_63 = 0 ; static const uint8_t P9N2_MCS_MCDBG0_DEBUG_BUS_0_63_LEN = 64 ; static const uint8_t P9N2_MCS_MCDBG1_DEBUG_BUS_64_87 = 0 ; static const uint8_t P9N2_MCS_MCDBG1_DEBUG_BUS_64_87_LEN = 24 ; static const uint8_t P9N2_MCS_MCDBG1_WRQ0_EMPTY = 24 ; static const uint8_t P9N2_MCS_MCDBG1_WRQ1_EMPTY = 25 ; static const uint8_t P9N2_MCS_PORT02_MCEBUSCL_BYTE0_SEL = 0 ; static const uint8_t P9N2_MCS_PORT02_MCEBUSCL_BYTE0_SEL_LEN = 2 ; static const uint8_t P9N2_MCS_PORT02_MCEBUSCL_BYTE1_SEL = 2 ; static const uint8_t P9N2_MCS_PORT02_MCEBUSCL_BYTE1_SEL_LEN = 2 ; static const uint8_t P9N2_MCS_PORT02_MCEBUSCL_BYTE2_SEL = 4 ; static const uint8_t P9N2_MCS_PORT02_MCEBUSCL_BYTE2_SEL_LEN = 2 ; static const uint8_t P9N2_MCS_PORT02_MCEBUSCL_BYTE3_SEL = 6 ; static const uint8_t P9N2_MCS_PORT02_MCEBUSCL_BYTE3_SEL_LEN = 2 ; static const uint8_t P9N2_MCS_PORT02_MCEBUSCL_LAT_THRESHA = 8 ; static const uint8_t P9N2_MCS_PORT02_MCEBUSCL_LAT_THRESHA_LEN = 8 ; static const uint8_t P9N2_MCS_PORT02_MCEBUSCL_LAT_THRESHB = 16 ; static const uint8_t P9N2_MCS_PORT02_MCEBUSCL_LAT_THRESHB_LEN = 8 ; static const uint8_t P9N2_MCS_PORT02_MCEBUSCL_LAT_THRESHC = 24 ; static const uint8_t P9N2_MCS_PORT02_MCEBUSCL_LAT_THRESHC_LEN = 8 ; static const uint8_t P9N2_MCS_PORT02_MCEBUSCL_SCOM20A_SEL = 32 ; static const uint8_t P9N2_MCS_PORT02_MCEBUSCL_SCOM28A_30A_SEL = 33 ; static const uint8_t P9N2_MCS_PORT13_MCEBUSCL_BYTE0_SEL = 0 ; static const uint8_t P9N2_MCS_PORT13_MCEBUSCL_BYTE0_SEL_LEN = 2 ; static const uint8_t P9N2_MCS_PORT13_MCEBUSCL_BYTE1_SEL = 2 ; static const uint8_t P9N2_MCS_PORT13_MCEBUSCL_BYTE1_SEL_LEN = 2 ; static const uint8_t P9N2_MCS_PORT13_MCEBUSCL_BYTE2_SEL = 4 ; static const uint8_t P9N2_MCS_PORT13_MCEBUSCL_BYTE2_SEL_LEN = 2 ; static const uint8_t P9N2_MCS_PORT13_MCEBUSCL_BYTE3_SEL = 6 ; static const uint8_t P9N2_MCS_PORT13_MCEBUSCL_BYTE3_SEL_LEN = 2 ; static const uint8_t P9N2_MCS_PORT13_MCEBUSCL_LAT_THRESHA = 8 ; static const uint8_t P9N2_MCS_PORT13_MCEBUSCL_LAT_THRESHA_LEN = 8 ; static const uint8_t P9N2_MCS_PORT13_MCEBUSCL_LAT_THRESHB = 16 ; static const uint8_t P9N2_MCS_PORT13_MCEBUSCL_LAT_THRESHB_LEN = 8 ; static const uint8_t P9N2_MCS_PORT13_MCEBUSCL_LAT_THRESHC = 24 ; static const uint8_t P9N2_MCS_PORT13_MCEBUSCL_LAT_THRESHC_LEN = 8 ; static const uint8_t P9N2_MCS_PORT13_MCEBUSCL_SCOM20A_SEL = 32 ; static const uint8_t P9N2_MCS_PORT13_MCEBUSCL_SCOM28A_30A_SEL = 33 ; static const uint8_t P9N2_MCS_PORT13_MCEBUSEN0_EVENT_BUS_SELECTS = 0 ; static const uint8_t P9N2_MCS_PORT13_MCEBUSEN0_EVENT_BUS_SELECTS_LEN = 64 ; static const uint8_t P9N2_MCS_PORT13_MCEBUSEN1_EVENT_BUS_SELECTS = 0 ; static const uint8_t P9N2_MCS_PORT13_MCEBUSEN1_EVENT_BUS_SELECTS_LEN = 64 ; static const uint8_t P9N2_MCS_PORT13_MCEBUSEN2_EVENT_BUS_SELECTS = 0 ; static const uint8_t P9N2_MCS_PORT13_MCEBUSEN2_EVENT_BUS_SELECTS_LEN = 64 ; static const uint8_t P9N2_MCS_PORT13_MCEBUSEN3_EVENT_BUS_EN = 0 ; static const uint8_t P9N2_MCS_PORT13_MCEBUSEN3_EVENT_BUS_EN_LEN = 16 ; static const uint8_t P9N2_MCS_PORT13_MCEBUSEN3_EVENT_BUS_ENABLE = 16 ; static const uint8_t P9N2_MCS_PORT13_MCEBUSEN3_EBUS_16A_SELECT = 17 ; static const uint8_t P9N2_MCS_PORT02_MCEPSQ_JITTER_EPSILON = 0 ; static const uint8_t P9N2_MCS_PORT02_MCEPSQ_JITTER_EPSILON_LEN = 8 ; static const uint8_t P9N2_MCS_PORT02_MCEPSQ_LOCAL_NODE_EPSILON = 8 ; static const uint8_t P9N2_MCS_PORT02_MCEPSQ_LOCAL_NODE_EPSILON_LEN = 8 ; static const uint8_t P9N2_MCS_PORT02_MCEPSQ_NEAR_NODAL_EPSILON = 16 ; static const uint8_t P9N2_MCS_PORT02_MCEPSQ_NEAR_NODAL_EPSILON_LEN = 8 ; static const uint8_t P9N2_MCS_PORT02_MCEPSQ_GROUP_EPSILON = 24 ; static const uint8_t P9N2_MCS_PORT02_MCEPSQ_GROUP_EPSILON_LEN = 8 ; static const uint8_t P9N2_MCS_PORT02_MCEPSQ_REMOTE_NODAL_EPSILON = 32 ; static const uint8_t P9N2_MCS_PORT02_MCEPSQ_REMOTE_NODAL_EPSILON_LEN = 8 ; static const uint8_t P9N2_MCS_PORT02_MCEPSQ_VECTOR_GROUP_EPSILON = 40 ; static const uint8_t P9N2_MCS_PORT02_MCEPSQ_VECTOR_GROUP_EPSILON_LEN = 8 ; static const uint8_t P9N2_MCS_PORT13_MCEPSQ_JITTER_EPSILON = 0 ; static const uint8_t P9N2_MCS_PORT13_MCEPSQ_JITTER_EPSILON_LEN = 8 ; static const uint8_t P9N2_MCS_PORT13_MCEPSQ_LOCAL_NODE_EPSILON = 8 ; static const uint8_t P9N2_MCS_PORT13_MCEPSQ_LOCAL_NODE_EPSILON_LEN = 8 ; static const uint8_t P9N2_MCS_PORT13_MCEPSQ_NEAR_NODAL_EPSILON = 16 ; static const uint8_t P9N2_MCS_PORT13_MCEPSQ_NEAR_NODAL_EPSILON_LEN = 8 ; static const uint8_t P9N2_MCS_PORT13_MCEPSQ_GROUP_EPSILON = 24 ; static const uint8_t P9N2_MCS_PORT13_MCEPSQ_GROUP_EPSILON_LEN = 8 ; static const uint8_t P9N2_MCS_PORT13_MCEPSQ_REMOTE_NODAL_EPSILON = 32 ; static const uint8_t P9N2_MCS_PORT13_MCEPSQ_REMOTE_NODAL_EPSILON_LEN = 8 ; static const uint8_t P9N2_MCS_PORT13_MCEPSQ_VECTOR_GROUP_EPSILON = 40 ; static const uint8_t P9N2_MCS_PORT13_MCEPSQ_VECTOR_GROUP_EPSILON_LEN = 8 ; static const uint8_t P9N2_MCS_MCERPT0_DATA = 0 ; static const uint8_t P9N2_MCS_MCERPT0_DATA_LEN = 63 ; static const uint8_t P9N2_MCS_MCERPT1_DATA = 0 ; static const uint8_t P9N2_MCS_MCERPT1_DATA_LEN = 63 ; static const uint8_t P9N2_MCS_MCERPT2_DATA = 0 ; static const uint8_t P9N2_MCS_MCERPT2_DATA_LEN = 7 ; static const uint8_t P9N2_MCS_PORT02_MCERRINJ_WDF_ERR_INJECT0 = 0 ; static const uint8_t P9N2_MCS_PORT02_MCERRINJ_WDF_ERR_INJECT0_LEN = 4 ; static const uint8_t P9N2_MCS_PORT02_MCERRINJ_READ_ERR_INJECT0 = 4 ; static const uint8_t P9N2_MCS_PORT02_MCERRINJ_READ_ERR_INJECT0_LEN = 4 ; static const uint8_t P9N2_MCS_PORT02_MCERRINJ_WRITE_ERR_INJECT0 = 8 ; static const uint8_t P9N2_MCS_PORT02_MCERRINJ_WRITE_ERR_INJECT0_LEN = 4 ; static const uint8_t P9N2_MCS_PORT02_MCERRINJ_READ_PAR_NOT_SEQ = 12 ; static const uint8_t P9N2_MCS_PORT02_MCERRINJ_RCMD_ERR_INJ = 13 ; static const uint8_t P9N2_MCS_PORT02_MCERRINJ_PF_PROMOTE_ERR_INJ = 14 ; static const uint8_t P9N2_MCS_PORT02_MCERRINJ_RESET_KEEPER = 15 ; static const uint8_t P9N2_MCS_PORT13_MCERRINJ_WDF_ERR_INJECT0 = 0 ; static const uint8_t P9N2_MCS_PORT13_MCERRINJ_WDF_ERR_INJECT0_LEN = 4 ; static const uint8_t P9N2_MCS_PORT13_MCERRINJ_READ_ERR_INJECT0 = 4 ; static const uint8_t P9N2_MCS_PORT13_MCERRINJ_READ_ERR_INJECT0_LEN = 4 ; static const uint8_t P9N2_MCS_PORT13_MCERRINJ_WRITE_ERR_INJECT0 = 8 ; static const uint8_t P9N2_MCS_PORT13_MCERRINJ_WRITE_ERR_INJECT0_LEN = 4 ; static const uint8_t P9N2_MCS_PORT13_MCERRINJ_READ_PAR_NOT_SEQ = 12 ; static const uint8_t P9N2_MCS_PORT13_MCERRINJ_RCMD_ERR_INJ = 13 ; static const uint8_t P9N2_MCS_PORT13_MCERRINJ_PF_PROMOTE_ERR_INJ = 14 ; static const uint8_t P9N2_MCS_PORT13_MCERRINJ_RESET_KEEPER = 15 ; static const uint8_t P9N2_MCS_MCFGP_VALID = 0 ; static const uint8_t P9N2_MCS_MCFGP_MC_CHANNELS_PER_GROUP = 1 ; static const uint8_t P9N2_MCS_MCFGP_MC_CHANNELS_PER_GROUP_LEN = 4 ; static const uint8_t P9N2_MCS_MCFGP_CHANNEL_0_GROUP_MEMBER_IDENTIFICATION = 5 ; static const uint8_t P9N2_MCS_MCFGP_CHANNEL_0_GROUP_MEMBER_IDENTIFICATION_LEN = 3 ; static const uint8_t P9N2_MCS_MCFGP_CHANNEL_1_GROUP_MEMBER_IDENTIFICATION = 8 ; static const uint8_t P9N2_MCS_MCFGP_CHANNEL_1_GROUP_MEMBER_IDENTIFICATION_LEN = 3 ; static const uint8_t P9N2_MCS_MCFGP_RESERVED_11_12 = 11 ; static const uint8_t P9N2_MCS_MCFGP_RESERVED_11_12_LEN = 2 ; static const uint8_t P9N2_MCS_MCFGP_GROUP_SIZE = 13 ; static const uint8_t P9N2_MCS_MCFGP_GROUP_SIZE_LEN = 11 ; static const uint8_t P9N2_MCS_MCFGP_GROUP_BASE_ADDRESS = 24 ; static const uint8_t P9N2_MCS_MCFGP_GROUP_BASE_ADDRESS_LEN = 24 ; static const uint8_t P9N2_MCS_MCFGPA_HOLE0_VALID = 0 ; static const uint8_t P9N2_MCS_MCFGPA_HOLE0_UPPER_ADDRESS_AT_END_OF_RANGE = 1 ; static const uint8_t P9N2_MCS_MCFGPA_HOLE0_LOWER_ADDRESS = 2 ; static const uint8_t P9N2_MCS_MCFGPA_HOLE0_LOWER_ADDRESS_LEN = 10 ; static const uint8_t P9N2_MCS_MCFGPA_HOLE0_UPPER_ADDRESS = 12 ; static const uint8_t P9N2_MCS_MCFGPA_HOLE0_UPPER_ADDRESS_LEN = 10 ; static const uint8_t P9N2_MCS_MCFGPA_RESERVED_22_27 = 22 ; static const uint8_t P9N2_MCS_MCFGPA_RESERVED_22_27_LEN = 6 ; static const uint8_t P9N2_MCS_MCFGPA_SMF_VALID = 28 ; static const uint8_t P9N2_MCS_MCFGPA_SMF_UPPER_ADDRESS_AT_END_OF_RANGE = 29 ; static const uint8_t P9N2_MCS_MCFGPA_SMF_LOWER_ADDRESS = 30 ; static const uint8_t P9N2_MCS_MCFGPA_SMF_LOWER_ADDRESS_LEN = 14 ; static const uint8_t P9N2_MCS_MCFGPA_SMF_UPPER_ADDRESS = 44 ; static const uint8_t P9N2_MCS_MCFGPA_SMF_UPPER_ADDRESS_LEN = 14 ; static const uint8_t P9N2_MCS_MCFGPM_VALID = 0 ; static const uint8_t P9N2_MCS_MCFGPM_RESERVED_1_12 = 1 ; static const uint8_t P9N2_MCS_MCFGPM_RESERVED_1_12_LEN = 12 ; static const uint8_t P9N2_MCS_MCFGPM_GROUP_SIZE = 13 ; static const uint8_t P9N2_MCS_MCFGPM_GROUP_SIZE_LEN = 11 ; static const uint8_t P9N2_MCS_MCFGPM_GROUP_BASE_ADDRESS = 24 ; static const uint8_t P9N2_MCS_MCFGPM_GROUP_BASE_ADDRESS_LEN = 24 ; static const uint8_t P9N2_MCS_MCFGPMA_HOLE0_VALID = 0 ; static const uint8_t P9N2_MCS_MCFGPMA_HOLE0_UPPER_ADDRESS_AT_END_OF_RANGE = 1 ; static const uint8_t P9N2_MCS_MCFGPMA_HOLE0_LOWER_ADDRESS = 2 ; static const uint8_t P9N2_MCS_MCFGPMA_HOLE0_LOWER_ADDRESS_LEN = 10 ; static const uint8_t P9N2_MCS_MCFGPMA_HOLE0_UPPER_ADDRESS = 12 ; static const uint8_t P9N2_MCS_MCFGPMA_HOLE0_UPPER_ADDRESS_LEN = 10 ; static const uint8_t P9N2_MCS_MCFGPMA_RESERVED_22_27 = 22 ; static const uint8_t P9N2_MCS_MCFGPMA_RESERVED_22_27_LEN = 6 ; static const uint8_t P9N2_MCS_MCFGPMA_SMF_VALID = 28 ; static const uint8_t P9N2_MCS_MCFGPMA_SMF_UPPER_ADDRESS_AT_END_OF_RANGE = 29 ; static const uint8_t P9N2_MCS_MCFGPMA_SMF_LOWER_ADDRESS = 30 ; static const uint8_t P9N2_MCS_MCFGPMA_SMF_LOWER_ADDRESS_LEN = 14 ; static const uint8_t P9N2_MCS_MCFGPMA_SMF_UPPER_ADDRESS = 44 ; static const uint8_t P9N2_MCS_MCFGPMA_SMF_UPPER_ADDRESS_LEN = 14 ; static const uint8_t P9N2_MCS_MCFIR_MC_INTERNAL_RECOVERABLE_ERROR = 0 ; static const uint8_t P9N2_MCS_MCFIR_MC_INTERNAL_NONRECOVERABLE_ERROR = 1 ; static const uint8_t P9N2_MCS_MCFIR_POWERBUS_PROTOCOL_ERROR = 2 ; static const uint8_t P9N2_MCS_MCFIR_RESERVED_3 = 3 ; static const uint8_t P9N2_MCS_MCFIR_MULTIPLE_BAR = 4 ; static const uint8_t P9N2_MCS_MCFIR_INVALID_ADDRESS = 5 ; static const uint8_t P9N2_MCS_MCFIR_HA_ILLEGAL_CONSUMER_ACCESS = 6 ; static const uint8_t P9N2_MCS_MCFIR_HA_ILLEGAL_PRODUCER_ACCESS = 7 ; static const uint8_t P9N2_MCS_MCFIR_COMMAND_LIST_TIMEOUT = 8 ; static const uint8_t P9N2_MCS_MCFIR_CHANNEL_0_TIMEOUT_ERROR = 9 ; static const uint8_t P9N2_MCS_MCFIR_CHANNEL_1_TIMEOUT_ERROR = 10 ; static const uint8_t P9N2_MCS_MCFIR_MCS_WAT0 = 11 ; static const uint8_t P9N2_MCS_MCFIR_MCS_WAT1 = 12 ; static const uint8_t P9N2_MCS_MCFIR_MCS_WAT2 = 13 ; static const uint8_t P9N2_MCS_MCFIR_MCS_WAT3 = 14 ; static const uint8_t P9N2_MCS_MCFIR_MIRROR_ACTION_OCCURRED = 15 ; static const uint8_t P9N2_MCS_MCFIR_CENTAUR_SYNC_COMMAND_OCCURRED = 16 ; static const uint8_t P9N2_MCS_MCFIR_MS_WAT_DEBUG_CONFIG_REG_ERROR = 17 ; static const uint8_t P9N2_MCS_MCFIR_RESERVED_18 = 18 ; static const uint8_t P9N2_MCS_MCFIR_RESERVED_19 = 19 ; static const uint8_t P9N2_MCS_MCFIR_RESERVED_20 = 20 ; static const uint8_t P9N2_MCS_MCFIR_RESERVED_21 = 21 ; static const uint8_t P9N2_MCS_MCFIR_INVALID_SMF_ACCESS = 22 ; static const uint8_t P9N2_MCS_MCFIR_RESERVED_23 = 23 ; static const uint8_t P9N2_MCS_MCFIR_INTERNAL_SCOM_ERROR = 24 ; static const uint8_t P9N2_MCS_MCFIR_INTERNAL_SCOM_ERROR_CLONE = 25 ; static const uint8_t P9N2_MCS_MCFIRACT0_ACTION_0 = 0 ; static const uint8_t P9N2_MCS_MCFIRACT0_ACTION_0_LEN = 26 ; static const uint8_t P9N2_MCS_MCFIRACT1_ACTION_1 = 0 ; static const uint8_t P9N2_MCS_MCFIRACT1_ACTION_1_LEN = 26 ; static const uint8_t P9N2_MCS_MCFIRMASK_FIR_MASK = 0 ; static const uint8_t P9N2_MCS_MCFIRMASK_FIR_MASK_LEN = 26 ; static const uint8_t P9N2_MCS_MCFIRWOF_WOF = 0 ; static const uint8_t P9N2_MCS_MCFIRWOF_WOF_LEN = 26 ; static const uint8_t P9N2_MCS_MCLFSR_RETRY_LPC_LFSR_SELECT = 0 ; static const uint8_t P9N2_MCS_MCLFSR_RETRY_LPC_LFSR_SELECT_LEN = 2 ; static const uint8_t P9N2_MCS_MCLFSR_ENABLE_READ_LFSR_DATA = 2 ; static const uint8_t P9N2_MCS_MCLFSR_ENABLE_CHANNEL_ARB_DISABLE_HP_OP_LFSR = 3 ; static const uint8_t P9N2_MCS_MCLFSR_ENABLE_CHANNEL_ARB_FORCE_WR_HP_LFSR = 4 ; static const uint8_t P9N2_MCS_MCLFSR_RESERVED_5_15 = 5 ; static const uint8_t P9N2_MCS_MCLFSR_RESERVED_5_15_LEN = 11 ; static const uint8_t P9N2_MCS_MCMODE0_CENTAUR_MODE = 0 ; static const uint8_t P9N2_MCS_MCMODE0_RESERVED_1 = 1 ; static const uint8_t P9N2_MCS_MCMODE0_CENTAURP_ENABLE_CP_ME = 2 ; static const uint8_t P9N2_MCS_MCMODE0_CENTAURP_ENABLE_NEW_AMO = 3 ; static const uint8_t P9N2_MCS_MCMODE0_CENTAURP_INBAND_IS_63 = 4 ; static const uint8_t P9N2_MCS_MCMODE0_SYNC_MODE = 5 ; static const uint8_t P9N2_MCS_MCMODE0_ASYNC_MODE = 6 ; static const uint8_t P9N2_MCS_MCMODE0_CENTAURP_ENABLE_ECRESP = 7 ; static const uint8_t P9N2_MCS_MCMODE0_ENABLE_DROP_FP_DYN64_ACTIVE = 8 ; static const uint8_t P9N2_MCS_MCMODE0_ENABLE_64_128B_READ = 9 ; static const uint8_t P9N2_MCS_MCMODE0_CENTAURP_ENABLE_CENTAURP_CMD = 10 ; static const uint8_t P9N2_MCS_MCMODE0_CENTAURP_ENABLE_BYPASS_CMD = 11 ; static const uint8_t P9N2_MCS_MCMODE0_CENTAURP_ENABLE_CR_SIDEBAND = 12 ; static const uint8_t P9N2_MCS_MCMODE0_CENTAURP_ENABLE_DTAG_CR = 13 ; static const uint8_t P9N2_MCS_MCMODE0_EN_CHARB_STALL = 14 ; static const uint8_t P9N2_MCS_MCMODE0_SYNC_FENCE = 15 ; static const uint8_t P9N2_MCS_MCMODE0_ECRESP_HASH_MODE = 16 ; static const uint8_t P9N2_MCS_MCMODE0_FORCE_COMMANDLIST_VALID = 17 ; static const uint8_t P9N2_MCS_MCMODE0_FORCE_ANY_BAR_ACTIVE = 18 ; static const uint8_t P9N2_MCS_MCMODE0_MCS_RESET_KEEPER = 19 ; static const uint8_t P9N2_MCS_MCMODE0_ENABLE_CENTAUR_SYNC = 20 ; static const uint8_t P9N2_MCS_MCMODE0_ENABLE_EMERGENCY_THROTTLE = 21 ; static const uint8_t P9N2_MCS_MCMODE0_ENABLE_CENTAUR_CHECKSTOP_COMMAND = 22 ; static const uint8_t P9N2_MCS_MCMODE0_ENABLE_CENTAUR_TRACESTOP_COMMAND = 23 ; static const uint8_t P9N2_MCS_MCMODE0_ENABLE_COMBINED_RESPONSE_PARITY_ERROR = 24 ; static const uint8_t P9N2_MCS_MCMODE0_RESERVED_25_26 = 25 ; static const uint8_t P9N2_MCS_MCMODE0_RESERVED_25_26_LEN = 2 ; static const uint8_t P9N2_MCS_MCMODE0_DISABLE_MC_SYNC = 27 ; static const uint8_t P9N2_MCS_MCMODE0_DISABLE_MC_PAIR_SYNC = 28 ; static const uint8_t P9N2_MCS_MCMODE0_64B_WR_IS_PWRT = 29 ; static const uint8_t P9N2_MCS_MCMODE0_CL_GLOBAL_DISABLE = 30 ; static const uint8_t P9N2_MCS_MCMODE0_CL_GLOBAL_DISABLE_LEN = 10 ; static const uint8_t P9N2_MCS_MCMODE0_CL_FINE_DISABLE = 40 ; static const uint8_t P9N2_MCS_MCMODE0_CL_FINE_DISABLE_LEN = 7 ; static const uint8_t P9N2_MCS_MCMODE0_RESERVED_47 = 47 ; static const uint8_t P9N2_MCS_MCMODE0_ENABLE_CENTAUR_PERFMON_COMMAND = 48 ; static const uint8_t P9N2_MCS_MCMODE0_SCOM_PERFMON_START_COMMAND = 49 ; static const uint8_t P9N2_MCS_MCMODE0_SCOM_PERFMON_STOP_COMMAND = 50 ; static const uint8_t P9N2_MCS_MCMODE0_DISABLE_PERFMON_RESET_ON_START = 51 ; static const uint8_t P9N2_MCS_MCMODE0_GROUP_ADDRESS_INTERLEAVE_GRANULARITY = 52 ; static const uint8_t P9N2_MCS_MCMODE0_GROUP_ADDRESS_INTERLEAVE_GRANULARITY_LEN = 4 ; static const uint8_t P9N2_MCS_MCMODE0_MPIPL_CANCEL = 56 ; static const uint8_t P9N2_MCS_MCMODE0_RESERVED_57_63 = 57 ; static const uint8_t P9N2_MCS_MCMODE0_RESERVED_57_63_LEN = 7 ; static const uint8_t P9N2_MCS_MCMODE1_DISABLE_HIGH_PRIORITY = 0 ; static const uint8_t P9N2_MCS_MCMODE1_DISABLE_HIGH_PRIORITY_LEN = 10 ; static const uint8_t P9N2_MCS_MCMODE1_DISABLE_FP_M_BIT = 10 ; static const uint8_t P9N2_MCS_MCMODE1_DISABLE_CRC_ECC_BYPASS = 11 ; static const uint8_t P9N2_MCS_MCMODE1_DISABLE_CRC_ECC_BYPASS_LEN = 6 ; static const uint8_t P9N2_MCS_MCMODE1_DISABLE_FP_CRC_ECC_BYPASS = 17 ; static const uint8_t P9N2_MCS_MCMODE1_ENABLE_CRC_ECC_BYPASS_NODAL_ONLY = 18 ; static const uint8_t P9N2_MCS_MCMODE1_DISABLE_SPEC_SOURCE_SCOPE = 19 ; static const uint8_t P9N2_MCS_MCMODE1_DISABLE_SPEC_SOURCE_SCOPE_LEN = 9 ; static const uint8_t P9N2_MCS_MCMODE1_DISABLE_CENTAUR_CMD_PREFETCH = 28 ; static const uint8_t P9N2_MCS_MCMODE1_DISABLE_CENTAUR_CMD_PREFETCH_LEN = 4 ; static const uint8_t P9N2_MCS_MCMODE1_DISABLE_ALL_SPEC_OPS = 32 ; static const uint8_t P9N2_MCS_MCMODE1_DISABLE_SPEC_OP = 33 ; static const uint8_t P9N2_MCS_MCMODE1_DISABLE_SPEC_OP_LEN = 19 ; static const uint8_t P9N2_MCS_MCMODE1_DISABLE_CI = 52 ; static const uint8_t P9N2_MCS_MCMODE1_DISABLE_CI_LEN = 2 ; static const uint8_t P9N2_MCS_MCMODE1_DISABLE_COMMAND_BYPASS = 54 ; static const uint8_t P9N2_MCS_MCMODE1_DISABLE_COMMAND_BYPASS_LEN = 7 ; static const uint8_t P9N2_MCS_MCMODE1_DISABLE_FP_COMMAND_BYPASS = 61 ; static const uint8_t P9N2_MCS_MCMODE1_DISABLE_BYPASS_IN_READ_DATAFLOW = 62 ; static const uint8_t P9N2_MCS_MCMODE1_RESERVED_63 = 63 ; static const uint8_t P9N2_MCS_MCMODE2_FORCE_SFSTAT_ACTIVE = 0 ; static const uint8_t P9N2_MCS_MCMODE2_DISABLE_MDI0 = 1 ; static const uint8_t P9N2_MCS_MCMODE2_DISABLE_MDI0_LEN = 13 ; static const uint8_t P9N2_MCS_MCMODE2_RESERVED_14 = 14 ; static const uint8_t P9N2_MCS_MCMODE2_RESERVED_15 = 15 ; static const uint8_t P9N2_MCS_MCMODE2_DISABLE_SHARED_PRESP_ABORT = 16 ; static const uint8_t P9N2_MCS_MCMODE2_DISABLE_RETRY_LOST_CLAIM = 17 ; static const uint8_t P9N2_MCS_MCMODE2_RESERVED_18 = 18 ; static const uint8_t P9N2_MCS_MCMODE2_SMF_MODE_SELECT = 19 ; static const uint8_t P9N2_MCS_MCMODE2_SMF_MODE_SELECT_LEN = 2 ; static const uint8_t P9N2_MCS_MCMODE2_RESERVED_21_22 = 21 ; static const uint8_t P9N2_MCS_MCMODE2_RESERVED_21_22_LEN = 2 ; static const uint8_t P9N2_MCS_MCMODE2_ENABLE_OP_HIT_ERROR = 23 ; static const uint8_t P9N2_MCS_MCMODE2_COLLISION_MODES = 24 ; static const uint8_t P9N2_MCS_MCMODE2_COLLISION_MODES_LEN = 16 ; static const uint8_t P9N2_MCS_MCMODE2_EPSILON_LENGTH = 40 ; static const uint8_t P9N2_MCS_MCMODE2_EPSILON_LENGTH_LEN = 4 ; static const uint8_t P9N2_MCS_MCMODE2_ENABLE_FIR_SPEC_ATTN = 44 ; static const uint8_t P9N2_MCS_MCMODE2_ENABLE_FIR_HOST_ATTN = 45 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT0_VALID = 0 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT0_D_VALUE = 1 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_12GB_ENABLE = 2 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT0_M0_VALID = 5 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT0_M1_VALID = 6 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT0_S0_VALID = 9 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT0_S1_VALID = 10 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT0_S2_VALID = 11 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT0_B2_VALID = 12 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT0_ROW15_VALID = 13 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT0_ROW16_VALID = 14 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT0_ROW17_VALID = 15 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT1_VALID = 16 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT1_D_VALUE = 17 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT1_M0_VALID = 21 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT1_M1_VALID = 22 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT1_S0_VALID = 25 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT1_S1_VALID = 26 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT1_S2_VALID = 27 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT1_B2_VALID = 28 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT1_ROW15_VALID = 29 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT1_ROW16_VALID = 30 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_SLOT1_ROW17_VALID = 31 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_D_BIT_MAP = 35 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_D_BIT_MAP_LEN = 5 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_M0_BIT_MAP = 41 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_M0_BIT_MAP_LEN = 3 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_M1_BIT_MAP = 47 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_M1_BIT_MAP_LEN = 5 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_R17_BIT_MAP = 53 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_R17_BIT_MAP_LEN = 3 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_R16_BIT_MAP = 57 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_R16_BIT_MAP_LEN = 3 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_R15_BIT_MAP = 61 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT0_R15_BIT_MAP_LEN = 3 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT0_VALID = 0 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT0_D_VALUE = 1 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_12GB_ENABLE = 2 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT0_M0_VALID = 5 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT0_M1_VALID = 6 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT0_S0_VALID = 9 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT0_S1_VALID = 10 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT0_S2_VALID = 11 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT0_B2_VALID = 12 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT0_ROW15_VALID = 13 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT0_ROW16_VALID = 14 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT0_ROW17_VALID = 15 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT1_VALID = 16 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT1_D_VALUE = 17 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT1_M0_VALID = 21 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT1_M1_VALID = 22 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT1_S0_VALID = 25 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT1_S1_VALID = 26 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT1_S2_VALID = 27 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT1_B2_VALID = 28 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT1_ROW15_VALID = 29 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT1_ROW16_VALID = 30 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_SLOT1_ROW17_VALID = 31 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_D_BIT_MAP = 35 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_D_BIT_MAP_LEN = 5 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_M0_BIT_MAP = 41 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_M0_BIT_MAP_LEN = 3 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_M1_BIT_MAP = 47 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_M1_BIT_MAP_LEN = 5 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_R17_BIT_MAP = 53 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_R17_BIT_MAP_LEN = 3 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_R16_BIT_MAP = 57 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_R16_BIT_MAP_LEN = 3 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_R15_BIT_MAP = 61 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT0_R15_BIT_MAP_LEN = 3 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT1_S0_BIT_MAP = 3 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT1_S0_BIT_MAP_LEN = 5 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT1_S1_BIT_MAP = 11 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT1_S1_BIT_MAP_LEN = 5 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT1_S2_BIT_MAP = 19 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT1_S2_BIT_MAP_LEN = 5 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT1_COL4_BIT_MAP = 35 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT1_COL4_BIT_MAP_LEN = 5 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT1_COL5_BIT_MAP = 43 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT1_COL5_BIT_MAP_LEN = 5 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT1_COL6_BIT_MAP = 51 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT1_COL6_BIT_MAP_LEN = 5 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT1_COL7_BIT_MAP = 59 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT1_COL7_BIT_MAP_LEN = 5 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT1_S0_BIT_MAP = 3 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT1_S0_BIT_MAP_LEN = 5 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT1_S1_BIT_MAP = 11 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT1_S1_BIT_MAP_LEN = 5 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT1_S2_BIT_MAP = 19 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT1_S2_BIT_MAP_LEN = 5 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT1_COL4_BIT_MAP = 35 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT1_COL4_BIT_MAP_LEN = 5 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT1_COL5_BIT_MAP = 43 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT1_COL5_BIT_MAP_LEN = 5 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT1_COL6_BIT_MAP = 51 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT1_COL6_BIT_MAP_LEN = 5 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT1_COL7_BIT_MAP = 59 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT1_COL7_BIT_MAP_LEN = 5 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT2_COL8_BIT_MAP = 3 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT2_COL8_BIT_MAP_LEN = 5 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT2_COL9_BIT_MAP = 11 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT2_COL9_BIT_MAP_LEN = 5 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT2_BANK0_BIT_MAP = 19 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT2_BANK0_BIT_MAP_LEN = 5 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT2_BANK1_BIT_MAP = 27 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT2_BANK1_BIT_MAP_LEN = 5 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT2_BANK2_BIT_MAP = 35 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT2_BANK2_BIT_MAP_LEN = 5 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT2_BANK_GROUP0_BIT_MAP = 43 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT2_BANK_GROUP0_BIT_MAP_LEN = 5 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT2_BANK_GROUP1_BIT_MAP = 51 ; static const uint8_t P9N2_MCS_PORT02_MCP0XLT2_BANK_GROUP1_BIT_MAP_LEN = 5 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT2_COL8_BIT_MAP = 3 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT2_COL8_BIT_MAP_LEN = 5 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT2_COL9_BIT_MAP = 11 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT2_COL9_BIT_MAP_LEN = 5 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT2_BANK0_BIT_MAP = 19 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT2_BANK0_BIT_MAP_LEN = 5 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT2_BANK1_BIT_MAP = 27 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT2_BANK1_BIT_MAP_LEN = 5 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT2_BANK2_BIT_MAP = 35 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT2_BANK2_BIT_MAP_LEN = 5 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT2_BANK_GROUP0_BIT_MAP = 43 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT2_BANK_GROUP0_BIT_MAP_LEN = 5 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT2_BANK_GROUP1_BIT_MAP = 51 ; static const uint8_t P9N2_MCS_PORT13_MCP0XLT2_BANK_GROUP1_BIT_MAP_LEN = 5 ; static const uint8_t P9N2_MCS_PORT02_MCPERF0_ENABLE_DYNAMIC_WR_USAGE = 0 ; static const uint8_t P9N2_MCS_PORT02_MCPERF0_ENABLE_DYNAMIC_PF_USAGE = 1 ; static const uint8_t P9N2_MCS_PORT02_MCPERF0_DYNAMIC_WINDOW_SELECT = 2 ; static const uint8_t P9N2_MCS_PORT02_MCPERF0_DYNAMIC_WINDOW_SELECT_LEN = 2 ; static const uint8_t P9N2_MCS_PORT02_MCPERF0_NUM_SEC_MIRROR_RSVD = 4 ; static const uint8_t P9N2_MCS_PORT02_MCPERF0_NUM_SEC_MIRROR_RSVD_LEN = 4 ; static const uint8_t P9N2_MCS_PORT02_MCPERF0_NUM_HPC_RD_RSVD = 8 ; static const uint8_t P9N2_MCS_PORT02_MCPERF0_NUM_HPC_RD_RSVD_LEN = 4 ; static const uint8_t P9N2_MCS_PORT02_MCPERF0_NUM_HA_RSVD = 12 ; static const uint8_t P9N2_MCS_PORT02_MCPERF0_NUM_HA_RSVD_LEN = 4 ; static const uint8_t P9N2_MCS_PORT02_MCPERF0_NUM_HTM_RSVD = 16 ; static const uint8_t P9N2_MCS_PORT02_MCPERF0_NUM_HTM_RSVD_LEN = 6 ; static const uint8_t P9N2_MCS_PORT02_MCPERF0_AMO_LIMIT = 22 ; static const uint8_t P9N2_MCS_PORT02_MCPERF0_AMO_LIMIT_LEN = 6 ; static const uint8_t P9N2_MCS_PORT02_MCPERF0_PREFETCH_LIMIT = 28 ; static const uint8_t P9N2_MCS_PORT02_MCPERF0_PREFETCH_LIMIT_LEN = 6 ; static const uint8_t P9N2_MCS_PORT02_MCPERF0_FASTPATH_LIMIT = 34 ; static const uint8_t P9N2_MCS_PORT02_MCPERF0_FASTPATH_LIMIT_LEN = 6 ; static const uint8_t P9N2_MCS_PORT02_MCPERF0_WR_RSVD_LOWER_OR_STATIC_LIMIT = 40 ; static const uint8_t P9N2_MCS_PORT02_MCPERF0_WR_RSVD_LOWER_OR_STATIC_LIMIT_LEN = 6 ; static const uint8_t P9N2_MCS_PORT02_MCPERF0_WR_RSVD_UPPER_LIMIT = 46 ; static const uint8_t P9N2_MCS_PORT02_MCPERF0_WR_RSVD_UPPER_LIMIT_LEN = 6 ; static const uint8_t P9N2_MCS_PORT02_MCPERF0_NUM_CL_ACTIVE = 52 ; static const uint8_t P9N2_MCS_PORT02_MCPERF0_NUM_CL_ACTIVE_LEN = 6 ; static const uint8_t P9N2_MCS_PORT02_MCPERF0_NUM_HA_RSVD_SEL = 58 ; static const uint8_t P9N2_MCS_PORT02_MCPERF0_NUM_HA_RSVD_SEL_LEN = 2 ; static const uint8_t P9N2_MCS_PORT02_MCPERF0_NUM_HTM_RSVD_SEL = 60 ; static const uint8_t P9N2_MCS_PORT02_MCPERF0_NUM_HTM_RSVD_SEL_LEN = 2 ; static const uint8_t P9N2_MCS_PORT02_MCPERF0_NUM_SEC_MIRROR_RSVD_SEL = 62 ; static const uint8_t P9N2_MCS_PORT02_MCPERF0_NUM_SEC_MIRROR_RSVD_SEL_LEN = 2 ; static const uint8_t P9N2_MCS_PORT13_MCPERF0_ENABLE_DYNAMIC_WR_USAGE = 0 ; static const uint8_t P9N2_MCS_PORT13_MCPERF0_ENABLE_DYNAMIC_PF_USAGE = 1 ; static const uint8_t P9N2_MCS_PORT13_MCPERF0_DYNAMIC_WINDOW_SELECT = 2 ; static const uint8_t P9N2_MCS_PORT13_MCPERF0_DYNAMIC_WINDOW_SELECT_LEN = 2 ; static const uint8_t P9N2_MCS_PORT13_MCPERF0_NUM_SEC_MIRROR_RSVD = 4 ; static const uint8_t P9N2_MCS_PORT13_MCPERF0_NUM_SEC_MIRROR_RSVD_LEN = 4 ; static const uint8_t P9N2_MCS_PORT13_MCPERF0_NUM_HPC_RD_RSVD = 8 ; static const uint8_t P9N2_MCS_PORT13_MCPERF0_NUM_HPC_RD_RSVD_LEN = 4 ; static const uint8_t P9N2_MCS_PORT13_MCPERF0_NUM_HA_RSVD = 12 ; static const uint8_t P9N2_MCS_PORT13_MCPERF0_NUM_HA_RSVD_LEN = 4 ; static const uint8_t P9N2_MCS_PORT13_MCPERF0_NUM_HTM_RSVD = 16 ; static const uint8_t P9N2_MCS_PORT13_MCPERF0_NUM_HTM_RSVD_LEN = 6 ; static const uint8_t P9N2_MCS_PORT13_MCPERF0_AMO_LIMIT = 22 ; static const uint8_t P9N2_MCS_PORT13_MCPERF0_AMO_LIMIT_LEN = 6 ; static const uint8_t P9N2_MCS_PORT13_MCPERF0_PREFETCH_LIMIT = 28 ; static const uint8_t P9N2_MCS_PORT13_MCPERF0_PREFETCH_LIMIT_LEN = 6 ; static const uint8_t P9N2_MCS_PORT13_MCPERF0_FASTPATH_LIMIT = 34 ; static const uint8_t P9N2_MCS_PORT13_MCPERF0_FASTPATH_LIMIT_LEN = 6 ; static const uint8_t P9N2_MCS_PORT13_MCPERF0_WR_RSVD_LOWER_OR_STATIC_LIMIT = 40 ; static const uint8_t P9N2_MCS_PORT13_MCPERF0_WR_RSVD_LOWER_OR_STATIC_LIMIT_LEN = 6 ; static const uint8_t P9N2_MCS_PORT13_MCPERF0_WR_RSVD_UPPER_LIMIT = 46 ; static const uint8_t P9N2_MCS_PORT13_MCPERF0_WR_RSVD_UPPER_LIMIT_LEN = 6 ; static const uint8_t P9N2_MCS_PORT13_MCPERF0_NUM_CL_ACTIVE = 52 ; static const uint8_t P9N2_MCS_PORT13_MCPERF0_NUM_CL_ACTIVE_LEN = 6 ; static const uint8_t P9N2_MCS_PORT13_MCPERF0_NUM_HA_RSVD_SEL = 58 ; static const uint8_t P9N2_MCS_PORT13_MCPERF0_NUM_HA_RSVD_SEL_LEN = 2 ; static const uint8_t P9N2_MCS_PORT13_MCPERF0_NUM_HTM_RSVD_SEL = 60 ; static const uint8_t P9N2_MCS_PORT13_MCPERF0_NUM_HTM_RSVD_SEL_LEN = 2 ; static const uint8_t P9N2_MCS_PORT13_MCPERF0_NUM_SEC_MIRROR_RSVD_SEL = 62 ; static const uint8_t P9N2_MCS_PORT13_MCPERF0_NUM_SEC_MIRROR_RSVD_SEL_LEN = 2 ; static const uint8_t P9N2_MCS_MCPERF1_DISABLE_FASTPATH = 0 ; static const uint8_t P9N2_MCS_MCPERF1_RESERVED_1_2 = 1 ; static const uint8_t P9N2_MCS_MCPERF1_RESERVED_1_2_LEN = 2 ; static const uint8_t P9N2_MCS_MCPERF1_ENABLE_DISABLE_SPEC_READ_FOR_NONDMA_GROUP_PUMP_LOCAL_READ = 3 ; static const uint8_t P9N2_MCS_MCPERF1_ENABLE_DISABLE_SPEC_READ_FOR_NONDMA_SYSTEM_PUMP_LOCAL_READ = 4 ; static const uint8_t P9N2_MCS_MCPERF1_DISABLE_FASTPATH_QOS = 5 ; static const uint8_t P9N2_MCS_MCPERF1_DISABLE_CHARB_BYPASS = 6 ; static const uint8_t P9N2_MCS_MCPERF1_DISABLE_SPEC_DISABLE_HINT_BIT = 7 ; static const uint8_t P9N2_MCS_MCPERF1_DISABLE_2K_SPEC_FILTER = 8 ; static const uint8_t P9N2_MCS_MCPERF1_DISABLE_RESET_2K_COUNT_IF_HINT_BIT_SET = 9 ; static const uint8_t P9N2_MCS_MCPERF1_D2K_SPEC_FILTER_COUNTER_LFSR_INC_SELECT = 10 ; static const uint8_t P9N2_MCS_MCPERF1_D2K_SPEC_FILTER_COUNTER_LFSR_INC_SELECT_LEN = 4 ; static const uint8_t P9N2_MCS_MCPERF1_D2K_SPEC_FILTER_COUNTER_LFSR_DEC_SELECT = 14 ; static const uint8_t P9N2_MCS_MCPERF1_D2K_SPEC_FILTER_COUNTER_LFSR_DEC_SELECT_LEN = 4 ; static const uint8_t P9N2_MCS_MCPERF1_SPEC_READ_FILTER_NO_HASH_MODE = 18 ; static const uint8_t P9N2_MCS_MCPERF1_RESERVED_19_31 = 19 ; static const uint8_t P9N2_MCS_MCPERF1_RESERVED_19_31_LEN = 13 ; static const uint8_t P9N2_MCS_MCPERF1_PF_DROP_CNT_THRESH = 32 ; static const uint8_t P9N2_MCS_MCPERF1_PF_DROP_CNT_THRESH_LEN = 7 ; static const uint8_t P9N2_MCS_MCPERF1_CP_RETRY_THRESH = 39 ; static const uint8_t P9N2_MCS_MCPERF1_CP_RETRY_THRESH_LEN = 7 ; static const uint8_t P9N2_MCS_MCPERF1_MERGE_CAPACITY_LIMIT = 46 ; static const uint8_t P9N2_MCS_MCPERF1_MERGE_CAPACITY_LIMIT_LEN = 4 ; static const uint8_t P9N2_MCS_MCPERF1_RRQ_CAPACITY_LIMIT = 50 ; static const uint8_t P9N2_MCS_MCPERF1_RRQ_CAPACITY_LIMIT_LEN = 5 ; static const uint8_t P9N2_MCS_MCPERF1_WRQ_CAPACITY_LIMIT = 55 ; static const uint8_t P9N2_MCS_MCPERF1_WRQ_CAPACITY_LIMIT_LEN = 6 ; static const uint8_t P9N2_MCS_MCPERF1_ENABLE_PF_DROP_CMDLIST = 61 ; static const uint8_t P9N2_MCS_MCPERF1_ENABLE_PF_DROP_SRQ = 62 ; static const uint8_t P9N2_MCS_MCPERF1_ENABLE_PREFETCH_PROMOTE = 63 ; static const uint8_t P9N2_MCS_PORT02_MCPERF2_PF_DROP_VALUE0 = 0 ; static const uint8_t P9N2_MCS_PORT02_MCPERF2_PF_DROP_VALUE0_LEN = 3 ; static const uint8_t P9N2_MCS_PORT02_MCPERF2_PF_DROP_VALUE1 = 3 ; static const uint8_t P9N2_MCS_PORT02_MCPERF2_PF_DROP_VALUE1_LEN = 3 ; static const uint8_t P9N2_MCS_PORT02_MCPERF2_PF_DROP_VALUE2 = 6 ; static const uint8_t P9N2_MCS_PORT02_MCPERF2_PF_DROP_VALUE2_LEN = 3 ; static const uint8_t P9N2_MCS_PORT02_MCPERF2_PF_DROP_VALUE3 = 9 ; static const uint8_t P9N2_MCS_PORT02_MCPERF2_PF_DROP_VALUE3_LEN = 3 ; static const uint8_t P9N2_MCS_PORT02_MCPERF2_DISABLE_DROPABLE = 12 ; static const uint8_t P9N2_MCS_PORT02_MCPERF2_REFRESH_BLOCK_CONFIG = 13 ; static const uint8_t P9N2_MCS_PORT02_MCPERF2_REFRESH_BLOCK_CONFIG_LEN = 3 ; static const uint8_t P9N2_MCS_PORT02_MCPERF2_ENABLE_REFRESH_BLOCK_SQ = 16 ; static const uint8_t P9N2_MCS_PORT02_MCPERF2_ENABLE_REFRESH_BLOCK_NSQ = 17 ; static const uint8_t P9N2_MCS_PORT02_MCPERF2_ENABLE_REFRESH_BLOCK_DISP = 18 ; static const uint8_t P9N2_MCS_PORT02_MCPERF2_PERF_THRESH = 19 ; static const uint8_t P9N2_MCS_PORT02_MCPERF2_PERF_THRESH_LEN = 5 ; static const uint8_t P9N2_MCS_PORT02_MCPERF2_NSQ_LFSR_CNTL = 24 ; static const uint8_t P9N2_MCS_PORT02_MCPERF2_NSQ_LFSR_CNTL_LEN = 4 ; static const uint8_t P9N2_MCS_PORT02_MCPERF2_SQ_LFSR_CNTL = 28 ; static const uint8_t P9N2_MCS_PORT02_MCPERF2_SQ_LFSR_CNTL_LEN = 4 ; static const uint8_t P9N2_MCS_PORT02_MCPERF2_EN_CHARB_CMD_STALL = 32 ; static const uint8_t P9N2_MCS_PORT02_MCPERF2_EN_CHARB_RRQ_STALL = 33 ; static const uint8_t P9N2_MCS_PORT02_MCPERF2_EN_CHARB_WRQ_STALL = 34 ; static const uint8_t P9N2_MCS_PORT02_MCPERF2_EN_CHARB_MERGE_STALL = 35 ; static const uint8_t P9N2_MCS_PORT02_MCPERF2_EN_64_128_PB_READ = 36 ; static const uint8_t P9N2_MCS_PORT02_MCPERF2_RCTRL_CONFIG = 37 ; static const uint8_t P9N2_MCS_PORT02_MCPERF2_RCTRL_CONFIG_LEN = 3 ; static const uint8_t P9N2_MCS_PORT02_MCPERF2_ALT_M = 40 ; static const uint8_t P9N2_MCS_PORT02_MCPERF2_ALT_M_LEN = 4 ; static const uint8_t P9N2_MCS_PORT02_MCPERF2_NUM_CLEAN = 44 ; static const uint8_t P9N2_MCS_PORT02_MCPERF2_NUM_CLEAN_LEN = 6 ; static const uint8_t P9N2_MCS_PORT02_MCPERF2_NUM_RMW_BUF = 50 ; static const uint8_t P9N2_MCS_PORT02_MCPERF2_NUM_RMW_BUF_LEN = 5 ; static const uint8_t P9N2_MCS_PORT02_MCPERF2_RMW_BUF_THRESH = 55 ; static const uint8_t P9N2_MCS_PORT02_MCPERF2_RMW_BUF_THRESH_LEN = 5 ; static const uint8_t P9N2_MCS_PORT02_MCPERF2_EN_ALT_ECR_NO_ERR = 60 ; static const uint8_t P9N2_MCS_PORT02_MCPERF2_EN_ALT_ECR_ERR = 61 ; static const uint8_t P9N2_MCS_PORT02_MCPERF2_EN_ALT_CR = 62 ; static const uint8_t P9N2_MCS_PORT02_MCPERF2_LOAD_RSVD_VALUES = 63 ; static const uint8_t P9N2_MCS_PORT13_MCPERF2_PF_DROP_VALUE0 = 0 ; static const uint8_t P9N2_MCS_PORT13_MCPERF2_PF_DROP_VALUE0_LEN = 3 ; static const uint8_t P9N2_MCS_PORT13_MCPERF2_PF_DROP_VALUE1 = 3 ; static const uint8_t P9N2_MCS_PORT13_MCPERF2_PF_DROP_VALUE1_LEN = 3 ; static const uint8_t P9N2_MCS_PORT13_MCPERF2_PF_DROP_VALUE2 = 6 ; static const uint8_t P9N2_MCS_PORT13_MCPERF2_PF_DROP_VALUE2_LEN = 3 ; static const uint8_t P9N2_MCS_PORT13_MCPERF2_PF_DROP_VALUE3 = 9 ; static const uint8_t P9N2_MCS_PORT13_MCPERF2_PF_DROP_VALUE3_LEN = 3 ; static const uint8_t P9N2_MCS_PORT13_MCPERF2_DISABLE_DROPABLE = 12 ; static const uint8_t P9N2_MCS_PORT13_MCPERF2_REFRESH_BLOCK_CONFIG = 13 ; static const uint8_t P9N2_MCS_PORT13_MCPERF2_REFRESH_BLOCK_CONFIG_LEN = 3 ; static const uint8_t P9N2_MCS_PORT13_MCPERF2_ENABLE_REFRESH_BLOCK_SQ = 16 ; static const uint8_t P9N2_MCS_PORT13_MCPERF2_ENABLE_REFRESH_BLOCK_NSQ = 17 ; static const uint8_t P9N2_MCS_PORT13_MCPERF2_ENABLE_REFRESH_BLOCK_DISP = 18 ; static const uint8_t P9N2_MCS_PORT13_MCPERF2_PERF_THRESH = 19 ; static const uint8_t P9N2_MCS_PORT13_MCPERF2_PERF_THRESH_LEN = 5 ; static const uint8_t P9N2_MCS_PORT13_MCPERF2_NSQ_LFSR_CNTL = 24 ; static const uint8_t P9N2_MCS_PORT13_MCPERF2_NSQ_LFSR_CNTL_LEN = 4 ; static const uint8_t P9N2_MCS_PORT13_MCPERF2_SQ_LFSR_CNTL = 28 ; static const uint8_t P9N2_MCS_PORT13_MCPERF2_SQ_LFSR_CNTL_LEN = 4 ; static const uint8_t P9N2_MCS_PORT13_MCPERF2_EN_CHARB_CMD_STALL = 32 ; static const uint8_t P9N2_MCS_PORT13_MCPERF2_EN_CHARB_RRQ_STALL = 33 ; static const uint8_t P9N2_MCS_PORT13_MCPERF2_EN_CHARB_WRQ_STALL = 34 ; static const uint8_t P9N2_MCS_PORT13_MCPERF2_EN_CHARB_MERGE_STALL = 35 ; static const uint8_t P9N2_MCS_PORT13_MCPERF2_EN_64_128_PB_READ = 36 ; static const uint8_t P9N2_MCS_PORT13_MCPERF2_RCTRL_CONFIG = 37 ; static const uint8_t P9N2_MCS_PORT13_MCPERF2_RCTRL_CONFIG_LEN = 3 ; static const uint8_t P9N2_MCS_PORT13_MCPERF2_ALT_M = 40 ; static const uint8_t P9N2_MCS_PORT13_MCPERF2_ALT_M_LEN = 4 ; static const uint8_t P9N2_MCS_PORT13_MCPERF2_NUM_CLEAN = 44 ; static const uint8_t P9N2_MCS_PORT13_MCPERF2_NUM_CLEAN_LEN = 6 ; static const uint8_t P9N2_MCS_PORT13_MCPERF2_NUM_RMW_BUF = 50 ; static const uint8_t P9N2_MCS_PORT13_MCPERF2_NUM_RMW_BUF_LEN = 5 ; static const uint8_t P9N2_MCS_PORT13_MCPERF2_RMW_BUF_THRESH = 55 ; static const uint8_t P9N2_MCS_PORT13_MCPERF2_RMW_BUF_THRESH_LEN = 5 ; static const uint8_t P9N2_MCS_PORT13_MCPERF2_EN_ALT_ECR_NO_ERR = 60 ; static const uint8_t P9N2_MCS_PORT13_MCPERF2_EN_ALT_ECR_ERR = 61 ; static const uint8_t P9N2_MCS_PORT13_MCPERF2_EN_ALT_CR = 62 ; static const uint8_t P9N2_MCS_PORT13_MCPERF2_LOAD_RSVD_VALUES = 63 ; static const uint8_t P9N2_MCS_PORT02_MCPERF3_EN_DROP_PLS_F_FULL = 0 ; static const uint8_t P9N2_MCS_PORT02_MCPERF3_DIS_DROPABLE_HP = 1 ; static const uint8_t P9N2_MCS_PORT02_MCPERF3_EN_PF_CONF_RETRY = 2 ; static const uint8_t P9N2_MCS_PORT02_MCPERF3_DROP_PLS_DIV00 = 3 ; static const uint8_t P9N2_MCS_PORT02_MCPERF3_DROP_PLS_DIV00_LEN = 3 ; static const uint8_t P9N2_MCS_PORT02_MCPERF3_DROP_PLS_DIV01 = 6 ; static const uint8_t P9N2_MCS_PORT02_MCPERF3_DROP_PLS_DIV01_LEN = 3 ; static const uint8_t P9N2_MCS_PORT02_MCPERF3_DROP_PLS_DIV10 = 9 ; static const uint8_t P9N2_MCS_PORT02_MCPERF3_DROP_PLS_DIV10_LEN = 3 ; static const uint8_t P9N2_MCS_PORT02_MCPERF3_DROP_PLS_DIV11 = 12 ; static const uint8_t P9N2_MCS_PORT02_MCPERF3_DROP_PLS_DIV11_LEN = 3 ; static const uint8_t P9N2_MCS_PORT02_MCPERF3_PF_CONF_RETRY_THRESH0 = 15 ; static const uint8_t P9N2_MCS_PORT02_MCPERF3_PF_CONF_RETRY_THRESH0_LEN = 4 ; static const uint8_t P9N2_MCS_PORT02_MCPERF3_PF_CONF_RETRY_THRESH1 = 19 ; static const uint8_t P9N2_MCS_PORT02_MCPERF3_PF_CONF_RETRY_THRESH1_LEN = 4 ; static const uint8_t P9N2_MCS_PORT02_MCPERF3_PF_CONF_RETRY_THRESH2 = 23 ; static const uint8_t P9N2_MCS_PORT02_MCPERF3_PF_CONF_RETRY_THRESH2_LEN = 4 ; static const uint8_t P9N2_MCS_PORT02_MCPERF3_PF_CONF_RETRY_THRESH3 = 27 ; static const uint8_t P9N2_MCS_PORT02_MCPERF3_PF_CONF_RETRY_THRESH3_LEN = 4 ; static const uint8_t P9N2_MCS_PORT02_MCPERF3_ENABLE_CL0 = 31 ; static const uint8_t P9N2_MCS_PORT02_MCPERF3_EN_NS_RD_DYN_64B = 32 ; static const uint8_t P9N2_MCS_PORT02_MCPERF3_EN_NS_RD_DYN_INV = 33 ; static const uint8_t P9N2_MCS_PORT02_MCPERF3_PF_DROP_IF_CNT = 34 ; static const uint8_t P9N2_MCS_PORT02_MCPERF3_PF_DROP_IF_CNT_LEN = 3 ; static const uint8_t P9N2_MCS_PORT02_MCPERF3_HP_PF_EQ_LP_RD = 37 ; static const uint8_t P9N2_MCS_PORT02_MCPERF3_LP_PF_EQ_LP_RD = 38 ; static const uint8_t P9N2_MCS_PORT02_MCPERF3_ENABLE_CRESP_STALL = 39 ; static const uint8_t P9N2_MCS_PORT02_MCPERF3_ENABLE_RMW_BUF_DEALLOC_STALL = 40 ; static const uint8_t P9N2_MCS_PORT02_MCPERF3_ENABLE_AMO_MSI_RMW_ONLY = 41 ; static const uint8_t P9N2_MCS_PORT02_MCPERF3_DISABLE_READ_HIT_AMO_WINDOW = 42 ; static const uint8_t P9N2_MCS_PORT02_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY = 43 ; static const uint8_t P9N2_MCS_PORT02_MCPERF3_DISABLE_WRTO_IG = 44 ; static const uint8_t P9N2_MCS_PORT02_MCPERF3_AMO_LIMIT_SEL = 45 ; static const uint8_t P9N2_MCS_PORT02_MCPERF3_RESERVED_46_47 = 46 ; static const uint8_t P9N2_MCS_PORT02_MCPERF3_RESERVED_46_47_LEN = 2 ; static const uint8_t P9N2_MCS_PORT13_MCPERF3_EN_DROP_PLS_F_FULL = 0 ; static const uint8_t P9N2_MCS_PORT13_MCPERF3_DIS_DROPABLE_HP = 1 ; static const uint8_t P9N2_MCS_PORT13_MCPERF3_EN_PF_CONF_RETRY = 2 ; static const uint8_t P9N2_MCS_PORT13_MCPERF3_DROP_PLS_DIV00 = 3 ; static const uint8_t P9N2_MCS_PORT13_MCPERF3_DROP_PLS_DIV00_LEN = 3 ; static const uint8_t P9N2_MCS_PORT13_MCPERF3_DROP_PLS_DIV01 = 6 ; static const uint8_t P9N2_MCS_PORT13_MCPERF3_DROP_PLS_DIV01_LEN = 3 ; static const uint8_t P9N2_MCS_PORT13_MCPERF3_DROP_PLS_DIV10 = 9 ; static const uint8_t P9N2_MCS_PORT13_MCPERF3_DROP_PLS_DIV10_LEN = 3 ; static const uint8_t P9N2_MCS_PORT13_MCPERF3_DROP_PLS_DIV11 = 12 ; static const uint8_t P9N2_MCS_PORT13_MCPERF3_DROP_PLS_DIV11_LEN = 3 ; static const uint8_t P9N2_MCS_PORT13_MCPERF3_PF_CONF_RETRY_THRESH0 = 15 ; static const uint8_t P9N2_MCS_PORT13_MCPERF3_PF_CONF_RETRY_THRESH0_LEN = 4 ; static const uint8_t P9N2_MCS_PORT13_MCPERF3_PF_CONF_RETRY_THRESH1 = 19 ; static const uint8_t P9N2_MCS_PORT13_MCPERF3_PF_CONF_RETRY_THRESH1_LEN = 4 ; static const uint8_t P9N2_MCS_PORT13_MCPERF3_PF_CONF_RETRY_THRESH2 = 23 ; static const uint8_t P9N2_MCS_PORT13_MCPERF3_PF_CONF_RETRY_THRESH2_LEN = 4 ; static const uint8_t P9N2_MCS_PORT13_MCPERF3_PF_CONF_RETRY_THRESH3 = 27 ; static const uint8_t P9N2_MCS_PORT13_MCPERF3_PF_CONF_RETRY_THRESH3_LEN = 4 ; static const uint8_t P9N2_MCS_PORT13_MCPERF3_ENABLE_CL0 = 31 ; static const uint8_t P9N2_MCS_PORT13_MCPERF3_EN_NS_RD_DYN_64B = 32 ; static const uint8_t P9N2_MCS_PORT13_MCPERF3_EN_NS_RD_DYN_INV = 33 ; static const uint8_t P9N2_MCS_PORT13_MCPERF3_PF_DROP_IF_CNT = 34 ; static const uint8_t P9N2_MCS_PORT13_MCPERF3_PF_DROP_IF_CNT_LEN = 3 ; static const uint8_t P9N2_MCS_PORT13_MCPERF3_HP_PF_EQ_LP_RD = 37 ; static const uint8_t P9N2_MCS_PORT13_MCPERF3_LP_PF_EQ_LP_RD = 38 ; static const uint8_t P9N2_MCS_PORT13_MCPERF3_ENABLE_CRESP_STALL = 39 ; static const uint8_t P9N2_MCS_PORT13_MCPERF3_ENABLE_RMW_BUF_DEALLOC_STALL = 40 ; static const uint8_t P9N2_MCS_PORT13_MCPERF3_ENABLE_AMO_MSI_RMW_ONLY = 41 ; static const uint8_t P9N2_MCS_PORT13_MCPERF3_DISABLE_READ_HIT_AMO_WINDOW = 42 ; static const uint8_t P9N2_MCS_PORT13_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY = 43 ; static const uint8_t P9N2_MCS_PORT13_MCPERF3_DISABLE_WRTO_IG = 44 ; static const uint8_t P9N2_MCS_PORT13_MCPERF3_AMO_LIMIT_SEL = 45 ; static const uint8_t P9N2_MCS_PORT13_MCPERF3_RESERVED_46_47 = 46 ; static const uint8_t P9N2_MCS_PORT13_MCPERF3_RESERVED_46_47_LEN = 2 ; static const uint8_t P9N2_MCS_MCSYNC_CHANNEL_SELECT = 0 ; static const uint8_t P9N2_MCS_MCSYNC_CHANNEL_SELECT_LEN = 8 ; static const uint8_t P9N2_MCS_MCSYNC_SYNC_TYPE = 8 ; static const uint8_t P9N2_MCS_MCSYNC_SYNC_TYPE_LEN = 8 ; static const uint8_t P9N2_MCS_MCSYNC_SYNC_GO = 16 ; static const uint8_t P9N2_MCS_MCSYNC_SYNC_RESERVED = 17 ; static const uint8_t P9N2_MCS_MCSYNC_SYNC_RESERVED_LEN = 11 ; static const uint8_t P9N2_MCS_MCTEST_INJECT_MODE_SELECT = 0 ; static const uint8_t P9N2_MCS_MCTEST_RESERVED_1 = 1 ; static const uint8_t P9N2_MCS_MCTEST_CONTINUOUS_LEVEL_INJECT_ENABLE = 2 ; static const uint8_t P9N2_MCS_MCTEST_RESERVED_3 = 3 ; static const uint8_t P9N2_MCS_MCTEST_EVENT_0_WAT_DISABLE_ALL_SPECULATION = 4 ; static const uint8_t P9N2_MCS_MCTEST_EVENT_1_WAT_DISABLE_ALL_SPECULATION = 5 ; static const uint8_t P9N2_MCS_MCTEST_EVENT_2_WAT_DISABLE_ALL_SPECULATION = 6 ; static const uint8_t P9N2_MCS_MCTEST_EVENT_3_WAT_DISABLE_ALL_SPECULATION = 7 ; static const uint8_t P9N2_MCS_MCTEST_EVENT_0_WAT_DISABLE_READ_BYPASS = 8 ; static const uint8_t P9N2_MCS_MCTEST_EVENT_1_WAT_DISABLE_READ_BYPASS = 9 ; static const uint8_t P9N2_MCS_MCTEST_EVENT_2_WAT_DISABLE_READ_BYPASS = 10 ; static const uint8_t P9N2_MCS_MCTEST_EVENT_3_WAT_DISABLE_READ_BYPASS = 11 ; static const uint8_t P9N2_MCS_MCTEST_EVENT_0_WAT_DISABLE_PREFETCH = 12 ; static const uint8_t P9N2_MCS_MCTEST_EVENT_1_WAT_DISABLE_PREFETCH = 13 ; static const uint8_t P9N2_MCS_MCTEST_EVENT_2_WAT_DISABLE_PREFETCH = 14 ; static const uint8_t P9N2_MCS_MCTEST_EVENT_3_WAT_DISABLE_PREFETCH = 15 ; static const uint8_t P9N2_MCS_MCTEST_EVENT_0_WAT_DISABLE_FASTPATH = 16 ; static const uint8_t P9N2_MCS_MCTEST_EVENT_1_WAT_DISABLE_FASTPATH = 17 ; static const uint8_t P9N2_MCS_MCTEST_EVENT_2_WAT_DISABLE_FASTPATH = 18 ; static const uint8_t P9N2_MCS_MCTEST_EVENT_3_WAT_DISABLE_FASTPATH = 19 ; static const uint8_t P9N2_MCS_MCTEST_EVENT_0_WAT_FORCE_SFSTAT = 20 ; static const uint8_t P9N2_MCS_MCTEST_EVENT_1_WAT_FORCE_SFSTAT = 21 ; static const uint8_t P9N2_MCS_MCTEST_EVENT_2_WAT_FORCE_SFSTAT = 22 ; static const uint8_t P9N2_MCS_MCTEST_EVENT_3_WAT_FORCE_SFSTAT = 23 ; static const uint8_t P9N2_MCS_MCTEST_EVENT_0_WAT_FORCE_MDI1 = 24 ; static const uint8_t P9N2_MCS_MCTEST_EVENT_1_WAT_FORCE_MDI1 = 25 ; static const uint8_t P9N2_MCS_MCTEST_EVENT_2_WAT_FORCE_MDI1 = 26 ; static const uint8_t P9N2_MCS_MCTEST_EVENT_3_WAT_FORCE_MDI1 = 27 ; static const uint8_t P9N2_MCS_MCTEST_RESERVED_28_31 = 28 ; static const uint8_t P9N2_MCS_MCTEST_RESERVED_28_31_LEN = 4 ; static const uint8_t P9N2_MCS_MCTEST_CONFIGURE_RCTRL_WAT_SELECT = 32 ; static const uint8_t P9N2_MCS_MCTEST_CONFIGURE_RCTRL_WAT_SELECT_LEN = 4 ; static const uint8_t P9N2_MCS_MCTEST_RESERVED_36_47 = 36 ; static const uint8_t P9N2_MCS_MCTEST_RESERVED_36_47_LEN = 12 ; static const uint8_t P9N2_MCS_MCTO_SELECT_PB_HANG_PULSE = 0 ; static const uint8_t P9N2_MCS_MCTO_SELECT_LOCAL_HANG_PULSE = 1 ; static const uint8_t P9N2_MCS_MCTO_RPT_HANG_SELECT = 2 ; static const uint8_t P9N2_MCS_MCTO_RPT_HANG_SELECT_LEN = 2 ; static const uint8_t P9N2_MCS_MCTO_RESERVED_4 = 4 ; static const uint8_t P9N2_MCS_MCTO_CL_TIMEOUT_VALUE = 5 ; static const uint8_t P9N2_MCS_MCTO_CL_TIMEOUT_VALUE_LEN = 3 ; static const uint8_t P9N2_MCS_MCTO_LOCAL_HANG_COMP = 8 ; static const uint8_t P9N2_MCS_MCTO_LOCAL_HANG_COMP_LEN = 16 ; static const uint8_t P9N2_MCS_MCTO_HANG_COMP = 24 ; static const uint8_t P9N2_MCS_MCTO_HANG_COMP_LEN = 8 ; static const uint8_t P9N2_MCS_MCTO_ENABLE_NONMIRROR_HANG = 32 ; static const uint8_t P9N2_MCS_MCTO_ENABLE_MIRROR_HANG = 33 ; static const uint8_t P9N2_MCS_MCTO_ENABLE_APO_HANG = 34 ; static const uint8_t P9N2_MCS_MCTO_ENABLE_CLIB_HANG = 35 ; static const uint8_t P9N2_MCS_PORT02_MCWAT_WAT_STALL_ACTION = 0 ; static const uint8_t P9N2_MCS_PORT02_MCWAT_WAT_STALL_ACTION_LEN = 4 ; static const uint8_t P9N2_MCS_PORT02_MCWAT_CL_WRAP_DEBUG_OR = 4 ; static const uint8_t P9N2_MCS_PORT02_MCWAT_CLSTATE_DEBUG_SEL = 5 ; static const uint8_t P9N2_MCS_PORT02_MCWAT_CLSTATE_DEBUG_SEL_LEN = 3 ; static const uint8_t P9N2_MCS_PORT02_MCWAT_RESERVED8_9 = 8 ; static const uint8_t P9N2_MCS_PORT02_MCWAT_RESERVED8_9_LEN = 2 ; static const uint8_t P9N2_MCS_PORT02_MCWAT_DISP_DEBUG_SEL = 10 ; static const uint8_t P9N2_MCS_PORT02_MCWAT_DISP_DEBUG_SEL_LEN = 2 ; static const uint8_t P9N2_MCS_PORT02_MCWAT_CL_WRAP_DEBUG_SEL = 12 ; static const uint8_t P9N2_MCS_PORT02_MCWAT_CL_WRAP_DEBUG_SEL_LEN = 5 ; static const uint8_t P9N2_MCS_PORT02_MCWAT_WAT_ACTION_SEL = 17 ; static const uint8_t P9N2_MCS_PORT02_MCWAT_WAT_ACTION_SEL_LEN = 5 ; static const uint8_t P9N2_MCS_PORT02_MCWAT_RESERVED22_31 = 22 ; static const uint8_t P9N2_MCS_PORT02_MCWAT_RESERVED22_31_LEN = 10 ; static const uint8_t P9N2_MCS_PORT13_MCWAT_WAT_STALL_ACTION = 0 ; static const uint8_t P9N2_MCS_PORT13_MCWAT_WAT_STALL_ACTION_LEN = 4 ; static const uint8_t P9N2_MCS_PORT13_MCWAT_CL_WRAP_DEBUG_OR = 4 ; static const uint8_t P9N2_MCS_PORT13_MCWAT_CLSTATE_DEBUG_SEL = 5 ; static const uint8_t P9N2_MCS_PORT13_MCWAT_CLSTATE_DEBUG_SEL_LEN = 3 ; static const uint8_t P9N2_MCS_PORT13_MCWAT_RESERVED8_9 = 8 ; static const uint8_t P9N2_MCS_PORT13_MCWAT_RESERVED8_9_LEN = 2 ; static const uint8_t P9N2_MCS_PORT13_MCWAT_DISP_DEBUG_SEL = 10 ; static const uint8_t P9N2_MCS_PORT13_MCWAT_DISP_DEBUG_SEL_LEN = 2 ; static const uint8_t P9N2_MCS_PORT13_MCWAT_CL_WRAP_DEBUG_SEL = 12 ; static const uint8_t P9N2_MCS_PORT13_MCWAT_CL_WRAP_DEBUG_SEL_LEN = 5 ; static const uint8_t P9N2_MCS_PORT13_MCWAT_WAT_ACTION_SEL = 17 ; static const uint8_t P9N2_MCS_PORT13_MCWAT_WAT_ACTION_SEL_LEN = 5 ; static const uint8_t P9N2_MCS_PORT13_MCWAT_RESERVED22_31 = 22 ; static const uint8_t P9N2_MCS_PORT13_MCWAT_RESERVED22_31_LEN = 10 ; static const uint8_t P9N2_MCS_MCWATCNTL_ENABLE_WAT = 0 ; static const uint8_t P9N2_MCS_MCWATCNTL_SET_WAT_EXTERNAL_ARM = 1 ; static const uint8_t P9N2_MCS_MCWATCNTL_SET_WAT_EXTERNAL_RESET = 2 ; static const uint8_t P9N2_MCS_MCWATCNTL_SET_WAT_EXTERNAL_TRIGGER = 3 ; static const uint8_t P9N2_MCS_MCWATCNTL_MCWATDATAX_SELECT = 4 ; static const uint8_t P9N2_MCS_MCWATCNTL_MCWATDATAX_SELECT_LEN = 4 ; static const uint8_t P9N2_MCS_MCWATCNTL_WAT_EVENT_SELECT = 8 ; static const uint8_t P9N2_MCS_MCWATCNTL_WAT_EVENT_SELECT_LEN = 2 ; static const uint8_t P9N2_MCS_MCWATCNTL_WAT_EXTERNAL_SELECT = 10 ; static const uint8_t P9N2_MCS_MCWATCNTL_WAT_EXTERNAL_SELECT_LEN = 2 ; static const uint8_t P9N2_MCS_MCWATCNTL_WAT_LOCAL_EVENT_SELECT = 12 ; static const uint8_t P9N2_MCS_MCWATCNTL_WAT_LOCAL_EVENT_SELECT_LEN = 2 ; static const uint8_t P9N2_MCS_MCWATCNTL_WAT_EXTERNAL_EVENT_TO_INTERNAL = 14 ; static const uint8_t P9N2_MCS_MCWATCNTL_WAT_EXTERNAL_EVENT_TO_INTERNAL_LEN = 2 ; static const uint8_t P9N2_MCS_MCWATCNTL_WAT_GLOBAL_EVENT_0_SELECT = 16 ; static const uint8_t P9N2_MCS_MCWATCNTL_WAT_GLOBAL_EVENT_0_SELECT_LEN = 3 ; static const uint8_t P9N2_MCS_MCWATCNTL_WAT_GLOBAL_EVENT_1_SELECT = 19 ; static const uint8_t P9N2_MCS_MCWATCNTL_WAT_GLOBAL_EVENT_1_SELECT_LEN = 3 ; static const uint8_t P9N2_MCS_MCWATCNTL_WAT_GLOBAL_EVENT_2_SELECT = 22 ; static const uint8_t P9N2_MCS_MCWATCNTL_WAT_GLOBAL_EVENT_2_SELECT_LEN = 3 ; static const uint8_t P9N2_MCS_MCWATCNTL_WAT_GLOBAL_EVENT_3_SELECT = 25 ; static const uint8_t P9N2_MCS_MCWATCNTL_WAT_GLOBAL_EVENT_3_SELECT_LEN = 3 ; static const uint8_t P9N2_MCS_MCWATCNTL_RESERVED_28_31 = 28 ; static const uint8_t P9N2_MCS_MCWATCNTL_RESERVED_28_31_LEN = 4 ; static const uint8_t P9N2_MCS_MCWATCNTL_PBI_DEBUG_SELECT = 32 ; static const uint8_t P9N2_MCS_MCWATCNTL_PBI_DEBUG_SELECT_LEN = 4 ; static const uint8_t P9N2_MCS_MCWATCNTL_RCTRL_DEBUG_SELECT = 36 ; static const uint8_t P9N2_MCS_MCWATCNTL_RCTRL_DEBUG_SELECT_LEN = 4 ; static const uint8_t P9N2_MCS_MCWATCNTL_DBG_COUNT_DEBUG_SELECT = 40 ; static const uint8_t P9N2_MCS_MCWATCNTL_DBG_COUNT_DEBUG_SELECT_LEN = 7 ; static const uint8_t P9N2_MCS_MCWATCNTL_DBG_COUNT_EVENT_BUS_SELECT = 47 ; static const uint8_t P9N2_MCS_MCWATCNTL_DBG_COUNT_EVENT_BUS_SELECT_LEN = 5 ; static const uint8_t P9N2_MCS_MCWATCNTL_DBG_COUNT_SELECT = 52 ; static const uint8_t P9N2_MCS_MCWATCNTL_DBG_COUNT_SELECT_LEN = 4 ; static const uint8_t P9N2_MCS_MCWATCNTL_RESERVED_56_59 = 56 ; static const uint8_t P9N2_MCS_MCWATCNTL_RESERVED_56_59_LEN = 4 ; static const uint8_t P9N2_MCS_MCWATCNTL_DBG_COUNT_ENABLE = 60 ; static const uint8_t P9N2_MCS_MCWATCNTL_DBG_COUNT_RESET = 61 ; static const uint8_t P9N2_MCS_MCWATCNTL_AND_22BIT_WAT_OUTPUTS = 62 ; static const uint8_t P9N2_MCS_MCWATCNTL_RESERVED_63 = 63 ; static const uint8_t P9N2_MCS_MCWATDATA_MCWATDATA0 = 0 ; static const uint8_t P9N2_MCS_MCWATDATA_MCWATDATA0_LEN = 40 ; static const uint8_t P9N2_MCA_MSR_CHIPMARK = 8 ; static const uint8_t P9N2_MCA_MSR_CHIPMARK_LEN = 8 ; static const uint8_t P9N2_MCA_MSR_RANK = 16 ; static const uint8_t P9N2_MCA_MSR_RANK_LEN = 3 ; static const uint8_t P9N2_MCA_PSCOM_ERROR_MASK_PCB_WDATA_PARITY = 0 ; static const uint8_t P9N2_MCA_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY = 1 ; static const uint8_t P9N2_MCA_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY = 2 ; static const uint8_t P9N2_MCA_PSCOM_ERROR_MASK_DL_RETURN_P0 = 3 ; static const uint8_t P9N2_MCA_PSCOM_ERROR_MASK_UL_RDATA_PARITY = 4 ; static const uint8_t P9N2_MCA_PSCOM_ERROR_MASK_UL_P0 = 5 ; static const uint8_t P9N2_MCA_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE = 6 ; static const uint8_t P9N2_MCA_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE = 7 ; static const uint8_t P9N2_MCA_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 8 ; static const uint8_t P9N2_MCA_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9 ; static const uint8_t P9N2_MCA_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 10 ; static const uint8_t P9N2_MCA_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD = 11 ; static const uint8_t P9N2_MCA_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD = 12 ; static const uint8_t P9N2_MCA_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID = 13 ; static const uint8_t P9N2_MCA_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY = 14 ; static const uint8_t P9N2_MCA_PSCOM_ERROR_MASK_GENERAL_TIMEOUT = 15 ; static const uint8_t P9N2_MCA_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16 ; static const uint8_t P9N2_MCA_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17 ; static const uint8_t P9N2_MCA_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR = 0 ; static const uint8_t P9N2_MCA_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR = 1 ; static const uint8_t P9N2_MCA_PSCOM_MODE_REG_UNUSED_BIT_2 = 2 ; static const uint8_t P9N2_MCA_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR = 3 ; static const uint8_t P9N2_MCA_PSCOM_MODE_REG_WATCHDOG_ENABLE = 4 ; static const uint8_t P9N2_MCA_PSCOM_MODE_REG_SCOM_HANG_LIMIT = 5 ; static const uint8_t P9N2_MCA_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN = 2 ; static const uint8_t P9N2_MCA_PSCOM_MODE_REG_FORCE_ALL_RINGS = 7 ; static const uint8_t P9N2_MCA_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE = 8 ; static const uint8_t P9N2_MCA_PSCOM_MODE_REG_RESERVED_LT = 9 ; static const uint8_t P9N2_MCA_PSCOM_MODE_REG_RESERVED_LT_LEN = 3 ; static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY = 0 ; static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY = 1 ; static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY = 2 ; static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0 = 3 ; static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY = 4 ; static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0 = 5 ; static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE = 6 ; static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE = 7 ; static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 8 ; static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9 ; static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 10 ; static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD = 11 ; static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD = 12 ; static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID = 13 ; static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY = 14 ; static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT = 15 ; static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16 ; static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17 ; static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY = 18 ; static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY = 19 ; static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY = 20 ; static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0 = 21 ; static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY = 22 ; static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0 = 23 ; static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE = 24 ; static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE = 25 ; static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 26 ; static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 27 ; static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 28 ; static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD = 29 ; static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD = 30 ; static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID = 31 ; static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY = 32 ; static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT = 33 ; static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 34 ; static const uint8_t P9N2_MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 35 ; static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM = 0 ; static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_LEN = 4 ; static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD1 = 4 ; static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD1_LEN = 4 ; static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD2 = 8 ; static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD2_LEN = 4 ; static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD3 = 12 ; static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD3_LEN = 4 ; static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD4 = 16 ; static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD4_LEN = 4 ; static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD5 = 20 ; static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD5_LEN = 4 ; static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD6 = 24 ; static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD6_LEN = 4 ; static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD7 = 28 ; static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD7_LEN = 4 ; static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD8 = 32 ; static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD8_LEN = 4 ; static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD9 = 36 ; static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD9_LEN = 4 ; static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD10 = 40 ; static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD10_LEN = 4 ; static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD11 = 44 ; static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD11_LEN = 4 ; static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD12 = 48 ; static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD12_LEN = 4 ; static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD13 = 52 ; static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD13_LEN = 4 ; static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD14 = 56 ; static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD14_LEN = 4 ; static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD15 = 60 ; static const uint8_t P9N2_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD15_LEN = 4 ; static const uint8_t P9N2_MCA_RECR_MBSECCQ_DISABLE_MEMORY_ECC_CHECK_CORRECT = 0 ; static const uint8_t P9N2_MCA_RECR_MBSECCQ_DISABLE_MEMORY_ECC_CORRECT = 1 ; static const uint8_t P9N2_MCA_RECR_MBSECCQ_DISABLE_MARK_STORE_WRITE = 2 ; static const uint8_t P9N2_MCA_RECR_MBSECCQ_DISABLE_UE_RETRY = 3 ; static const uint8_t P9N2_MCA_RECR_MBSECCQ_ITAG_METADATA_ENABLE = 4 ; static const uint8_t P9N2_MCA_RECR_MBSECCQ_SLOW_EXIT_REDUCTION = 5 ; static const uint8_t P9N2_MCA_RECR_MBSECCQ_READ_POINTER_DELAY = 6 ; static const uint8_t P9N2_MCA_RECR_MBSECCQ_READ_POINTER_DELAY_LEN = 3 ; static const uint8_t P9N2_MCA_RECR_MBSECCQ_EXIT_OVERRIDE = 9 ; static const uint8_t P9N2_MCA_RECR_MBSECCQ_EXIT_OVERRIDE_LEN = 2 ; static const uint8_t P9N2_MCA_RECR_MBSECCQ_HWMARK_EXIT1 = 11 ; static const uint8_t P9N2_MCA_RECR_MBSECCQ_DATA_GENERATOR_OVERRIDE = 12 ; static const uint8_t P9N2_MCA_RECR_MBSECCQ_ECC_SCHEDULER_DELAY = 13 ; static const uint8_t P9N2_MCA_RECR_MBSECCQ_ECC_SCHEDULER_DELAY_LEN = 3 ; static const uint8_t P9N2_MCA_RECR_MBSECCQ_VAL_TO_DATA_DELAY = 16 ; static const uint8_t P9N2_MCA_RECR_MBSECCQ_VAL_TO_DATA_DELAY_LEN = 3 ; static const uint8_t P9N2_MCA_RECR_MBSECCQ_DELAY_VALID_1X = 19 ; static const uint8_t P9N2_MCA_RECR_MBSECCQ_NEST_VAL_TO_DATA_DELAY = 20 ; static const uint8_t P9N2_MCA_RECR_MBSECCQ_NEST_VAL_TO_DATA_DELAY_LEN = 2 ; static const uint8_t P9N2_MCA_RECR_MBSECCQ_DELAY_NONBYPASS = 22 ; static const uint8_t P9N2_MCA_RECR_MBSECCQ_ENABLE_SPECIAL_ATTENTION = 23 ; static const uint8_t P9N2_MCA_RECR_MBSECCQ_ENABLE_HOST_ATTENTION = 24 ; static const uint8_t P9N2_MCA_RECR_MBSECCQ_DISABLE_MPE_CONFIRM = 25 ; static const uint8_t P9N2_MCA_RECR_MBSECCQ_ENABLE_UE_NOISE_WINDOW = 26 ; static const uint8_t P9N2_MCA_RECR_MBSECCQ_ENABLE_TCE_CORRECTION = 27 ; static const uint8_t P9N2_MCA_RECR_MBSECCQ_ENABLE_CHIPMARKED_SCE_NCE = 28 ; static const uint8_t P9N2_MCA_RECR_MBSECCQ_USE_ADDRESS_HASH = 29 ; static const uint8_t P9N2_MCA_RECR_MBSECCQ_DATA_INVERSION = 30 ; static const uint8_t P9N2_MCA_RECR_MBSECCQ_DATA_INVERSION_LEN = 2 ; static const uint8_t P9N2_MCA_RECR_MBSECCQ_DISABLE_PIPE_NOERR_CLOCK_GATING = 32 ; static const uint8_t P9N2_MCA_RECR_MBSECCQ_MAINT_NO_RETRY_UE = 33 ; static const uint8_t P9N2_MCA_RECR_MBSECCQ_MAINT_NO_RETRY_MPE = 34 ; static const uint8_t P9N2_MCA_RECR_MBSECCQ_DISABLE_BYPASS_TEMPLATE_A = 35 ; static const uint8_t P9N2_MCA_RECR_HW372042_MARKS_ACT_EMPTY_IF_PERR_FIX_DISABLE = 36 ; static const uint8_t P9N2_MCA_RECR_HW365909_NOCONFIRM_REDUNDANT_FIR_FIX_DISABLE = 37 ; static const uint8_t P9N2_MCA_RECR_HW365926_FORCE_EXIT2_FIX_DISABLE = 38 ; static const uint8_t P9N2_MCA_RECR_MBSECCQ_ENABLE_BYPASS_MARK_PLACE = 39 ; static const uint8_t P9N2_MCA_RECR_MBSECCQ_BYPASS_TENURE_3 = 40 ; static const uint8_t P9N2_MCA_RECR_MBSECCQ_RESERVED_41_47 = 41 ; static const uint8_t P9N2_MCA_RECR_MBSECCQ_RESERVED_41_47_LEN = 7 ; static const uint8_t P9N2_MCA_RING_FENCE_MASK_LATCH_REG_ENABLE = 1 ; static const uint8_t P9N2_MCA_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN = 15 ; static const uint8_t P9N2_MCBIST_RUNTIMECTRQ_CFG_RUNTIME_CTR = 0 ; static const uint8_t P9N2_MCBIST_RUNTIMECTRQ_CFG_RUNTIME_CTR_LEN = 37 ; static const uint8_t P9N2_MCA_TRACE_HI_DATA_REG_DATA = 0 ; static const uint8_t P9N2_MCA_TRACE_HI_DATA_REG_DATA_LEN = 64 ; static const uint8_t P9N2_MCA_TRACE_LO_DATA_REG_DATA = 0 ; static const uint8_t P9N2_MCA_TRACE_LO_DATA_REG_DATA_LEN = 32 ; static const uint8_t P9N2_MCA_TRACE_LO_DATA_REG_ADDRESS = 32 ; static const uint8_t P9N2_MCA_TRACE_LO_DATA_REG_ADDRESS_LEN = 10 ; static const uint8_t P9N2_MCA_TRACE_LO_DATA_REG_LAST_BANK = 42 ; static const uint8_t P9N2_MCA_TRACE_LO_DATA_REG_LAST_BANK_LEN = 9 ; static const uint8_t P9N2_MCA_TRACE_LO_DATA_REG_LAST_BANK_VALID = 51 ; static const uint8_t P9N2_MCA_TRACE_LO_DATA_REG_WRITE_ON_RUN = 52 ; static const uint8_t P9N2_MCA_TRACE_LO_DATA_REG_RUNNING = 53 ; static const uint8_t P9N2_MCA_TRACE_LO_DATA_REG_HOLD_ADDRESS = 54 ; static const uint8_t P9N2_MCA_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN = 10 ; static const uint8_t P9N2_MCA_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE = 0 ; static const uint8_t P9N2_MCA_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE = 1 ; static const uint8_t P9N2_MCA_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE = 2 ; static const uint8_t P9N2_MCA_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN = 8 ; static const uint8_t P9N2_MCA_TRACE_TRCTRL_CONFIG_BANK_MODE = 10 ; static const uint8_t P9N2_MCA_TRACE_TRCTRL_CONFIG_ENH_MODE = 11 ; static const uint8_t P9N2_MCA_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL = 12 ; static const uint8_t P9N2_MCA_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN = 2 ; static const uint8_t P9N2_MCA_TRACE_TRCTRL_CONFIG_SELECT_CONTROL = 14 ; static const uint8_t P9N2_MCA_TRACE_TRCTRL_CONFIG_SELECT_CONTROL_LEN = 4 ; static const uint8_t P9N2_MCA_TRACE_TRCTRL_CONFIG_RUN_HOLD_OFF = 18 ; static const uint8_t P9N2_MCA_TRACE_TRCTRL_CONFIG_RUN_STATUS = 19 ; static const uint8_t P9N2_MCA_TRACE_TRCTRL_CONFIG_RUN_STICKY = 20 ; static const uint8_t P9N2_MCA_TRACE_TRCTRL_CONFIG_DISABLE_BANK_EDGE_DETECT = 21 ; static const uint8_t P9N2_MCA_TRACE_TRCTRL_CONFIG_CONTROL_UNUSED = 22 ; static const uint8_t P9N2_MCA_TRACE_TRCTRL_CONFIG_CONTROL_UNUSED_LEN = 6 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 = 0 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN = 64 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 = 0 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN = 24 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_2_PATTERNA = 0 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN = 24 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_2_PATTERNB = 24 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN = 24 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_3_PATTERNC = 0 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN = 24 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_3_PATTERND = 24 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_3_PATTERND_LEN = 24 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_4_MASKA = 0 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_4_MASKA_LEN = 24 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_4_MASKB = 24 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_4_MASKB_LEN = 24 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_5_MASKC = 0 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_5_MASKC_LEN = 24 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_5_MASKD = 24 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_5_MASKD_LEN = 24 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION = 0 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK = 1 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL = 2 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN = 2 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL = 4 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN = 2 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL = 6 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN = 2 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL = 8 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN = 2 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK = 10 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN = 4 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK = 14 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN = 4 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK = 18 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN = 4 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK = 22 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN = 4 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE = 26 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE = 27 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE = 28 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN = 4 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_ERROR_CMP_MASK = 32 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_ERROR_CMP_PATTERN = 33 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_TRIG0_ERR_CMP = 34 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_TRIG1_ERR_CMP = 35 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES = 36 ; static const uint8_t P9N2_MCA_TRACE_TRDATA_CONFIG_9_SPARE_LT = 37 ; static const uint8_t P9N2_MCBIST_WATCFG0AQ_CFG_WAT_EVENT_SEL = 0 ; static const uint8_t P9N2_MCBIST_WATCFG0AQ_CFG_WAT_EVENT_SEL_LEN = 48 ; static const uint8_t P9N2_MCBIST_WATCFG0BQ_CFG_WAT_MSKA = 0 ; static const uint8_t P9N2_MCBIST_WATCFG0BQ_CFG_WAT_MSKA_LEN = 44 ; static const uint8_t P9N2_MCBIST_WATCFG0BQ_CFG_WAT_CNTL = 44 ; static const uint8_t P9N2_MCBIST_WATCFG0BQ_CFG_WAT_CNTL_LEN = 17 ; static const uint8_t P9N2_MCBIST_WATCFG0CQ_CFG_WAT_MSKB = 0 ; static const uint8_t P9N2_MCBIST_WATCFG0CQ_CFG_WAT_MSKB_LEN = 44 ; static const uint8_t P9N2_MCBIST_WATCFG0DQ_CFG_WAT_PATA = 0 ; static const uint8_t P9N2_MCBIST_WATCFG0DQ_CFG_WAT_PATA_LEN = 44 ; static const uint8_t P9N2_MCBIST_WATCFG0EQ_CFG_WAT_PATB = 0 ; static const uint8_t P9N2_MCBIST_WATCFG0EQ_CFG_WAT_PATB_LEN = 44 ; static const uint8_t P9N2_MCBIST_WATCFG1AQ_CFG_WAT_EVENT_SEL = 0 ; static const uint8_t P9N2_MCBIST_WATCFG1AQ_CFG_WAT_EVENT_SEL_LEN = 48 ; static const uint8_t P9N2_MCBIST_WATCFG1BQ_CFG_WAT_MSKA = 0 ; static const uint8_t P9N2_MCBIST_WATCFG1BQ_CFG_WAT_MSKA_LEN = 44 ; static const uint8_t P9N2_MCBIST_WATCFG1BQ_CFG_WAT_CNTL = 44 ; static const uint8_t P9N2_MCBIST_WATCFG1BQ_CFG_WAT_CNTL_LEN = 17 ; static const uint8_t P9N2_MCBIST_WATCFG1CQ_CFG_WAT_MSKB = 0 ; static const uint8_t P9N2_MCBIST_WATCFG1CQ_CFG_WAT_MSKB_LEN = 44 ; static const uint8_t P9N2_MCBIST_WATCFG1DQ_CFG_WAT_PATA = 0 ; static const uint8_t P9N2_MCBIST_WATCFG1DQ_CFG_WAT_PATA_LEN = 44 ; static const uint8_t P9N2_MCBIST_WATCFG1EQ_CFG_WAT_PATB = 0 ; static const uint8_t P9N2_MCBIST_WATCFG1EQ_CFG_WAT_PATB_LEN = 44 ; static const uint8_t P9N2_MCBIST_WATCFG2AQ_CFG_WAT_EVENT_SEL = 0 ; static const uint8_t P9N2_MCBIST_WATCFG2AQ_CFG_WAT_EVENT_SEL_LEN = 48 ; static const uint8_t P9N2_MCBIST_WATCFG2BQ_CFG_WAT_MSKA = 0 ; static const uint8_t P9N2_MCBIST_WATCFG2BQ_CFG_WAT_MSKA_LEN = 44 ; static const uint8_t P9N2_MCBIST_WATCFG2BQ_CFG_WAT_CNTL = 44 ; static const uint8_t P9N2_MCBIST_WATCFG2BQ_CFG_WAT_CNTL_LEN = 17 ; static const uint8_t P9N2_MCBIST_WATCFG2CQ_CFG_WAT_MSKB = 0 ; static const uint8_t P9N2_MCBIST_WATCFG2CQ_CFG_WAT_MSKB_LEN = 44 ; static const uint8_t P9N2_MCBIST_WATCFG2DQ_CFG_WAT_PATA = 0 ; static const uint8_t P9N2_MCBIST_WATCFG2DQ_CFG_WAT_PATA_LEN = 44 ; static const uint8_t P9N2_MCBIST_WATCFG2EQ_CFG_WAT_PATB = 0 ; static const uint8_t P9N2_MCBIST_WATCFG2EQ_CFG_WAT_PATB_LEN = 44 ; static const uint8_t P9N2_MCBIST_WATCFG3AQ_CFG_WAT_EVENT_SEL = 0 ; static const uint8_t P9N2_MCBIST_WATCFG3AQ_CFG_WAT_EVENT_SEL_LEN = 48 ; static const uint8_t P9N2_MCBIST_WATCFG3BQ_CFG_WAT_MSKA = 0 ; static const uint8_t P9N2_MCBIST_WATCFG3BQ_CFG_WAT_MSKA_LEN = 44 ; static const uint8_t P9N2_MCBIST_WATCFG3BQ_CFG_WAT_CNTL = 44 ; static const uint8_t P9N2_MCBIST_WATCFG3BQ_CFG_WAT_CNTL_LEN = 17 ; static const uint8_t P9N2_MCBIST_WATCFG3CQ_CFG_WAT_MSKB = 0 ; static const uint8_t P9N2_MCBIST_WATCFG3CQ_CFG_WAT_MSKB_LEN = 44 ; static const uint8_t P9N2_MCBIST_WATCFG3DQ_CFG_WAT_PATA = 0 ; static const uint8_t P9N2_MCBIST_WATCFG3DQ_CFG_WAT_PATA_LEN = 44 ; static const uint8_t P9N2_MCBIST_WATCFG3EQ_CFG_WAT_PATB = 0 ; static const uint8_t P9N2_MCBIST_WATCFG3EQ_CFG_WAT_PATB_LEN = 44 ; static const uint8_t P9N2_MCA_WBMGR_TAG_INFO_BUFFER_OVERRUN = 0 ; static const uint8_t P9N2_MCA_WBMGR_TAG_INFO_OVERRUN = 1 ; static const uint8_t P9N2_MCA_WBMGR_TAG_INFO_REL_ASYNC_PARITY_ERROR = 2 ; static const uint8_t P9N2_MCA_WBMGR_TAG_INFO_REL_ASYNC_SEQUENCE_ERROR = 3 ; static const uint8_t P9N2_MCA_WBMGR_TAG_INFO_REL_MERGE_ASYNC_PARITY_ERROR = 4 ; static const uint8_t P9N2_MCA_WBMGR_TAG_INFO_REL_MERGE_ASYNC_SEQUENCE_ERROR = 5 ; static const uint8_t P9N2_MCA_WBMGR_TAG_INFO_INFORMATION = 6 ; static const uint8_t P9N2_MCA_WBMGR_TAG_INFO_INFORMATION_LEN = 7 ; static const uint8_t P9N2_MCA_WDFCFG_CFG_WRITE_MODE_ECC_CHK_DIS = 0 ; static const uint8_t P9N2_MCA_WDFCFG_CFG_WRITE_MODE_ECC_COR_DIS = 1 ; static const uint8_t P9N2_MCA_WDFCFG_CFG_WDF_SERIAL_SEQ_MODE = 2 ; static const uint8_t P9N2_MCA_WDFCFG_RESET_KEEPER = 3 ; static const uint8_t P9N2_MCA_WDFCFG_MERGE_CAPACITY_LIMIT = 4 ; static const uint8_t P9N2_MCA_WDFCFG_MERGE_CAPACITY_LIMIT_LEN = 4 ; static const uint8_t P9N2_MCA_WDFCFG_EN_HW365559 = 8 ; static const uint8_t P9N2_MCA_WDFCFG_CFG_OVERRUN_FORCE_SUE_ENABLE = 9 ; static const uint8_t P9N2_MCA_WDFCFG_10_11_SPARE = 10 ; static const uint8_t P9N2_MCA_WDFCFG_10_11_SPARE_LEN = 2 ; static const uint8_t P9N2_MCA_WDFCFG_ASYNC_INJ = 12 ; static const uint8_t P9N2_MCA_WDFCFG_ASYNC_INJ_LEN = 6 ; static const uint8_t P9N2_MCA_WDFCFG_18_31_SPARE = 18 ; static const uint8_t P9N2_MCA_WDFCFG_18_31_SPARE_LEN = 14 ; static const uint8_t P9N2_MCA_WDFCFG_ECC_WDF_HCA_TIMEBASE_SELECT = 32 ; static const uint8_t P9N2_MCA_WDFCFG_ECC_WDF_HCA_TIMEBASE_SELECT_LEN = 4 ; static const uint8_t P9N2_MCA_WDFCFG_ECC_WDF_HCA_TIMEBASE = 36 ; static const uint8_t P9N2_MCA_WDFCFG_ECC_WDF_HCA_TIMEBASE_LEN = 28 ; static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_IN = 0 ; static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_WDF = 1 ; static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_PWSEQ0_DEBUG_0 = 2 ; static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_PWSEQ0_DEBUG_1 = 3 ; static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_PWSEQ1_DEBUG_0 = 4 ; static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_PWSEQ1_DEBUG_1 = 5 ; static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_PWSEQ2_DEBUG_0 = 6 ; static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_PWSEQ2_DEBUG_1 = 7 ; static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_PWSEQ3_DEBUG_0 = 8 ; static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_PWSEQ3_DEBUG_1 = 9 ; static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_PWSEQ4_DEBUG_0 = 10 ; static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_PWSEQ4_DEBUG_1 = 11 ; static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_PWSEQ5_DEBUG_0 = 12 ; static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_PWSEQ5_DEBUG_1 = 13 ; static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_PWCTL_DEBUG = 14 ; static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_WDFMGR_DEBUG = 15 ; static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_WDFRD_DEBUG_0 = 16 ; static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_WDFRD_DEBUG_1 = 17 ; static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_WDFWR_DEBUG_0 = 18 ; static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_WDFWR_DEBUG_1 = 19 ; static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_SEC_WDFRD_DEBUG_0 = 20 ; static const uint8_t P9N2_MCA_WDFDBG_DBG_SEL_SEC_WDFRD_DEBUG_1 = 21 ; static const uint8_t P9N2_MCA_WDFDBG_DBG_SPARE = 22 ; static const uint8_t P9N2_MCA_WDFDBG_DBG_SPARE_LEN = 10 ; static const uint8_t P9N2_MCA_WDFDBG_WAT_EVENT_ENABLE = 32 ; static const uint8_t P9N2_MCA_WDFDBG_WAT_SPARE1 = 33 ; static const uint8_t P9N2_MCA_WDFDBG_WAT_SPARE1_LEN = 3 ; static const uint8_t P9N2_MCA_WDFDBG_WAT0_EVENT_SELECT = 36 ; static const uint8_t P9N2_MCA_WDFDBG_WAT0_EVENT_SELECT_LEN = 4 ; static const uint8_t P9N2_MCA_WDFDBG_WAT1_EVENT_SELECT = 40 ; static const uint8_t P9N2_MCA_WDFDBG_WAT1_EVENT_SELECT_LEN = 4 ; static const uint8_t P9N2_MCA_WECR_MBA_WRD_MODE_CFG_WRD_ECC_CHK_DISABLE = 0 ; static const uint8_t P9N2_MCA_WECR_MBA_WRD_MODE_CFG_WRD_ECC_COR_DISABLE = 1 ; static const uint8_t P9N2_MCA_WECR_MBA_WRD_MODE_CFG_CRC_MODE_EN = 2 ; static const uint8_t P9N2_MCA_WECR_MBA_WRD_MODE_CFG_CRC_MODE_X8 = 3 ; static const uint8_t P9N2_MCA_WECR_MBA_WRD_MODE_CFG_FORCE_DFI_CG_ALWAYS_ON = 4 ; static const uint8_t P9N2_MCA_WECR_MBA_WRD_MODE_CFG_CAW2_CE_UE_ERR_DETECT_EN = 5 ; static const uint8_t P9N2_MCA_WESR_SYNDROME = 0 ; static const uint8_t P9N2_MCA_WESR_SYNDROME_LEN = 8 ; static const uint8_t P9N2_MCA_WESR_WHICH_8BECK = 8 ; static const uint8_t P9N2_MCA_WESR_WHICH_8BECK_LEN = 2 ; static const uint8_t P9N2_MCA_WESR_PAR_ERR_ONLY = 10 ; static const uint8_t P9N2_MCA_WOF_FIR = 0 ; static const uint8_t P9N2_MCA_WOF_FIR_LEN = 64 ; static const uint8_t P9N2_MCA_WRITE_PROTECT_ENABLE_REG_RING_LOCKING = 0 ; static const uint8_t P9N2_MCA_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING = 1 ; static const uint8_t P9N2_MCA_WRITE_PROTECT_RINGS_REG_RINGS = 0 ; static const uint8_t P9N2_MCA_WRITE_PROTECT_RINGS_REG_RINGS_LEN = 16 ; static const uint8_t P9N2_MCA_WRTCFG_CFG_WRITE_MODE_ECC_CHK_DIS = 0 ; static const uint8_t P9N2_MCA_WRTCFG_CFG_WRITE_MODE_ECC_COR_DIS = 1 ; static const uint8_t P9N2_MCA_WRTCFG_RESET_KEEPER = 2 ; static const uint8_t P9N2_MCA_WRTCFG_MPIPL = 3 ; static const uint8_t P9N2_MCA_WRTCFG_ASYNC_INJ = 4 ; static const uint8_t P9N2_MCA_WRTCFG_ASYNC_INJ_LEN = 4 ; static const uint8_t P9N2_MCA_WRTCFG_EN_HW365559 = 8 ; static const uint8_t P9N2_MCA_WRTCFG_NEW_WRITE_64B_MODE = 9 ; static const uint8_t P9N2_MCA_WRTCFG_CFG_OVERRUN_FORCE_SUE_ENABLE = 10 ; static const uint8_t P9N2_MCA_WRTDBGMCA_MCA_DBG_SEL_IN = 0 ; static const uint8_t P9N2_MCA_WRTDBGMCA_MCA_DBG_SEL_WRT = 1 ; static const uint8_t P9N2_MCA_WRTDBGMCA_WBRD_DEBUG_0_SELECT = 2 ; static const uint8_t P9N2_MCA_WRTDBGMCA_WBRD_DEBUG_1_SELECT = 3 ; static const uint8_t P9N2_MCA_WRTDBGMCA_SEC_WBRD_DEBUG_0_SELECT = 4 ; static const uint8_t P9N2_MCA_WRTDBGMCA_SEC_WBRD_DEBUG_1_SELECT = 5 ; static const uint8_t P9N2_MCA_WRTDBGMCA_DBG_SPARE_MCA = 6 ; static const uint8_t P9N2_MCA_WRTDBGMCA_DBG_SPARE_MCA_LEN = 10 ; static const uint8_t P9N2_MCA_WRTDBGMCA_WAT_EVENT_ENABLE_MCA = 16 ; static const uint8_t P9N2_MCA_WRTDBGMCA_WAT_SPARE1_MCA = 17 ; static const uint8_t P9N2_MCA_WRTDBGMCA_WAT_SPARE1_MCA_LEN = 3 ; static const uint8_t P9N2_MCA_WRTDBGMCA_WAT0_EVENT_SELECT_MCA = 20 ; static const uint8_t P9N2_MCA_WRTDBGMCA_WAT0_EVENT_SELECT_MCA_LEN = 4 ; static const uint8_t P9N2_MCA_WRTDBGMCA_WAT1_EVENT_SELECT_MCA = 24 ; static const uint8_t P9N2_MCA_WRTDBGMCA_WAT1_EVENT_SELECT_MCA_LEN = 4 ; static const uint8_t P9N2_MCA_WRTDBGNEST_NEST_DBG_SEL_IN = 0 ; static const uint8_t P9N2_MCA_WRTDBGNEST_NEST_DBG_SEL_WRT = 1 ; static const uint8_t P9N2_MCA_WRTDBGNEST_WBMGR_DBG_0_SELECT = 2 ; static const uint8_t P9N2_MCA_WRTDBGNEST_WBMGR_DBG_1_SELECT = 3 ; static const uint8_t P9N2_MCA_WRTDBGNEST_WRCNTL_DBG_SELECT = 4 ; static const uint8_t P9N2_MCA_WRTDBGNEST_DBG_SPARE_NEST = 5 ; static const uint8_t P9N2_MCA_WRTDBGNEST_DBG_SPARE_NEST_LEN = 11 ; static const uint8_t P9N2_MCA_WRTDBGNEST_WAT_EVENT_ENABLE_NEST = 16 ; static const uint8_t P9N2_MCA_WRTDBGNEST_WAT_SPARE1_NEST = 17 ; static const uint8_t P9N2_MCA_WRTDBGNEST_WAT_SPARE1_NEST_LEN = 3 ; static const uint8_t P9N2_MCA_WRTDBGNEST_WAT0_EVENT_SELECT_NEST = 20 ; static const uint8_t P9N2_MCA_WRTDBGNEST_WAT0_EVENT_SELECT_NEST_LEN = 4 ; static const uint8_t P9N2_MCA_WRTDBGNEST_WAT1_EVENT_SELECT_NEST = 24 ; static const uint8_t P9N2_MCA_WRTDBGNEST_WAT1_EVENT_SELECT_NEST_LEN = 4 ; static const uint8_t P9N2_MCA_WDF_WRT_ECC_DW0_ERR_TYPE = 0 ; static const uint8_t P9N2_MCA_WDF_WRT_ECC_DW0_ERR_TYPE_LEN = 3 ; static const uint8_t P9N2_MCA_WDF_WRT_ECC_DW0_SYNDROME = 8 ; static const uint8_t P9N2_MCA_WDF_WRT_ECC_DW0_SYNDROME_LEN = 8 ; static const uint8_t P9N2_MCA_WDF_WRT_ECC_DW1_ERR_TYPE = 16 ; static const uint8_t P9N2_MCA_WDF_WRT_ECC_DW1_ERR_TYPE_LEN = 3 ; static const uint8_t P9N2_MCA_WDF_WRT_ECC_DW1_SYNDROME = 24 ; static const uint8_t P9N2_MCA_WDF_WRT_ECC_DW1_SYNDROME_LEN = 8 ; static const uint8_t P9N2_MCA_WDF_WRT_ECC_DW2_ERR_TYPE = 32 ; static const uint8_t P9N2_MCA_WDF_WRT_ECC_DW2_ERR_TYPE_LEN = 3 ; static const uint8_t P9N2_MCA_WDF_WRT_ECC_DW2_SYNDROME = 40 ; static const uint8_t P9N2_MCA_WDF_WRT_ECC_DW2_SYNDROME_LEN = 8 ; static const uint8_t P9N2_MCA_WDF_WRT_ECC_DW3_ERR_TYPE = 48 ; static const uint8_t P9N2_MCA_WDF_WRT_ECC_DW3_ERR_TYPE_LEN = 3 ; static const uint8_t P9N2_MCA_WDF_WRT_ECC_DW3_SYNDROME = 56 ; static const uint8_t P9N2_MCA_WDF_WRT_ECC_DW3_SYNDROME_LEN = 8 ; static const uint8_t P9N2_MCA_WREITE_WRT_ECC_DW0_ERR_TYPE = 0 ; static const uint8_t P9N2_MCA_WREITE_WRT_ECC_DW0_ERR_TYPE_LEN = 3 ; static const uint8_t P9N2_MCA_WREITE_WRT_ECC_DW0_SYNDROME = 8 ; static const uint8_t P9N2_MCA_WREITE_WRT_ECC_DW0_SYNDROME_LEN = 8 ; static const uint8_t P9N2_MCA_WREITE_WRT_ECC_DW1_ERR_TYPE = 16 ; static const uint8_t P9N2_MCA_WREITE_WRT_ECC_DW1_ERR_TYPE_LEN = 3 ; static const uint8_t P9N2_MCA_WREITE_WRT_ECC_DW1_SYNDROME = 24 ; static const uint8_t P9N2_MCA_WREITE_WRT_ECC_DW1_SYNDROME_LEN = 8 ; static const uint8_t P9N2_MCA_WREITE_WRT_ECC_DW2_ERR_TYPE = 32 ; static const uint8_t P9N2_MCA_WREITE_WRT_ECC_DW2_ERR_TYPE_LEN = 3 ; static const uint8_t P9N2_MCA_WREITE_WRT_ECC_DW2_SYNDROME = 40 ; static const uint8_t P9N2_MCA_WREITE_WRT_ECC_DW2_SYNDROME_LEN = 8 ; static const uint8_t P9N2_MCA_WREITE_WRT_ECC_DW3_ERR_TYPE = 48 ; static const uint8_t P9N2_MCA_WREITE_WRT_ECC_DW3_ERR_TYPE_LEN = 3 ; static const uint8_t P9N2_MCA_WREITE_WRT_ECC_DW3_SYNDROME = 56 ; static const uint8_t P9N2_MCA_WREITE_WRT_ECC_DW3_SYNDROME_LEN = 8 ; #endif