ATTR_MEM_EFF_PSTATES
TARGET_TYPE_MEM_PORT
ARRAY[DIMM]
This byte defines the allowed number of
P-States for the DDR4 Differential Memory Buffer.
P-States can be thought of as an available performance profile.
uint8
2
pstates
ATTR_MEM_EFF_BYTE_ENABLES
TARGET_TYPE_MEM_PORT
ARRAY[DIMM]
These bits are used to activate or deactivate bytes in the
DDR interface of the differential memory
buffer chip.
Right aligned data.
uint16
2
byte_enables
ATTR_MEM_EFF_NIBBLE_ENABLES
TARGET_TYPE_MEM_PORT
ARRAY[DIMM]
These bits are used to select the active nibbles or DQS on the DDR interface.
Right aligned data.
uint32
2
nibble_enables
ATTR_MEM_EFF_FOUR_RANK_MODE
TARGET_TYPE_MEM_PORT
ARRAY[DIMM]
A-Side CA bus drives rank 0/1
and B-Side CA bus drives rank 2/3, DQ/DQS are
shared across the ranks
uint8
DISABLE = 0, ENABLE = 1
2
bool
four_rank_mode
ATTR_MEM_EFF_MRAM_SUPPORT
TARGET_TYPE_MEM_PORT
ARRAY[DIMM]
MRAM Support
Support timing parameters of Everspin DDR4 MRAM
uint8
DISABLE = 0, ENABLE = 1
2
bool
mram_support
ATTR_MEM_EFF_DDP_COMPATIBILITY
TARGET_TYPE_MEM_PORT
ARRAY[DIMM]
DDP Compatibility
Support 1 rank 3DS Device in DDP board routing. CKE[1], CSN[1], ODT[1] of
PHY are connected to C[0], C[1], C[2] of DRAM
uint8
DISABLE = 0, ENABLE = 1
2
bool
ddp_compatibility
ATTR_MEM_EFF_TSV_8H_SUPPORT
TARGET_TYPE_MEM_PORT
ARRAY[DIMM]
TSV 8H Support
Support 8H 3DS routing in board routing when parity check is disabled
uint8
DISABLE = 0, ENABLE = 1
2
bool
tsv_8h_support