ATTR_MSS_OCMB_ENTERPRISE_MODE TARGET_TYPE_OCMB_CHIP Indicates whether the OCMB can support enterprise mode or if it has been fused to only support non-enterprise mode. Note: needs to be setup by the get ECID functionality uint8 NON_ENTERPRISE = 0, ENTERPRISE = 1 ocmb_enterprise_mode ATTR_MSS_OCMB_ENTERPRISE_POLICY TARGET_TYPE_SYSTEM Indicates whether the OCMB is allowed to run in enterprise mode, commodity mode, or either. ALLOW_ENTERPRISE = Most permissive, uses whatever is installed in the way it is intended to be used. REQUIRE_ENTERPRISE = Throws an error for any commodity dimms that are installed. FORCE_NONENTERPRISE = Throws an error for any enterprise dimms that are installed. uint8 ALLOW_ENTERPRISE = 0, FORCE_ENTERPRISE = 1, FORCE_COMMODITY = 2 ALLOW_ENTERPRISE ocmb_enterprise_policy ATTR_MSS_OCMB_NONENTERPRISE_MODE_OVERRIDE TARGET_TYPE_OCMB_CHIP An override to allow an enterprise capable DIMM to be run in non-enterprise mode. Defaults to NO_OVERRIDE uint8 NO_OVERRIDE = 0, OVERRIDE_NON_ENTERPRISE = 1 ocmb_nonenterprise_mode_override ATTR_MSS_OCMB_HALF_DIMM_MODE TARGET_TYPE_OCMB_CHIP Indicates whether the OCMB should be run in half DIMM mode or not Note: needs to be setup by the get ECID functionality uint8 FULL_DIMM = 0, HALF_DIMM = 1 ocmb_half_dimm_mode ATTR_MSS_OCMB_HALF_DIMM_MODE_OVERRIDE TARGET_TYPE_OCMB_CHIP An override that allows the user to control full or half DIMM mode uint8 NO_OVERRIDE = 0, OVERRIDE_FULL_DIMM = 1, OVERRIDE_HALF_DIMM = 2 ocmb_half_dimm_mode_override ATTR_MSS_MEM_MVPD_FWMS TARGET_TYPE_OCMB_CHIP Mark store records from OCMB VPD. The array dimension is [port][mark]. Explorer only has one port so only [0][mark] is used in explorer. uint32 8 mvpd_fwms ATTR_MEM_EXP_INIT_VREF_DQ TARGET_TYPE_MEM_PORT Initial VrefDQ setting before training uint8 2 4 exp_init_vref_dq ATTR_MEM_EXP_INIT_PHY_VREF TARGET_TYPE_MEM_PORT Initial DQ Vref setting of PHY before training uint8 2 4 exp_init_phy_vref ATTR_MEM_EXP_RCD_DIC TARGET_TYPE_MEM_PORT CA and CS signal Driver Characteristics from F0RC03, F0RC04, F0RC05 uint16 exp_rcd_dic ATTR_MEM_EXP_RCD_VOLTAGE_CTRL TARGET_TYPE_MEM_PORT RCD operating voltage VDD and VrefCA control from F0RC0B and F0RC1x uint16 exp_rcd_voltage_ctrl ATTR_MEM_EXP_DRAM_ADDRESS_MIRRORING TARGET_TYPE_MEM_PORT Ranks that have address mirroring. This data is derived from SPD or VPD. Note: This is a bit-wise map and muliple ranks can be mirrored. uint8 2 exp_dram_address_mirroring ATTR_MEM_EXP_RCD_SLEW_RATE TARGET_TYPE_MEM_PORT RCD slew rate control from F1RC02,F1RC03,F1RC04,F1RC05 uint16 exp_rcd_slew_rate ATTR_MEM_EXP_SPD_CL_SUPPORTED TARGET_TYPE_MEM_PORT Cas Latency Supported by DRAM uint32 exp_spd_cl_supported ATTR_MEM_EXP_SPD_TAA_MIN TARGET_TYPE_MEM_PORT Minimum Cas Latency Time (tAAmin) in Picosecond (Byte 24) uint16 ps exp_spd_taa_min ATTR_MSS_EXP_REORDER_QUEUE_SETTING TARGET_TYPE_OCMB_CHIP Contains the settings for write/read reorder queue REORDER REORDER = 0, FIFO = 1 uint8 exp_reorder_queue_setting ATTR_MEM_EXP_FIRMWARE_EMULATION_MODE TARGET_TYPE_MEM_PORT Enable Special mode for Emulation Support uint8 bool NORMAL = 0, EMULATION = 1 exp_firmware_emulation_mode ATTR_MSS_OCMB_EXP_STRUCT_MMIO_ENDIAN_CTRL TARGET_TYPE_SYSTEM Controls whether or not transaction bytes are swapped before and after mmio accesses to the buffer. uint8 SWAP = 0, NO_SWAP = 1 ATTR_MSS_OCMB_EXP_STRUCT_ENDIAN TARGET_TYPE_SYSTEM Controls whether the structure fields written and read to and from the buffer are big or little endian. uint8 BIG_ENDIAN = 0, LITTLE_ENDIAN = 1 ATTR_MSS_OCMB_EXP_STRUCT_MMIO_WORD_SWAP TARGET_TYPE_SYSTEM Controls whether or not the first and second half of MMIO transactions are swapped before and after mmio accesses to the buffer. uint8 SWAP = 0, NO_SWAP = 1 NO_SWAP ATTR_MSS_OCMB_EXP_OMI_CFG_ENDIAN_CTRL TARGET_TYPE_SYSTEM Controls whether OMI CFG reg accesses are considered big or little endian. uint8 LITTLE_ENDIAN = 0, BIG_ENDIAN = 1 LITTLE_ENDIAN ATTR_MSS_OCMB_ECID TARGET_TYPE_OCMB_CHIP ECID of the chip as determined by the IPL getecid procedure. uint16 14 ocmb_ecid ATTR_MEM_EXP_DFIMRL_CLK TARGET_TYPE_MEM_PORT timing parameter for the DFIMRL clock uint8 exp_dfimrl_clk ATTR_MEM_EFF_ATXDLY_A TARGET_TYPE_MEM_PORT ARRAY[ADDRESS INDEX] ATxDly_A/B[0]: ODT[1],ODT[0],CS_N[0],CS_N[1] ATxDly_A/B[1]: ADDR[13],ADDR[5],BG[0],CKE[1] ATxDly_A/B[2]: ADDR[17],ADDR[7],BA[0],ADDR[16] ATxDly_A/B[3]: ADDR[8],BG[1],CID[1],CID[0] ATxDly_A/B[4]: ADDR[1],ADDR[9],ADDR[2],CAPARITY ATxDly_A/B[5]: ADDR[12],ADDR[3],ADDR[4],ADDR[0] ATxDly_A/B[6]: CKE[0],ADDR[15],ACT_N,ADDR[10] ATxDly_A/B[7]: ADDR[11],ADDR[6],BA[1],ADDR[14] uint8 8 exp_atxdly_a ATTR_MEM_EFF_ATXDLY_B TARGET_TYPE_MEM_PORT ARRAY[ADDRESS INDEX] ATxDly_A/B[0]: ODT[1],ODT[0],CS_N[0],CS_N[1] ATxDly_A/B[1]: ADDR[13],ADDR[5],BG[0],CKE[1] ATxDly_A/B[2]: ADDR[17],ADDR[7],BA[0],ADDR[16] ATxDly_A/B[3]: ADDR[8],BG[1],CID[1],CID[0] ATxDly_A/B[4]: ADDR[1],ADDR[9],ADDR[2],CAPARITY ATxDly_A/B[5]: ADDR[12],ADDR[3],ADDR[4],ADDR[0] ATxDly_A/B[6]: CKE[0],ADDR[15],ACT_N,ADDR[10] ATxDly_A/B[7]: ADDR[11],ADDR[6],BA[1],ADDR[14] uint8 8 exp_atxdly_b