ATTR_CEN_EFF_DRAM_ADDRESS_MIRRORING
TARGET_TYPE_MBA
Ranks that have address mirroring.
This data is derived from SPD and C-DIMM VPD.
Bit wise map bit4=RANK0_MIRRORED, bit5=RANK1_MIRRORED, bit6=RANK2_MIRRORED, bit7=RANK3_MIRRORED
Note: Muliple ranks can be mirrored.
uint8
2 2
ATTR_CEN_MSS_VOLT
TARGET_TYPE_MEMBUF_CHIP
DRAM Voltage, each voltage rail would need to have a value. Computed in mss_volt C code - in millivolts
creator: mss_volt
consumer: mss_eff_cnfg, others
firmware notes: none
uint32
ATTR_CEN_MSS_VOLT_VPP
TARGET_TYPE_MEMBUF_CHIP
DRAM VPP Voltage, each voltage rail would need to have a value. Computed in mss_volt C code - in millivolts. 0V - DDR3, 2.5V - DDR4
creator: mss_volt
consumer: mss_eff_cnfg, others
firmware notes: none
uint32
ATTR_CEN_MSS_FREQ_OVERRIDE
TARGET_TYPE_MEMBUF_CHIP
FOR LAB USE ONLY: Frequency override of this memory channel in MHz, comprising of up to three DIMMs. Set by config file or an attribute writing program. Consumed by mss_freq. The default of AUTO means mss_freq will find the best frequencies given the DIMMs plugged in and other rules. Otherwise, this is the system frequency.
firmware notes: Platforms should initialize this attribute to AUTO (0)
uint32
AUTO = 0
ATTR_CEN_MSS_FREQ
TARGET_TYPE_MEMBUF_CHIP
Frequency of this memory channel in MHz, comprising of three DIMMs. Computed in mss_freq
creator: mss_freq
consumer: mss_eff_cnfg, others
firmware notes: none
uint32
ATTR_CEN_MSS_FREQ_BIAS_PERCENTAGE
TARGET_TYPE_MEMBUF_CHIP
Percentage to increase/decrease MEM frequency - two's complement number. Measured in 100's. So the value of 100 is one percent increase.
This frequency change comes from changing multipliers and dividers to get the desired frequency. The supported frequencies come from Tim Diemoz.
Creator: platform set this to 0. Users can set this to a valid value.
VALID Values: (TBD % to TBD %) (Tuleta) (TBD % to TBD %) (Glacier)
Set by: PLL settings written by Dave Cadigan
uint32
ATTR_CEN_MSS_VREF_CAL_CNTL
TARGET_TYPE_MEMBUF_CHIP
Training Control over IPL - ENUM - 0x00=DISABLE /Skip V-ref Train; 0x01=P8_DRAM - Enable V-Ref Train DRAM Level (P8 algorithm); 0x02=P8_RANK Level Training (P8 algorithm); 0x03=Box shmoo; 0x04=Ternary shmoo
Default Value = 0x04 for WR_VREF training on all platforms
uint8
DISABLE = 0, P8_DRAM = 1, P8_RANK = 2, BOX = 3, TERNARY = 4
TERNARY
ATTR_CEN_MSS_VREF_CAL_DELTA_FROM_NOMINAL
TARGET_TYPE_MBA
Controls search boundaries for WR_VREF Ternary shmoo. Value is a delta of register ticks from nominal
Default Value = 0x08 (taken from characterization values), Max value = 0x19
uint8
0x08
ATTR_CEN_EFF_DIMM_RANKS_CONFIGED
TARGET_TYPE_MBA
Bit wise representation of master ranks in each DIMM that are used for reads and writes. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
Dimensions are [port][dimm] A/B=Mba_0 C/D=Mba_1 There are only two DIMM ranks: DIMM0 and DIMM1 where DIMM0 is the furthest from the centaur.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
2 2
ATTR_CEN_EFF_NUM_RANKS_PER_DIMM
TARGET_TYPE_MBA
Number of ranks in each DIMM. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
values are 0,1,2, 4 up to 32
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
2 2
ATTR_CEN_EFF_DIMM_TYPE
TARGET_TYPE_MBA
Type of DIMM: RDIMM, UDIMM, LRDIMM as specified by the JEDIC standard. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
NOTE: Do not use the enum type of CDIMM. Use the attribute EFF_DIMM_CUSTOM to test for a CUSTOM DIMM or CDIMM.
uint8
CDIMM = 0, RDIMM = 1, UDIMM = 2, LRDIMM = 3
ATTR_CEN_EFF_CUSTOM_DIMM
TARGET_TYPE_MBA
DIMM is a custom DIMM. This is commonly known as a CDIMM, but technically, we could support Custom DIMMs of different types than an UDIMM, such as RDIMM and LRDIMM. Created in mss_eff_cnfg
Use this attribute if you need to know if the Centaur is on the DIMM instead of on a planar.
uint8
NO = 0, YES = 1
ATTR_CEN_EFF_DRAM_WIDTH
TARGET_TYPE_MBA
DRAM Device Width: X4, X8, X16, X32. Used in various locations and is computed in mss_eff_cnfg.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
X4 = 4, X8 = 8, X16 = 16, X32 = 32
ATTR_CEN_EFF_DRAM_GEN
TARGET_TYPE_MBA
Generation of memory: DDR3, DDR4. Used in various locations and is computed in mss_eff_cnfg.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
EMPTY = 0, DDR3 = 1, DDR4 = 2
ATTR_CEN_EFF_PRIMARY_RANK_GROUP0
TARGET_TYPE_MBA
RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: mss_eff_cnfg_rank_group
consumer: various
firmware notes: none
uint8
INVALID = 255
2
ATTR_CEN_EFF_PRIMARY_RANK_GROUP1
TARGET_TYPE_MBA
RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: mss_eff_cnfg_rank_group
consumer: various
firmware notes: none
uint8
INVALID = 255
2
ATTR_CEN_EFF_PRIMARY_RANK_GROUP2
TARGET_TYPE_MBA
RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: mss_eff_cnfg_rank_group
consumer: various
firmware notes: none
uint8
INVALID = 255
2
ATTR_CEN_EFF_PRIMARY_RANK_GROUP3
TARGET_TYPE_MBA
RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: mss_eff_cnfg_rank_group
consumer: various
firmware notes: none
uint8
INVALID = 255
2
ATTR_CEN_EFF_SECONDARY_RANK_GROUP0
TARGET_TYPE_MBA
RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: mss_eff_cnfg_rank_group
consumer: various
firmware notes: none
uint8
INVALID = 255
2
ATTR_CEN_EFF_SECONDARY_RANK_GROUP1
TARGET_TYPE_MBA
RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: mss_eff_cnfg_rank_group
consumer: various
firmware notes: none
uint8
INVALID = 255
2
ATTR_CEN_EFF_SECONDARY_RANK_GROUP2
TARGET_TYPE_MBA
RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: mss_eff_cnfg_rank_group
consumer: various
firmware notes: none
uint8
INVALID = 255
2
ATTR_CEN_EFF_SECONDARY_RANK_GROUP3
TARGET_TYPE_MBA
RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: mss_eff_cnfg_rank_group
consumer: various
firmware notes: none
uint8
INVALID = 255
2
ATTR_CEN_EFF_TERTIARY_RANK_GROUP0
TARGET_TYPE_MBA
RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: mss_eff_cnfg_rank_group
consumer: various
firmware notes: none
uint8
INVALID = 255
2
ATTR_CEN_EFF_TERTIARY_RANK_GROUP1
TARGET_TYPE_MBA
RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: mss_eff_cnfg_rank_group
consumer: various
firmware notes: none
uint8
INVALID = 255
2
ATTR_CEN_EFF_TERTIARY_RANK_GROUP2
TARGET_TYPE_MBA
RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: mss_eff_cnfg_rank_group
consumer: various
firmware notes: none
uint8
INVALID = 255
2
ATTR_CEN_EFF_TERTIARY_RANK_GROUP3
TARGET_TYPE_MBA
RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: mss_eff_cnfg_rank_group
consumer: various
firmware notes: none
uint8
INVALID = 255
2
ATTR_CEN_EFF_QUATERNARY_RANK_GROUP0
TARGET_TYPE_MBA
RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: mss_eff_cnfg_rank_group
consumer: various
firmware notes: none
uint8
INVALID = 255
2
ATTR_CEN_EFF_QUATERNARY_RANK_GROUP1
TARGET_TYPE_MBA
RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: mss_eff_cnfg_rank_group
consumer: various
firmware notes: none
uint8
INVALID = 255
2
ATTR_CEN_EFF_QUATERNARY_RANK_GROUP2
TARGET_TYPE_MBA
RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: mss_eff_cnfg_rank_group
consumer: various
firmware notes: none
uint8
INVALID = 255
2
ATTR_CEN_EFF_QUATERNARY_RANK_GROUP3
TARGET_TYPE_MBA
RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: mss_eff_cnfg_rank_group
consumer: various
firmware notes: none
uint8
INVALID = 255
2
ATTR_CEN_EFF_DRAM_WR_VREF
TARGET_TYPE_MBA
DRAM Write Vref. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: VPD(MT) or mss_eff_cnfg_termination
consumer: various.C and initfile
firmware notes: none
This is the nominal value
This is for DDR3
uint32
VDD420 = 420, VDD425 = 425, VDD430 = 430, VDD435 = 435, VDD440 = 440, VDD445 = 445, VDD450 = 450, VDD455 = 455, VDD460 = 460, VDD465 = 465, VDD470 = 470, VDD475 = 475, VDD480 = 480, VDD485 = 485, VDD490 = 490, VDD495 = 495, VDD500 = 500, VDD505 = 505, VDD510 = 510, VDD515 = 515, VDD520 = 520, VDD525 = 525, VDD530 = 530, VDD535 = 535, VDD540 = 540, VDD545 = 545, VDD550 = 550, VDD555 = 555, VDD560 = 560, VDD565 = 565, VDD570 = 570, VDD575 = 575
2
ATTR_CEN_EFF_DRAM_WR_VREF_SCHMOO
TARGET_TYPE_MBA
Enables for which VREF to use on the WR Schmoo. The LSB corresponds to the highest WR Vref
uint32
2
ATTR_CEN_EFF_CEN_DRV_IMP_DQ_DQS
TARGET_TYPE_MBA
Centaur DQ and DQS Drive Impedance Used in various locations and comes from the MT Keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: VPD(MT)/mss_eff_cnfg_termination
consumer: initfile,various.C files
firmware notes: none
This is the nominal value
uint8
OHM24_FFE0 = 0x0A, OHM30_FFE0 = 0x08,
OHM30_FFE480 = 0x48, OHM30_FFE240 = 0x38, OHM30_FFE160 = 0x28, OHM30_FFE120 = 0x18, OHM34_FFE0 = 0x07, OHM34_FFE480 = 0x47, OHM34_FFE240 = 0x37, OHM34_FFE160 = 0x27, OHM34_FFE120 = 0x17, OHM40_FFE0 = 0x06, OHM40_FFE480 = 0x46, OHM40_FFE240 = 0x36, OHM40_FFE160 = 0x26, OHM40_FFE120 = 0x16
2
ATTR_CEN_EFF_CEN_DRV_IMP_DQ_DQS_SCHMOO
TARGET_TYPE_MBA
Enables for which impedance values can be used and tested in a timing test. The bits have a one to one correspondence to the possible driver strengths and start with the first value down to the last (largest) impedance as the LSB of the 8 bit field.
uint32
2
ATTR_CEN_EFF_CEN_SLEW_RATE_DQ_DQS
TARGET_TYPE_MBA
Centaur DQ and DQS Slew Rate Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Slowest slew rate is 0, incrementing by one. The lower the number the slower the slew rate the higher the faster. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: VPD(MT), mss_eff_cnfg_termination
consumer: initfiles,various.C
firmware notes: none
This is the nominal value
uint8
SLEW_3V_NS = 3,
SLEW_4V_NS = 4,
SLEW_5V_NS = 5,
SLEW_6V_NS = 6,
SLEW_MAXV_NS = 7
2
ATTR_CEN_EFF_CEN_DRV_IMP_CLK_SCHMOO
TARGET_TYPE_MBA
Enables for which impedance values can be used and tested in a timing test. The bits have a one to one correspondence to the possible driver strengths and start with the first value down to the last (largest) impedance as the LSB of the 8 bit field.
uint8
2
ATTR_CEN_EFF_CEN_DRV_IMP_SPCKE_SCHMOO
TARGET_TYPE_MBA
Enables for which impedance values can be used and tested in a timing test. The bits have a one to one correspondence to the possible driver strengths and start with the first value down to the last (largest) impedance as the LSB of the 8 bit field.
uint8
2
ATTR_CEN_EFF_CEN_DRV_IMP_CNTL_SCHMOO
TARGET_TYPE_MBA
Enables for which impedance values can be used and tested in a timing test. The bits have a one to one correspondence to the possible driver strengths and start with the first value down to the last (largest) impedance as the LSB of the 8 bit field.
This is the nominal value
uint8
2
ATTR_CEN_EFF_CEN_RCV_IMP_DQ_DQS
TARGET_TYPE_MBA
Centaur DQ and DQS Receiver Impedance Used in various locations and it comes from the VPD MT keyword for custom DIMMs or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
creator: VPD, mss_eff_cnfg_termination
Consumer: initfile + C code
firmware notes: none
This is the nominal value
uint8
OHM15 = 15, OHM20 = 20, OHM30 = 30, OHM40 = 40, OHM48 = 48, OHM60 = 60, OHM80 = 80, OHM120 = 120, OHM160 = 160, OHM240 = 240
2
ATTR_CEN_EFF_CEN_RCV_IMP_DQ_DQS_SCHMOO
TARGET_TYPE_MBA
Enables for which impedance values can be used and tested in a timing test. The bits have a one to one correspondence to the possible receiver termination and start with the first value down to the last (largest) impedance as the LSB of the 32 bit field.
uint32
2
ATTR_CEN_EFF_CEN_SLEW_RATE_DQ_DQS_SCHMOO
TARGET_TYPE_MBA
Slew Rates that can be selected during timing adjustments. The fastest rate is the LSB
uint8
2
ATTR_CEN_EFF_CEN_SLEW_RATE_CLK_SCHMOO
TARGET_TYPE_MBA
Slew Rates that can be selected during timing adjustments. The fastest rate is the LSB
uint8
2
ATTR_CEN_EFF_CEN_SLEW_RATE_SPCKE_SCHMOO
TARGET_TYPE_MBA
Slew Rates that can be selected during timing adjustments. The fastest rate is the LSB
uint8
2
ATTR_CEN_EFF_CEN_SLEW_RATE_ADDR_SCHMOO
TARGET_TYPE_MBA
Slew Rates that can be selected during timing adjustments. The fastest rate is the LSB
uint8
2
ATTR_CEN_EFF_CEN_SLEW_RATE_CNTL_SCHMOO
TARGET_TYPE_MBA
Slew Rates that can be selected during timing adjustments. The fastest rate is the LSB
uint8
2
ATTR_CEN_EFF_RD_VREF
TARGET_TYPE_MBA
Centaur Read Vref. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
Creator: VPD(MT) or mss_eff_cnfg_termination
consumer: various.C and initfiles
firmware notes: none
This is the nominal value
uint32
VDD40375 = 40375, VDD41750 = 41750, VDD43125 = 43125, VDD44500 = 44500, VDD45875 = 45875, VDD47250 = 47250, VDD48625 = 48625, VDD50000 = 50000, VDD51375 = 51375, VDD52750 = 52750, VDD54125 = 54125, VDD55500 = 55500, VDD56875 = 56875, VDD58250 = 58250, VDD59625 = 59625, VDD61000 = 61000, VDD60375 = 60375, VDD61750 = 61750, VDD63125 = 63125, VDD64500 = 64500, VDD65875 = 65875, VDD67250 = 67250, VDD68625 = 68625, VDD70000 = 70000, VDD71375 = 71375, VDD72750 = 72750, VDD74125 = 74125, VDD75500 = 75500, VDD76875 = 76875, VDD78250 = 78250, VDD79625 = 79625, VDD81000 = 81000
2
ATTR_CEN_EFF_CEN_RD_VREF_SCHMOO
TARGET_TYPE_MBA
Enables for which VREF value can be used in timing adjustments. The highest voltage corresponds to the LSB
uint32
2
ATTR_CEN_EFF_DIMM_SIZE
TARGET_TYPE_MBA
DIMM Size. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
2 2
ATTR_CEN_EFF_DRAM_BANKS
TARGET_TYPE_MBA
Number of DRAM banks. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
ATTR_CEN_EFF_DRAM_ROWS
TARGET_TYPE_MBA
Number of DRAM rows. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
ATTR_CEN_EFF_DRAM_COLS
TARGET_TYPE_MBA
Number of DRAM columns. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
ATTR_CEN_EFF_DRAM_DENSITY
TARGET_TYPE_MBA
DRAM Density. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
ATTR_CEN_EFF_DRAM_TRCD
TARGET_TYPE_MBA
RAS to CAS Delay. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg_timing
consumer: various
firmware notes: none
uint8
ATTR_CEN_EFF_DRAM_TRRD
TARGET_TYPE_MBA
Row ACT to Row ACT Delay. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg_timing
consumer: various
firmware notes: none
uint8
ATTR_CEN_EFF_DRAM_TRRD_L
TARGET_TYPE_MBA
DDR4 - Row to Row:Long timings tRRD_L : bank accesses within the same bank group
creator: mss_eff_cnfg_timing
consumer: various
firmware notes: none
uint8
ATTR_CEN_EFF_DRAM_TRP
TARGET_TYPE_MBA
Row Precharge Delay. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg_timing
consumer: various
firmware notes: none
uint8
ATTR_CEN_EFF_DRAM_TRAS
TARGET_TYPE_MBA
ACT to Precharge Delay. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg_timing
consumer: various
firmware notes: none
uint8
ATTR_CEN_EFF_DRAM_TRC
TARGET_TYPE_MBA
ACT to ACT/Refresh Delay. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg_timing
consumer: various
firmware notes: none
uint8
ATTR_CEN_EFF_DRAM_TRFI
TARGET_TYPE_MBA
Refresh Interval. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. In unit clock.
creator: mss_eff_cnfg_timing
consumer: various
firmware notes: none
uint32
ATTR_CEN_EFF_DRAM_TRFC
TARGET_TYPE_MBA
Refresh Recovery Delay. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. In unit clock.
creator: mss_eff_cnfg_timing
consumer: various
firmware notes: none
uint32
ATTR_CEN_EFF_DRAM_TWTR
TARGET_TYPE_MBA
Internal Write to Read Delay. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg_timing
consumer: various
firmware notes: none
uint8
ATTR_CEN_EFF_DRAM_TWTR_L
TARGET_TYPE_MBA
DDR4 - Long timings (tCCD_L, tRRD_L, and tWTR_L): bank accesses within the same bank group
creator: mss_eff_cnfg_timing
consumer: various
firmware notes: none
uint8
ATTR_CEN_EFF_DRAM_TRTP
TARGET_TYPE_MBA
Internal Read to Precharge Delay. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg_timing
consumer: various
firmware notes: none
uint8
ATTR_CEN_EFF_DRAM_TFAW
TARGET_TYPE_MBA
Four ACT Window Delay. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg_timing
consumer: various
firmware notes: none
uint8
ATTR_CEN_EFF_DRAM_BL
TARGET_TYPE_MBA
Burst Length. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
BL8 = 0, OTF = 1, BC4 = 2
ATTR_CEN_EFF_DRAM_CL
TARGET_TYPE_MBA
CAS Latency. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg_timing
consumer: various
firmware notes: none
uint8
ATTR_CEN_EFF_DRAM_AL
TARGET_TYPE_MBA
Additive Latency. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg_timing
consumer: various
firmware notes: none
uint8
DISABLE = 0, CL_MINUS_1 = 1, CL_MINUS_2 = 2, CL_MINUS_3 = 3
ATTR_CEN_EFF_DRAM_CWL
TARGET_TYPE_MBA
CAS Write Latency. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg_timing
consumer: various
firmware notes: none
uint8
ATTR_CEN_EFF_DRAM_RBT
TARGET_TYPE_MBA
Read Burst Type. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
SEQUENTIAL = 0, INTERLEAVE = 1
ATTR_CEN_EFF_DRAM_TM
TARGET_TYPE_MBA
Test Mode. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
NORMAL= 0, TEST = 1
ATTR_CEN_EFF_DRAM_DLL_RESET
TARGET_TYPE_MBA
DLL Reset. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
NO = 0, YES = 1
ATTR_CEN_EFF_DRAM_WR
TARGET_TYPE_MBA
Write Recovery. Used in various locations and is computed in mss_eff_cnfg_timing. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg_timing
consumer: various
firmware notes: none
uint8
ATTR_CEN_EFF_DRAM_DLL_PPD
TARGET_TYPE_MBA
DLL Precharge PD. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
SLOWEXIT = 0, FASTEXIT = 1
ATTR_CEN_EFF_DRAM_DLL_ENABLE
TARGET_TYPE_MBA
DLL Enable. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
ENABLE = 0, DISABLE = 1
ATTR_CEN_EFF_DRAM_TDQS
TARGET_TYPE_MBA
TDQS. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
DISABLE = 0, ENABLE = 1
ATTR_CEN_EFF_DRAM_WR_LVL_ENABLE
TARGET_TYPE_MBA
Write Level Enable. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
DISABLE = 0, ENABLE = 1
ATTR_CEN_EFF_DRAM_OUTPUT_BUFFER
TARGET_TYPE_MBA
DRAM Qoff. Enables or disables DRAM output. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
ENABLE = 0, DISABLE = 1
ATTR_CEN_EFF_DRAM_PASR
TARGET_TYPE_MBA
Partial Array Self-Refresh. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
FULL = 0, FIRST_HALF = 1, FIRST_QUARTER = 2, FIRST_EIGHTH = 3, LAST_THREE_FOURTH = 4, LAST_HALF = 5, LAST_QUARTER = 6, LAST_EIGHTH = 7
ATTR_CEN_EFF_DRAM_ASR
TARGET_TYPE_MBA
Auto Self-Refresh. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
SRT = 0, ASR = 1
ATTR_CEN_EFF_DRAM_SRT
TARGET_TYPE_MBA
Self-Refresh Temperature Range. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
NORMAL = 0, EXTEND = 1
ATTR_CEN_EFF_MPR_LOC
TARGET_TYPE_MBA
Multi Purpose Register Location. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
ATTR_CEN_EFF_MPR_MODE
TARGET_TYPE_MBA
Multi Purpose Register Mode. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
DISABLE = 0, ENABLE = 1
ATTR_CEN_EFF_DIMM_RCD_CNTL_WORD_0_15
TARGET_TYPE_MBA
RCD Control Word. Used in mss_dram_init and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint64
2 2
ATTR_CEN_EFF_DIMM_DDR4_RC00
TARGET_TYPE_MBA
F0RC00: Global Features Control Word.For normal operation, output inversion is always enabled. For DIMM vendor test purpose, output inversion can be disabled.
When disabled, register tPDM is not guaranteed to be met. NOTE: creator: mss_eff_cnfg will set Default value - 0x00. Values Range from 0-8.
00 - Normal Operation; 01 - Output Inversion Disabled; 02 - Weak Drive Enabled; 04 - A outputs disabled; 08 - B outputs disabled; So on.
No need to calculate; User can override with desired experimental value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
ATTR_CEN_EFF_DIMM_DDR4_RC01
TARGET_TYPE_MBA
F0RC01 - Clock Driver Enable Control Word.1. Output clocks may be individually turned on or off to conserve power. The system must read the module SPD to determine which clock outputs are used by the module. The PLL remains locked on CK_t/CK_c unless the system stops the clock inputs to the DDR4RCD02 to enter the lowest power mode.
creator: mss_eff_cnfg will set Default value - 0x00. Values Range from 0-8. No need to calculate; User can override with desired experimental value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
ATTR_CEN_EFF_DIMM_DDR4_RC02
TARGET_TYPE_MBA
F0RC02: Timing and IBT Control Word; mss_eff_cnfg will set Default value - 0x00. Values Range from 0-8. No need to calculate; User can override with desired experimental value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
ATTR_CEN_EFF_DIMM_DDR4_RC03
TARGET_TYPE_MBA
F0RC03 - CA and CS Signals Driver Characteristics Control Word; mss_eff_cnfg will set Default value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD byte 137, 1st Nibble for CS and CA.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
ATTR_CEN_EFF_DIMM_DDR4_RC04
TARGET_TYPE_MBA
F0RC04 - ODT and CKE Signals Driver Characteristics Control Word; mss_eff_cnfg will set Default value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD byte 137, 2nd Nibble for ODT and CKE.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
ATTR_CEN_EFF_DIMM_DDR4_RC05
TARGET_TYPE_MBA
F0RC05 - Clock Driver Characteristics Control Word; mss_eff_cnfg will set Default value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD byte 138, 2nd Nibble for CK.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
ATTR_CEN_EFF_DIMM_DDR4_RC06_07
TARGET_TYPE_MBA
F0RC06: Command Space Control Word definition; mss_eff_cnfg will set Default value - 0xF0 (NOP). Values Range from 00 to F0. F0RC07 not used. RDIMM
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
ATTR_CEN_EFF_DIMM_DDR4_RC08
TARGET_TYPE_MBA
F0RC08: Input/Output Configuration Control Word; mss_eff_cnfg will set Default value - 0x03. Values Range from 00 to 08 decimal. Check the stack height and calculate dynamically; 00 = Stack height_8; 01 = Stack height_4;
02 = Stack height_2;
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
ATTR_CEN_EFF_DIMM_DDR4_RC09
TARGET_TYPE_MBA
F0RC06: Command Space Control Word definition;mss_eff_cnfg will set Default value - 0xF0 (NOP). Values Range from 00 to F0. No need to calculate; User can override with desired experimental value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
ATTR_CEN_EFF_DIMM_DDR4_RC10
TARGET_TYPE_MBA
RDIMM Operating Speed; Read from ATTR_CEN_MSS_FREQ; mss_eff_cnfg will set Default value - 00. Values Range from 00 to 09. No need to calculate; User can override with desired experimental value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
ATTR_CEN_EFF_DIMM_DDR4_RC11
TARGET_TYPE_MBA
Operating Voltage VDD and VrefCA Source Control Word; Read from ATTR_CEN_MSS_VOLT.mss_eff_cnfg will set Default value - 14. Values Range from 00 to 15 decimal. No need to calculate; User can override with desired experimental value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
ATTR_CEN_EFF_DIMM_DDR4_RC12
TARGET_TYPE_MBA
F0RC0C - Training Control Word; mss_eff_cnfg will set Default value - 00. Values Range from 00 to 07 decimal.No need to calculate; User can override with desired experimental value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
ATTR_CEN_EFF_DIMM_DDR4_RC13
TARGET_TYPE_MBA
F0RC0D - DIMM Configuration Control Word; mss_eff_cnfg will set Default value - 0B. Values Range from 00 to 15 decimal. Dynamically calculated using 4 bits[0:3] Bit 0 - Address Mirroring; Bit 1 - Rdimm(1)/Lrdimm (0) ; Bit 2 - N/A ; Bit 3 - CS Mode (Direct / Quad CS mode etc);
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
ATTR_CEN_EFF_DIMM_DDR4_RC14
TARGET_TYPE_MBA
F0RC0E - Parity Control Word; mss_eff_cnfg will set Default value - 00. Check from ATTR_CEN_EFF_CA_PARITY and assign; Values Range from 00 to 0F.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
ATTR_CEN_EFF_DIMM_DDR4_RC15
TARGET_TYPE_MBA
F0RC0F - Command Latency Adder Control Word; mss_eff_cnfg will set Default value - 04. Values Range from 00 to 04. No need to calculate; User can override with desired experimental value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
ATTR_CEN_EFF_DIMM_DDR4_RC_1x
TARGET_TYPE_MBA
F0RC1x - Internal VrefCA Control Word; mss_eff_cnfg will set Default value - 00. Values Range from 00 to 3F.No need to calculate; User can override with desired experimental value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
ATTR_CEN_EFF_DIMM_DDR4_RC_2x
TARGET_TYPE_MBA
F0RC2x: I2C Bus Control Word; mss_eff_cnfg will set Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
ATTR_CEN_EFF_DIMM_DDR4_RC_3x
TARGET_TYPE_MBA
F0RC3x - Fine Granularity RDIMM Operating Speed; mss_eff_cnfg will set Default value = (Operating Freq - 1250)/20. Values Range from 00 to 61 Hex.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
ATTR_CEN_EFF_DIMM_DDR4_RC_4x
TARGET_TYPE_MBA
F0RC4x: CW Source Selection Control Word; mss_eff_cnfg will set Default value - 00. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
ATTR_CEN_EFF_DIMM_DDR4_RC_5x
TARGET_TYPE_MBA
F0RC5x: CW Destination Selection and Write/Read Additional QxODT[1:0] Signal High; mss_eff_cnfg will set Default value - 00. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
ATTR_CEN_EFF_DIMM_DDR4_RC_6x
TARGET_TYPE_MBA
F0RC6x: CW Data Control Word; mss_eff_cnfg will set Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
ATTR_CEN_EFF_DIMM_DDR4_RC_7x
TARGET_TYPE_MBA
F0RC7x: IBT Control Word; mss_eff_cnfg will set Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
ATTR_CEN_EFF_DIMM_DDR4_RC_8x
TARGET_TYPE_MBA
F0RC8x: ODT Input Buffer/IBT, QxODT Output Buffer and Timing Control Word; mss_eff_cnfg will set Default value - 00. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
ATTR_CEN_EFF_DIMM_DDR4_RC_9x
TARGET_TYPE_MBA
F0RC9x1: QxODT[1:0] Write Pattern Control Word; mss_eff_cnfg will set Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
ATTR_CEN_EFF_DIMM_DDR4_RC_Ax
TARGET_TYPE_MBA
F0RCAx1: QxODT[1:0] Read Pattern Control Word; mss_eff_cnfg will set Default value - 00. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
ATTR_CEN_EFF_DIMM_DDR4_RC_Bx
TARGET_TYPE_MBA
F0RCBx: IBT and MRS Snoop Control Word; mss_eff_cnfg will set Default value - 07. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value.
creator: mss_eff_cnfg
consumer: mss_dram_init
firmware notes: none
uint8
2 2
ATTR_CEN_EFF_SCHMOO_MODE
TARGET_TYPE_MBA
Specifies the shmoo mode to use during draminit_train_adv.
uint8
FAST = 0, ONE_SLOW = 1, QUARTER_SLOW = 2, HALF_SLOW = 3, FULL_SLOW = 4, ONE_CHAR = 5, QUARTER_CHAR = 6, HALF_CHAR = 7, FULL_CHAR = 8
ATTR_CEN_EFF_SCHMOO_ADDR_MODE
TARGET_TYPE_MBA
Specifies the shmoo mode to use during draminit_train_adv
uint8
FEW_ADDR= 0, QUARTER_ADDR = 1, HALF_ADDR = 2, FULL_ADDR = 3
ATTR_CEN_EFF_SCHMOO_TEST_VALID
TARGET_TYPE_MBA
Specifies the shmoo test to run during draminit_train_adv. Bit wise.
uint8
NONE = 0x00,
MCBIST = 0x01,
WR_EYE = 0x02,
RD_EYE = 0x04,
WR_DQS = 0x08,
RD_DQS = 0x10,
BOX = 0x20
ATTR_CEN_EFF_SCHMOO_PARAM_VALID
TARGET_TYPE_MBA
Specifies the shmoo parameters to use during draminit_train_adv. Bit wise.
uint8
PARAM_NONE = 0x00,
DELAY_REG = 0x01,
DRV_IMP = 0x02,
SLEW_RATE = 0x04,
WR_VREF = 0x08,
RD_VREF = 0x10,
RCV_IMP = 0x20
ATTR_CEN_EFF_SCHMOO_VREF_STEP
TARGET_TYPE_MBA
Specifies the step size in register ticks for WR_VREF and RD_VREF shmoos.
uint8
ATTR_CEN_EFF_SCHMOO_WR_EYE_MIN_MARGIN
TARGET_TYPE_MBA
Specifies the shmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.
uint8
ATTR_CEN_EFF_SCHMOO_RD_EYE_MIN_MARGIN
TARGET_TYPE_MBA
Specifies the shmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.
uint8
ATTR_CEN_EFF_SCHMOO_DQS_CLK_MIN_MARGIN
TARGET_TYPE_MBA
Specifies the shmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.
uint8
ATTR_CEN_EFF_SCHMOO_RD_GATE_MIN_MARGIN
TARGET_TYPE_MBA
Specifies the shmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.
uint8
ATTR_CEN_EFF_SCHMOO_ADDR_CMD_MIN_MARGIN
TARGET_TYPE_MBA
Specifies the shmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.
uint8
ATTR_CEN_EFF_MEMCAL_INTERVAL
TARGET_TYPE_MBA
Specifies the memcal interval in clocks.
uint32
DISABLE = 0
ATTR_CEN_EFF_ZQCAL_INTERVAL
TARGET_TYPE_MBA
Specifies the zqcal interval in clocks.
uint32
DISABLE = 0
ATTR_CEN_EFF_IBM_TYPE
TARGET_TYPE_MBA
Specifies the memory topology type. See centaur workbook.
uint8
UNDEFINED = 0, TYPE_1A = 1, TYPE_1B = 2, TYPE_1C = 3, TYPE_1D = 4, TYPE_2A = 5, TYPE_2B = 6, TYPE_2C = 7, TYPE_3A = 8, TYPE_3B = 9, TYPE_3C = 10, TYPE_4A = 11, TYPE_4B = 12, TYPE_4C = 13, TYPE_5A = 14, TYPE_5B = 15, TYPE_5C = 16, TYPE_5D = 17, TYPE_6A = 18, TYPE_6B = 19, TYPE_6C = 20, TYPE_7A = 21, TYPE_7B = 22, TYPE_7C = 23, TYPE_8A = 24, TYPE_8B = 25, TYPE_8C = 26
2 2
ATTR_CEN_EFF_NUM_DROPS_PER_PORT
TARGET_TYPE_MBA
Specifies the number of DIMM dimensions that are valid per port.
uint8
EMPTY = 0, SINGLE = 1, DUAL = 2
ATTR_CEN_EFF_STACK_TYPE
TARGET_TYPE_MBA
Specifies the DRAM package type.
uint8
NONE = 0, DDP_QDP = 1, STACK_3DS = 2
2 2
ATTR_CEN_EFF_NUM_MASTER_RANKS_PER_DIMM
TARGET_TYPE_MBA
Specifies the number of master ranks per DIMM.
uint8
2 2
ATTR_CEN_EFF_NUM_PACKAGES_PER_RANK
TARGET_TYPE_MBA
Specifies the number of DRAM packages per rank.
uint8
2 2
ATTR_CEN_EFF_NUM_DIES_PER_PACKAGE
TARGET_TYPE_MBA
Specifies the number of DRAM dies per package.
uint8
2 2
ATTR_CEN_MSS_MEM_THROTTLE_NUMERATOR_PER_MBA
TARGET_TYPE_MBA
This is the throttle numerator setting for cfg_nm_n_per_mba creator: mss_eff_cnfg consumer: mc_config firmware notes: none
uint32
ATTR_CEN_MSS_MEM_THROTTLE_DENOMINATOR
TARGET_TYPE_MBA
This is the throttle denominator setting for cfg_nm_m creator: mss_eff_cnfg consumer: mc_config firmware notes: none
uint32
ATTR_CEN_MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP
TARGET_TYPE_MBA
This is the throttle numerator setting for cfg_nm_n_per_chip creator: mss_eff_cnfg consumer: mc_config firmware notes: none
uint32
ATTR_CEN_MSS_MEM_WATT_TARGET
TARGET_TYPE_MBA
Total memory power limit in cW for the dimms on the memory channel pair. Used to compute the throttles on the channel and/or dimms creator: unknown consumer: mss_eff_config firmware notes: none
uint32
ATTR_CEN_MSS_POWER_SLOPE
TARGET_TYPE_MBA
Master Power slope value for dimm
uint32
2 2
ATTR_CEN_MSS_POWER_SLOPE2
TARGET_TYPE_MBA
Supplier Power slope value for dimm
uint32
2 2
ATTR_CEN_MSS_POWER_INT
TARGET_TYPE_MBA
Master Power intercept value for dimm
uint32
2 2
ATTR_CEN_MSS_POWER_INT2
TARGET_TYPE_MBA
Supplier Power intercept value for dimm
uint32
2 2
ATTR_CEN_MSS_TOTAL_POWER_SLOPE
TARGET_TYPE_MBA
Master Total Power slope value for dimm
uint32
2 2
ATTR_CEN_MSS_TOTAL_POWER_SLOPE2
TARGET_TYPE_MBA
Supplier Total Power slope value for dimm
uint32
2 2
ATTR_CEN_MSS_TOTAL_POWER_INT
TARGET_TYPE_MBA
Master Total Power intercept value for dimm
uint32
2 2
ATTR_CEN_MSS_TOTAL_POWER_INT2
TARGET_TYPE_MBA
Supplier Total Power intercept value for dimm
uint32
2 2
ATTR_CEN_MSS_CHANNEL_PAIR_MAXPOWER
TARGET_TYPE_MBA
Channel Pair Max Power output from thermal procedures
uint32
ATTR_CEN_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA
TARGET_TYPE_MBA
Runtime throttle numerator setting for cfg_nm_n_per_mba
uint32
ATTR_CEN_MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR
TARGET_TYPE_MBA
Runtime throttle denominator setting for cfg_nm_m
uint32
ATTR_CEN_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP
TARGET_TYPE_MBA
Runtime throttle numerator setting for cfg_nm_n_per_chip
uint32
ATTR_CEN_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_MBA
TARGET_TYPE_SYSTEM
Machine Readable Workbook safe mode throttle value for numerator cfg_nm_n_per_mba
uint32
ATTR_CEN_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP
TARGET_TYPE_SYSTEM
Machine Readable Workbook safe mode throttle value for numerator cfg_nm_n_per_chip
uint32
ATTR_CEN_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT
TARGET_TYPE_MEMBUF_CHIP
This dial sets the Centaur address bits used to interleave addresses between MBA01 and MBA23. Valid values are 23 through 32. See Centaur Spec Chapter 5 for details. Used in the intifile
uint8
ATTR_CEN_MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE
TARGET_TYPE_MEMBUF_CHIP
Value of on or off. On is 256 bit interleave. Off, the translation is on 128 bit interleave mode. See centaur workbook chapter 5.
uint8
OFF = 0, ON = 1
ATTR_CEN_MRW_MBA_CACHELINE_INTERLEAVE_MODE_CONTROL
TARGET_TYPE_SYSTEM
At a system level, this attribute controls if interleaving is required, requested or never. The MRW.
uint8
NEVER = 0, REQUIRED = 1, REQUESTED = 2
ATTR_CEN_MSS_CACHE_ENABLE
TARGET_TYPE_MEMBUF_CHIP
Reflects the functionality of the L4 Cache. Determines if the L4 is enabled or not. See chapter 6 of the Centaur Workbook. On means the full cache is enabled. HALF_A (EVEN) means only A is enabled and HALF_B (ODD) means only B is enabled. For DD1X, the values of UNK_OFF, UNK_ON, UNK_HALF_A and UNK_HALFB were added because early parts did not have the fuses blown correctly, so the cache repairs may not have worked. This value is set by the platform which can get the chips value by running the mss_cen_get_ecid function.
Note: Cronus and Firmware plus our initfiles do not really support any of the UNK values. It is the responsibility of the platform to map the UNK values to the appropriate value of OFF/ON/HALF_A/HALF_B
uint8
OFF = 0, ON = 1, HALF_A = 3, HALF_B = 5, UNK_OFF = 8, UNK_ON = 9, UNK_HALF_A = 0xB, UNK_HALF_B = 0xD
ON
ATTR_CEN_MSS_PREFETCH_ENABLE
TARGET_TYPE_SYSTEM
Value of on or off. Determines if prefetching enabled or not. See chapter 7 of the Centaur Workbook.
uint8
OFF = 0, ON = 1
ON
ATTR_CEN_MSS_CLEANER_ENABLE
TARGET_TYPE_SYSTEM
Value of on or off. Determines if the cleaner of the L4 cache (write modified entries to memory on idle cycles) enabled or not. See chapter 7 of the Centaur Workbook.
uint8
OFF = 0, ON = 1
ATTR_CEN_MSS_EFF_DIMM_FUNCTIONAL_VECTOR
TARGET_TYPE_MBA
A bit vector (per Dean's request) specifying if a DIMM is functional. DIMM attributes, such as SIZE, are qualified by this bit vector. The attribute ANDed 0x80 means port 0, DIMM 0 is functional, 0x40 means port 0, DIMM 1 is functional. 0x08 means port 1, DIMM 0 is functional and 0x04 means port 1 DIMM 1 is functional. A fully populated system would have the value of 0xCC. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. creator: mss_eff_cnfg consumer: various firmware notes: none
This factors in functionality
uint8
ATTR_CEN_EFF_DRAM_LPASR
TARGET_TYPE_MBA
Low Power Auto Self-Refresh. This is for DDR4 MRS2. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
MANUAL_NORMAL =0, MANUAL_REDUCED = 1, MANUAL_EXTENDED = 2, ASR = 3
ATTR_CEN_EFF_MPR_PAGE
TARGET_TYPE_MBA
MPR Page Selection This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
PG0 = 0, PG1 = 1, PG2 = 2, PG3 = 3
ATTR_CEN_EFF_GEARDOWN_MODE
TARGET_TYPE_MBA
Gear Down Mode. This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
HALF =0, QUARTER=1
ATTR_CEN_EFF_PER_DRAM_ACCESS
TARGET_TYPE_MBA
Per DRAM accessibility. This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
DISABLE = 0, ENABLE = 1
ATTR_CEN_EFF_TEMP_READOUT
TARGET_TYPE_MBA
Temperature sensor readout. This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
DISABLE = 0, ENABLE = 1
ATTR_CEN_EFF_FINE_REFRESH_MODE
TARGET_TYPE_MBA
Fine refresh mode. This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
NORMAL = 0, FIXED_2X = 1, FIXED_4X = 2, FLY_2X = 5, FLY_4X = 6
ATTR_CEN_EFF_CRC_WR_LATENCY
TARGET_TYPE_MBA
write latency for CRC and DM. This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
4NCK = 4, 5NCK = 5, 6NCK = 6
ATTR_CEN_EFF_MPR_RD_FORMAT
TARGET_TYPE_MBA
MPR READ FORMAT. This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
SERIAL = 0, PARALLEL = 1, STAGGERED = 2, RESERVED_TEMP= 3
ATTR_CEN_EFF_MAX_POWERDOWN_MODE
TARGET_TYPE_MBA
Max Power down mode. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
DISABLE = 0, ENABLE = 1
ATTR_CEN_EFF_TEMP_REF_RANGE
TARGET_TYPE_MBA
Temp ref range. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
NORMAL = 0, EXTEND = 1
ATTR_CEN_EFF_TEMP_REF_MODE
TARGET_TYPE_MBA
Temp controlled ref mode. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
DISABLE = 0, ENABLE = 1
ATTR_CEN_EFF_INT_VREF_MON
TARGET_TYPE_MBA
Internal Vref Monitor.. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
DISABLE = 0, ENABLE = 1
ATTR_CEN_EFF_CS_CMD_LATENCY
TARGET_TYPE_MBA
CS to CMD/ADDR Latency. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
DISABLE = 0, 3CYC = 3, 4CYC = 4, 5CYC = 5, 6CYC = 6, 8CYC = 8
ATTR_CEN_EFF_SELF_REF_ABORT
TARGET_TYPE_MBA
Self Refresh Abort. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
DISABLE = 0, ENABLE = 1
ATTR_CEN_EFF_RD_PREAMBLE_TRAIN
TARGET_TYPE_MBA
Read Pre amble Training Mode. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
DISABLE = 0, ENABLE = 1
ATTR_CEN_EFF_RD_PREAMBLE
TARGET_TYPE_MBA
Read Pre amble. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
1NCLK = 1, 2NCLK = 2
ATTR_CEN_EFF_WR_PREAMBLE
TARGET_TYPE_MBA
Write Pre amble. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
1NCLK = 1, 2NCLK = 2
ATTR_CEN_EFF_CA_PARITY_LATENCY
TARGET_TYPE_MBA
C/A Parity Latency Mode. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
DISABLE = 0, PL4 = 4, PL5 = 5, PL6 = 6, PL8 = 8
ATTR_CEN_EFF_CRC_ERROR_CLEAR
TARGET_TYPE_MBA
CRC Error Clear. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
CLEAR = 0, ERROR = 1
ATTR_CEN_EFF_CA_PARITY_ERROR_STATUS
TARGET_TYPE_MBA
C/A Parity Error Status. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
CLEAR = 0, ERROR = 1
ATTR_CEN_EFF_ODT_INPUT_BUFF
TARGET_TYPE_MBA
ODT Input Buffer during power down. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
ACTIVATED = 0, DEACTIVATED = 1
ATTR_CEN_EFF_CA_PARITY
TARGET_TYPE_MBA
CA Parity Persistance Error. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
DISABLE = 0, ENABLE = 1
ATTR_CEN_EFF_DATA_MASK
TARGET_TYPE_MBA
Data Mask. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
DISABLE = 0, ENABLE = 1
ATTR_CEN_EFF_WRITE_DBI
TARGET_TYPE_MBA
Write DBI. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
DISABLE = 0, ENABLE = 1
ATTR_CEN_EFF_READ_DBI
TARGET_TYPE_MBA
Read DBI. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory channel will have a value.
creator: mss_eff_cnfg
consumer: various
firmware notes: none
uint8
DISABLE = 0, ENABLE = 1
ATTR_CEN_EFF_VREF_DQ_TRAIN_VALUE
TARGET_TYPE_MBA
vrefdq_train value. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory channel will have a value.
Creator: mss_eff_cnfg
Consumer:various
Firmware notes: none
uint8
2 2 4
ATTR_CEN_EFF_VREF_DQ_TRAIN_RANGE
TARGET_TYPE_MBA
vrefdq_train range. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory channel will have a value.
Creator: mss_eff_cnfg
Consumer:various
Firmware notes: none
uint8
RANGE1 = 0, RANGE2 = 1
2 2 4
ATTR_CEN_EFF_VREF_DQ_TRAIN_ENABLE
TARGET_TYPE_MBA
vrefdq_train enable. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory channel will have a value.
Creator: mss_eff_cnfg
Consumer:various
Firmware notes: none
uint8
DISABLE = 0, ENABLE = 1
2 2 4
ATTR_CEN_EFF_DRAM_TCCD_L
TARGET_TYPE_MBA
tccd_l. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory channel will have a value.
Creator: mss_eff_cnfg
Consumer:various
Firmware notes: none
uint8
4NCK = 4, 5NCK = 5, 6NCK = 6, 7NCK = 7, 8NCK = 8
ATTR_CEN_TCCD_L
TARGET_TYPE_MBA
tccd_l. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory channel will have a value.
Creator: mss_eff_cnfg
Consumer:various
Firmware notes: none
uint8
4NCK = 4, 5NCK = 5, 6NCK = 6, 7NCK = 7, 8NCK = 8
ATTR_CEN_EFF_WRITE_CRC
TARGET_TYPE_MBA
Write CRC control for DDR4 in MRS2. Set in mss_eff_cnfg. Each memory channel will have a value.
Creator: mss_eff_cnfg
Consumer:various
Firmware notes: none
uint8
DISABLE = 0, ENABLE = 1
ATTR_CEN_MSS_CAL_STEP_ENABLE
TARGET_TYPE_MBA
A bit vector denoting valid cal steps to run during dram_init_train.
[0] EXT_ZQCAL
[1] WR_LEVEL
[2] DQS_ALIGN
[3] RDCLK_ALIGN
[4] READ_CTR
[5] WRITE_CTR
[6] COARSE_WR
[7] COARSE_RD
bits6:7 will be consumed together to form COARSE_LVL.
uint8
EXT_ZQCAL = 0, WR_LVL = 1, DQS_ALIGN = 2, RDCLK_ALIGN = 3, RD_CTR = 4, WR_CTR = 5, COARSE_WR = 6, COARSE_RD = 7
ATTR_CEN_MSS_DRAMINIT_RESET_DISABLE
TARGET_TYPE_SYSTEM
A disable switch for resetting the phy delay values at the beginning of calling mss_draminit_training.
uint8
DISABLE = 1, ENABLE = 0
ENABLE
ATTR_CEN_MSS_SLEW_RATE_DATA
TARGET_TYPE_MBA
The 4 bit result of running the slew calibration algorithm at various rates and impedances. The first dimension is port, the second is the impedance of 24,30,34, and 40 Ohms. The 3rd dimension is the rate: 3,4,5 or 6 V/ns. Computed and sent to the correct data blocks in phy_reset. Also used in advanced training
uint8
2 4 4
ATTR_CEN_MSS_SLEW_RATE_ADR
TARGET_TYPE_MBA
The 4 bit result of running the slew calibration algorithm at various rates and impedances. The first dimension is the port. The second is the impedance of 15, 20, 30 and 40 Ohms. The 3rd dimension is the rate:3, 4,5 or 6 V/ns. Computed and sent to the correct data blocks in phy_reset. Also used in advanced training
uint8
2 4 4
ATTR_CEN_MSS_ALLOW_SINGLE_PORT
TARGET_TYPE_MBA
When this value is true, then mss_eff config will allow a single port to have one dimm and will allow ports to have different sizes. Used in eff_config
uint8
FALSE = 0, TRUE = 1
ATTR_CEN_MSS_DQS_SWIZZLE_TYPE
TARGET_TYPE_MBA
DQS Swizzle type is set by the platform to describe what kind of DQS connection is being used for register acceses. Type 0 is normal, type 1 is for systems with wiring like glacier 1, type 2 is for Pallmeto. Additional types maybe defined if new boards have even different DQS swizzle features
uint8
NORMAL_TYPE_0 = 0, GLACIER_TYPE_1 = 1, ISDIMM_TYPE_2 = 2
ATTR_CEN_MSS_PSRO
TARGET_TYPE_MEMBUF_CHIP
Set by the centaur mss_get_cen_ecid function used diagnostic and chip characterization reporting
uint8
ATTR_CEN_MSS_NWELL_MISPLACEMENT
TARGET_TYPE_MEMBUF_CHIP
Set by the platform depending on DD1 vs DD1.01. If true, then SI settings affected by the NWELL problem are adjusted. Used in eff_config
uint8
FALSE = 0, TRUE = 1
ATTR_CEN_MSS_BLUEWATERFALL_BROKEN
TARGET_TYPE_MEMBUF_CHIP
Set by the platform depending on DD1.0X vs DD1.03 or newer. If true, then draminit_train will modify dqs_clk_ps and gate to work around the issue. Set in get ecid which determines if we are at 1.03
uint8
FALSE = 0, TRUE = 1
ATTR_CEN_MCBIST_PATTERN
TARGET_TYPE_MBA
Enables mcbist data pattern selection.
uint32
ATTR_CEN_MCBIST_TEST_TYPE
TARGET_TYPE_MBA
Enables mcbist test type selection.
uint32
ATTR_CEN_MCBIST_PRINTING_DISABLE
TARGET_TYPE_MBA
MCBIST support for printing
uint8
ATTR_CEN_MCBIST_DATA_ENABLE
TARGET_TYPE_MBA
MCBIST support for enabling data
uint8
ATTR_CEN_MCBIST_USER_RANK
TARGET_TYPE_MBA
MCBIST support for rank selection
uint8
ATTR_CEN_MCBIST_USER_BANK
TARGET_TYPE_MBA
MCBIST support for bank selection
uint8
ATTR_CEN_SCHMOO_MULTIPLE_SETUP_CALL
TARGET_TYPE_MBA
MCBIST for multiple setup
uint8
ATTR_CEN_LRDIMM_RANK_MULT_MODE
TARGET_TYPE_MBA
LRDIMM rank multiplication mode.
Will be set at an MBA level with one policy to be used
uint8
NORMAL = 0, 2X_MULT = 2, 4X_MULT = 4
ATTR_CEN_MSS_THROTTLE_CONTROL_RAS_WEIGHT
TARGET_TYPE_MBA
RAS weight to use for memory throttle control - set in thermal procedures
uint8
ATTR_CEN_MSS_THROTTLE_CONTROL_CAS_WEIGHT
TARGET_TYPE_MBA
CAS weight to use for memory throttle control - set in thermal procedures
uint8
ATTR_CEN_MCBIST_RANDOM_SEED_VALUE
TARGET_TYPE_MBA
Controls the MCBIST engine in the centaur chip. The value will be set in mss_eff_config_shmoo.
uint32
ATTR_CEN_MCBIST_RANDOM_SEED_TYPE
TARGET_TYPE_MBA
Controls the MCBIST engine in the centaur chip. The value will be set in mss_eff_config_shmoo.
uint8
ATTR_CEN_MSS_INIT_STATE
TARGET_TYPE_MEMBUF_CHIP
How far into the ipl istep the centaur has been brought up
COLD = 0, CLOCKS_ON = 1, DMI_ACTIVE = 2
uint8
ATTR_CEN_MSS_EFF_VPD_VERSION
TARGET_TYPE_MBA
The lowest VPD Version of the DIMMs attached to the MBA. Comes directly (in ASCII) of the VINI VZ keyword
uint32
ATTR_CEN_MSS_NEST_CAPABLE_FREQUENCIES
TARGET_TYPE_MEMBUF_CHIP
The NEST frequencies the memory chip can run at computed by the mss_freq. The possibilities are ORed together. The platform uses these value and the MRW to determine what frequency to boot the fabric (nest) if it can. There are two values: 8G and 9.6G
uint8
NONE = 0, 8_0G = 1, 9_6G = 2, 8_0G_OR_9_6G = 3
ATTR_CEN_MRW_STRICT_MBA_PLUG_RULE_CHECKING
TARGET_TYPE_SYSTEM
The MRW for a system should set this to TRUE for systems that must obey plug rules. Lab environments should default this to off and allow the user to override using normal methods to test.
uint8
FALSE = 0, TRUE = 1
ATTR_CEN_MRW_CDIMM_MASTER_I2C_TEMP_SENSOR_ENABLE
TARGET_TYPE_SYSTEM
Used for Custom DIMMs to not enable the reading of the dimm temperature sensor on the master i2c bus
uint8
OFF = 0, ON = 1
ATTR_CEN_MRW_CDIMM_SPARE_I2C_TEMP_SENSOR_ENABLE
TARGET_TYPE_SYSTEM
Used for Custom DIMMs to not enable the reading of the dimm temperature sensor on the spare i2c bus
uint8
OFF = 0, ON = 1
ATTR_CEN_MRW_THERMAL_MEMORY_POWER_LIMIT
TARGET_TYPE_SYSTEM
Machine Readable Workbook Thermal Memory Power Limit
uint32
ATTR_CEN_MRW_POWER_CONTROL_REQUESTED
TARGET_TYPE_SYSTEM
Capable power control settings. In MRW.
uint8
OFF = 0x00, SLOWEXIT = 0x01, FASTEXIT = 0x02
ATTR_CEN_MSS_DDR3_VDDR_SLOPE
TARGET_TYPE_MEMBUF_CHIP
Slope value used to determine the dynamic VID DDR3 VDDR adjustment for all parts. In uV/Centaur.
uint32
0x000000FA
ATTR_CEN_MSS_DDR3_VDDR_INTERCEPT
TARGET_TYPE_MEMBUF_CHIP
Intercept value used to determine the dynamic VID DDR3 VDDR adjustment for all parts. In mV.
uint32
0x00000556
ATTR_CEN_MSS_DDR4_VDDR_SLOPE
TARGET_TYPE_MEMBUF_CHIP
Slope value used to determine the dynamic VID DDR3 VDDR adjustment for all parts. In uV/Centaur.
uint32
0x000000FA
ATTR_CEN_MSS_DDR4_VDDR_INTERCEPT
TARGET_TYPE_MEMBUF_CHIP
Intercept value used to determine the dynamic VID DDR3 VDDR adjustment for all parts. In mV.
uint32
0x000004C4
ATTR_CEN_MSS_VOLT_OVERRIDE
TARGET_TYPE_MEMBUF_CHIP
Possible DRAM voltage override.
uint8
NONE = 0x00, VOLT_135 = 0x01, VOLT_120 = 0x02
ATTR_CEN_MSS_VOLT_COMPLIANT_DIMMS
TARGET_TYPE_SYSTEM
List of Voltages that are compliant with the system. DIMMs that do not have voltages listed in their SPD as supported are errored out. Procedure defined is currently 1.2V and 1.35V only.
uint8
PROCEDURE_DEFINED = 0x00, ALL_VOLTAGES = 0x01
ATTR_CEN_MRW_MCS_PREFETCH_RETRY_THRESHOLD
TARGET_TYPE_SYSTEM
Option to control MCS prefetch retry threshold, for performance optimization. This attribute controls the number of retries in the prefetch engine. Retry threshold available ranges from 16 to 30. Note: Values outside those ranges will default to 30. In MRW.
uint8
ATTR_CEN_MSS_VDDR_OFFSET
TARGET_TYPE_MEMBUF_CHIP
Dynamic VID offset applied to VDDR. In mV.
uint32
ATTR_CEN_VPD_ISDIMMTOC4DQ
TARGET_TYPE_MEMBUF_CHIP
ISDIMM DQ mapping that comes from QX keyword on the CDIMM VPD.
uint8
4 80
ATTR_CEN_VPD_ISDIMMTOC4DQS
TARGET_TYPE_MEMBUF_CHIP
ISDIMM DQQ mapping that comes from QS keyword on the CDIMM VPD.
uint8
4 20
ATTR_CEN_MRW_DDR3_VDDR_MAX_LIMIT
TARGET_TYPE_MEMBUF_CHIP
Maximum voltage limit for the dynamic VID DDR3 VDDR voltage setpoint. In mV.
uint32
0x00000591
ATTR_CEN_MRW_DDR4_VDDR_MAX_LIMIT
TARGET_TYPE_MEMBUF_CHIP
Maximum voltage limit for the dynamic VID DDR4 VDDR voltage setpoint. In mV.
uint32
0x000004f6
ATTR_MRW_MEM_SENSOR_CACHE_ADDR_MAP
TARGET_TYPE_MEMBUF_CHIP
Machine Readable Workbook value detailing the wiring of the 8 dimm temperature sensors for non custom dimms, in DIMM A0,A1,B0,B1,C0,C1,D0,D1 order. One nibble per sensor where bit0 (MSB) is the i2c bus the sensor is attached to (0 for master, 1 for spare) and bits 1:3 are for A2,A1,A0 of the sensor i2c address (where A2 is MSB)
uint32
ATTR_CEN_MRW_WR_VREF_CHECK_VREF_STEP_SIZE
TARGET_TYPE_SYSTEM
Machine Readable Workbook attribute that holds the step size of the VREF when doing a box shmoo
uint8