ATTR_CEN_CENTAUR_EC_FEATURE_ENABLE_RCE_WITH_OTHER_ERRORS_HW246685 TARGET_TYPE_MEMBUF_CHIP Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE. If true, it allow RCE to be reported even if we also have chip marks or symbol marks in place. MBSTR(60)=1 and MBSECC(16)=1, DD2 is set. ENUM_ATTR_NAME_CENTAUR 0x20 GREATER_THAN_OR_EQUAL ATTR_CEN_CENTAUR_EC_FEATURE_BLUEWATERFALL_NWELL_BROKEN_CHECK_FLAG TARGET_TYPE_MEMBUF_CHIP Set by the platform depending on DD1.0 (TRUE), otherwise FALSE. If true, subversion will be checked in mss_get_cen_ecid.C to determine if changes need to be made to the transistor misplaced in the nwell. ENUM_ATTR_NAME_CENTAUR 0x10 EQUAL ATTR_CEN_CENTAUR_EC_FEATURE_MSS_CONTINUE_ON_DP18_PLL_LOCK_FAIL TARGET_TYPE_MEMBUF_CHIP Controls the ddr_phy_reset procedure. When set to TRUE, the procedure will continue with processing other DP18 blocks, if one fails. In DD2, this attribute must be set to false so that the failing hardware (centaur) is marked as bad and not the DIMM. Set by firwmare using the EC level or by a MRW ENUM_ATTR_NAME_CENTAUR 0x10 EQUAL ATTR_CEN_CENTAUR_EC_FEATURE_CHECK_L4_CACHE_ENABLE_UNKNOWN TARGET_TYPE_MEMBUF_CHIP If true then mss_get_cen_ecid needs to read an ECBIT from the ECID in order to determine if the L4 Cache Enable data in the ECID is in an unknown state. This is true for Centaur 1.* ENUM_ATTR_NAME_CENTAUR 0x20 LESS_THAN ATTR_CEN_CENTAUR_EC_FEATURE_ECID_CONTAINS_PORT_LOGIC_BAD_INDICATION TARGET_TYPE_MEMBUF_CHIP If true then mss_get_cen_ecid reads the ECID bits to determine if logic on either of the ports are good. For DD2, these bits are not used for this purpose and so the check is not made. This is true for Centaur 1.* ENUM_ATTR_NAME_CENTAUR 0x20 LESS_THAN ATTR_CEN_CENTAUR_EC_FEATURE_MCBIST_RANDOM_ADDRESS TARGET_TYPE_MEMBUF_CHIP Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE. If false, this will enable workaround for start and end counters for Random Addressing. ENUM_ATTR_NAME_CENTAUR 0x20 GREATER_THAN_OR_EQUAL ATTR_CEN_CENTAUR_EC_FEATURE_HW217608_MBSPA_0_CMD_COMPLETE_ATTN_FIXED TARGET_TYPE_MEMBUF_CHIP Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE. If true, MBSPA bit 8 is masked, and MBSPA bit 0 is unmasked and configured to report when maint cmd either stops clean or stops on error. Otherwise, MBSPA bit 0 is masked, and MBSPA bit 8 is unmasked. NOTE: For DD1 when using MBSPA bit 8, a scan init is needed to enable the WAT workaround allows bit 8 to report when maint cmd either stops clean or stops on error. The scan init is enabled for DD1 and disabled for DD2, but does not use this same attribute. ENUM_ATTR_NAME_CENTAUR 0x20 GREATER_THAN_OR_EQUAL ATTR_CEN_CENTAUR_EC_FEATURE_ENABLE_SAFEMODE_THROTTLE TARGET_TYPE_MEMBUF_CHIP Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE. If true, this will enable safe mode throttle values to be set during the IPL in mss_thermal_init. ENUM_ATTR_NAME_CENTAUR 0x20 GREATER_THAN_OR_EQUAL ATTR_CEN_CENTAUR_EC_FEATURE_DD2_FIR_BIT_DEFN_CHANGES TARGET_TYPE_MEMBUF_CHIP Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE. If true, mss_unmask_errors.C will use the DD2 FIR bit definitions when setting FIR action regs and masks. ENUM_ATTR_NAME_CENTAUR 0x20 GREATER_THAN_OR_EQUAL ATTR_CEN_CENTAUR_EC_FEATURE_RDCLK_PR_UPDATE_HW236658_FIXED TARGET_TYPE_MEMBUF_CHIP Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE. If false, draminit_mc will execute a putscom to set bit 52 (PER_RDCLK_UPDATE_DISABLE) of DP18 Read Diag Cfg 5 on DD1.X parts. ENUM_ATTR_NAME_CENTAUR 0x20 GREATER_THAN_OR_EQUAL ATTR_CEN_CENTAUR_EC_FEATURE_DD2_ENABLE_EXIT_POINT_1 TARGET_TYPE_MEMBUF_CHIP Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE. If true, exit point 1 will be enabled if any mark in markstore. ENUM_ATTR_NAME_CENTAUR 0x20 GREATER_THAN_OR_EQUAL ATTR_CEN_CENTAUR_EC_FEATURE_DISABLE_VDDR_DYNAMIC_VID TARGET_TYPE_MEMBUF_CHIP Set by the platform depending on EC less than DD2.0 (TRUE), otherwise FALSE. If true, mss_volt_vddr_offset will use the value from mss_volt instead of the calculated dynamic vid value, even if vddr dynamic vid is enabled in the MRW. Centaur DD1.X chips need vmem voltage to be at 1.35V. ENUM_ATTR_NAME_CENTAUR 0x20 LESS_THAN ATTR_CEN_CENTAUR_EC_FEATURE_SUPPORTED TARGET_TYPE_MEMBUF_CHIP Set by platform. If true, Centaur level is supported. ENUM_ATTR_NAME_CENTAUR 0x20 GREATER_THAN_OR_EQUAL