# Force DJVPD read/write to use EEPROM layer instead of VPD cache 
set DJVPD_READ_FROM_HW
set DJVPD_WRITE_TO_HW
unset DJVPD_READ_FROM_PNOR
unset DJVPD_WRITE_TO_PNOR

# Force MEMVPD read/write to PNOR ( No actual hardware )
set MEMVPD_READ_FROM_PNOR
set MEMVPD_WRITE_TO_PNOR
unset MEMVPD_READ_FROM_HW
unset MEMVPD_WRITE_TO_HW

# Force MVPD read/write to use EEPROM layer instead of VPD cache
# (not working because shoddy MVPD currently)
#set MVPD_READ_FROM_HW
#set MVPD_WRITE_TO_HW
set MVPD_READ_FROM_PNOR
set MVPD_WRITE_TO_PNOR


#skip enabling checkstop analysis until OCC is ready in simics
unset IPLTIME_CHECKSTOP_ANALYSIS

#enable EEPROM caching
set SUPPORT_EEPROM_CACHING

#run cxx testcases during boot
set EARLY_TESTCASES

#Try to keep a list of things this does
# - skipping setting voltages in istep 8.12, nothing on other side of AVSbus
#   in simics currently.
set AXONE_BRING_UP

# Set this to pull in Axone on code (such as P9A/EXP MSS code)
set AXONE