From fc433c65ca76105816ffe39bffc7f5d23345104b Mon Sep 17 00:00:00 2001 From: Dan Crowell Date: Tue, 1 May 2012 15:14:05 -0500 Subject: Pick up Simics FSI fixes for multiple chips Updating the Simics level to get FSI fixes to allow multiple chips to work. This also allows us to remove some previous workarounds. The new Simics build pulled in a different PNOR so needed to disable some of the tests. The new Simics build also modified some of the L3 objects so changes were required to some debug tools. Had to update the VENICE config since Ched rewired it to look like MURANO/Tuleta. Testing: Verified 2-proc, 4-centaur MURANO config Verified 2-proc, 4-centaur VENICE config Change-Id: I6aaaf8aad2f82dbfffb8ade551d545bedaa3e048 RTC: 41305 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1066 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III --- src/build/citest/autocitest | 3 +- src/build/citest/etc/bbuild | 2 +- src/build/citest/etc/workarounds.postsimsetup | 30 +++ src/build/citest/etc/workarounds.presimsetup | 22 -- src/build/debug/simics-debug-framework.py | 2 +- src/build/simics/hb-simdebug.py | 2 +- src/build/simics/post_model_hook.simics | 4 - src/include/kernel/cpumgr.H | 2 +- src/usr/hwas/plat/hwasPlat.C | 10 +- src/usr/scom/test/scomtest.H | 67 ++++- .../common/xmltohb/simics_VENICE.system.xml | 275 +++++++++++---------- src/usr/targeting/test/testtargeting.H | 2 +- 12 files changed, 243 insertions(+), 178 deletions(-) (limited to 'src') diff --git a/src/build/citest/autocitest b/src/build/citest/autocitest index bd41cfccd..cc49290ea 100755 --- a/src/build/citest/autocitest +++ b/src/build/citest/autocitest @@ -107,6 +107,7 @@ fi ## set up ## DRIVER="$1" ## backing tree +export bb=$DRIVER ## simulate a workon TEST_SANDBOX="$2" ## test sandbox HBICORE_TEST="$3" ## path to hbicore_test.img @@ -387,7 +388,7 @@ tracecalls=`cat $SBXHOME/tracecalls.log | xargs echo -n` echo "====> dump printk buffer..." -autosim $NOWIN --simcmd "memory_image_ln0.save ${SBXHOME}/testprintk.log 0x$printk_buffer_addr 0x$printk_buffer_size" 1> /dev/null 2> /dev/null +autosim $NOWIN --simcmd "p8Proc0.l3_cache_image.save ${SBXHOME}/testprintk.log 0x$printk_buffer_addr 0x$printk_buffer_size" 1> /dev/null 2> /dev/null if [ $? -ne 0 ] ; then echo "ERROR: Unable to run $?" stopsim diff --git a/src/build/citest/etc/bbuild b/src/build/citest/etc/bbuild index f832afe05..588c3b8b7 100644 --- a/src/build/citest/etc/bbuild +++ b/src/build/citest/etc/bbuild @@ -1 +1 @@ -/esw/fips810/Builds/b0419a_1215.810 +/esw/fips810/Builds/b0510a_1219.810 diff --git a/src/build/citest/etc/workarounds.postsimsetup b/src/build/citest/etc/workarounds.postsimsetup index 9d27730f7..821b936fa 100755 --- a/src/build/citest/etc/workarounds.postsimsetup +++ b/src/build/citest/etc/workarounds.postsimsetup @@ -27,7 +27,37 @@ ## to setup the sandbox ## +##### echo "+++ Point Simics to our base image +++" #ln -sf $sb/../img/hbicore.bin $sb/../simics/hostboot.bin mkdir -p $sb/../images/ppc/lab/flash/ ln -sf $sb/../img/hbicore.bin $sb/../images/ppc/lab/flash/hostboot.bin +##### + +##### +#@fixme - Fix with RTC:41342 +echo "+++ Copy centaur.act" +mkdir -p $sb/simu/data/cec-chip +cp $HOSTBOOTROOT/src/build/citest/etc/patches/centaur.act $sb/simu/data/cec-chip/centaur.act +##### + +##### +#@fixme - Fix with RTC:41342 +echo "+++ Update Model EC." +mkdir -p $sb/simu/configs/ + +cp --update $bb/src/simu/configs/P8_MURANO.config $sb/simu/configs/P8_MURANO.config +sed -i -e's/SETENV GFW_P8_MURANO_PROC_MODEL_EC.*/SETENV GFW_P8_MURANO_PROC_MODEL_EC 910623/' $sb/simu/configs/P8_MURANO.config +sed -i -e's/SETENV GFW_P8_MURANO_CENTAUR_MODEL_EC.*/SETENV GFW_P8_MURANO_CENTAUR_MODEL_EC 910610/' $sb/simu/configs/P8_MURANO.config + +cp --update $bb/src/simu/configs/P8_VENICE.config $sb/simu/configs/P8_VENICE.config +sed -i -e's/SETENV GFW_P8_VENICE_PROC_MODEL_EC.*/SETENV GFW_P8_VENICE_PROC_MODEL_EC 910623/' $sb/simu/configs/P8_VENICE.config +##### + +##### +#@fixme - Fix with RTC:41205 +echo "+++ Fix centaur aliases in p8.act (SW141619) +++" +mkdir -p $sb/simu/data/cec-chip/ +cp --update $bb/src/simu/data/cec-chip/p8.act $sb/simu/data/cec-chip/ +sed -i -e's/mycentaur/mymcPort/' $sb/simu/data/cec-chip/p8.act +##### diff --git a/src/build/citest/etc/workarounds.presimsetup b/src/build/citest/etc/workarounds.presimsetup index 265862240..d8616729f 100755 --- a/src/build/citest/etc/workarounds.presimsetup +++ b/src/build/citest/etc/workarounds.presimsetup @@ -27,28 +27,6 @@ ## to setup the sandbox ## -echo "+++ Copy centaur.act" -mkdir -p $sb/simu/data/cec-chip -cp $HOSTBOOTROOT/src/build/citest/etc/patches/centaur.act $sb/simu/data/cec-chip/centaur.act - -echo "+++ Copy desired config file to sandbox and modify Model EC." -mkdir -p $sb/simu/configs -cp --update $BACKING_BUILD/src/simu/configs/P8_MURANO.config $sb/simu/configs -cp --update $BACKING_BUILD/src/simu/configs/P8_VENICE.config $sb/simu/configs -sed -i -e's/SETENV GFW_P8_MURANO_PROC_MODEL_EC.*/SETENV GFW_P8_MURANO_PROC_MODEL_EC 910623/' $sb/simu/configs/P8_MURANO.config -sed -i -e's/SETENV GFW_P8_MURANO_CENTAUR_MODEL_EC.*/SETENV GFW_P8_MURANO_CENTAUR_MODEL_EC 910610/' $sb/simu/configs/P8_MURANO.config -sed -i -e's/SETENV GFW_P8_VENICE_PROC_MODEL_EC.*/SETENV GFW_P8_VENICE_PROC_MODEL_EC 910623/' $sb/simu/configs/P8_VENICE.config - -echo "+++ Enable 8-threads." -sed -i -e's/SETENV GFW_SIMICS_ENV_THREADS_PER_CORE.*/SETENV GFW_SIMICS_ENV_THREADS_PER_CORE 8/' $sb/simu/configs/P8_VENICE.config -sed -i -e's/SETENV GFW_SIMICS_ENV_THREADS_PER_CORE.*/SETENV GFW_SIMICS_ENV_THREADS_PER_CORE 8/' $sb/simu/configs/P8_MURANO.config - -#Remove with RTC:40975 -echo "+++ Update to new phyp level for XSCOM fixes." -mkdir -p $sb/simu/data -cp --update $BACKING_BUILD/src/simu/data/simicsInfo $sb/simu/data/simicsInfo -sed -i -e's/^WSALIAS DEFAULT PHYPLEVEL.*/WSALIAS DEFAULT PHYPLEVEL env\/phypb\/simics-4.2.0\/simics-4.2.85\/ph120424b700.42/' $sb/simu/data/simicsInfo - #### Examples #### #echo "+++ Some message about why you need to do this." diff --git a/src/build/debug/simics-debug-framework.py b/src/build/debug/simics-debug-framework.py index edf5f0bdd..682c8aa56 100755 --- a/src/build/debug/simics-debug-framework.py +++ b/src/build/debug/simics-debug-framework.py @@ -399,7 +399,7 @@ def magic_instruction_callback(user_arg, cpu, arg): # fsp-trace style. writeLongLong(tracBinaryInfoAddr+8,1) # Save the tracBinary buffer to a file named tracBINARY in current dir - saveCommand = "memory_image_ln0.save tracBINARY 0x%x %d"%(pTracBinaryBuffer,cbUsed) + saveCommand = "p8Proc0.l3_cache_image.save tracBINARY 0x%x %d"%(pTracBinaryBuffer,cbUsed) SIM_run_alone(run_command, saveCommand ) # Run fsp-trace on tracBINARY file (implied), append output to tracMERG os.system( "fsp-trace ./ -s hbotStringFile >>tracMERG 2>/dev/null" ) diff --git a/src/build/simics/hb-simdebug.py b/src/build/simics/hb-simdebug.py index 9b779dd67..7041bd2e5 100755 --- a/src/build/simics/hb-simdebug.py +++ b/src/build/simics/hb-simdebug.py @@ -44,7 +44,7 @@ def dumpL3(): #print t #dump L3 to hbdump. - string = "memory_image_ln0.save hbdump.%s 0 0x%x"%(t, L3_SIZE) + string = "p8Proc0.l3_cache_image.save hbdump.%s 0 0x%x"%(t, L3_SIZE) #print string result = run_command(string) #print result diff --git a/src/build/simics/post_model_hook.simics b/src/build/simics/post_model_hook.simics index f2705f615..656b55b8e 100755 --- a/src/build/simics/post_model_hook.simics +++ b/src/build/simics/post_model_hook.simics @@ -49,7 +49,3 @@ venice_cec_chip_cmp0.psi_hb->psihb_xivr_fsi=0x0140000000 #02010917 venice_cec_chip_cmp0.psi_hb->psihb_irsn=0x00030000FFFF0000 #0201091b p8Proc0.proc_fsi2host_mbox->responder_enable=1 -#@fixme - Remove with RTC:41070 -#Get the OCC scoms to work correctly -p8Proc0.occ_scom_bridge->occ_pib=p8Proc0.OccComplexSlot.OccSimpleSlot.pcb_space -p8Proc0.OccComplexSlot.OccSimpleSlot.ocb->trusted_boot=FALSE diff --git a/src/include/kernel/cpumgr.H b/src/include/kernel/cpumgr.H index 4374d50a0..589eb385c 100644 --- a/src/include/kernel/cpumgr.H +++ b/src/include/kernel/cpumgr.H @@ -34,7 +34,7 @@ class CpuManager enum { MAXCPUS = KERNEL_MAX_SUPPORTED_CPUS, - CPU_PERIODIC_CHECK_MEMORY = 32, + CPU_PERIODIC_CHECK_MEMORY = 16, CPU_PERIODIC_FLUSH_PAGETABLE = 256, CPU_PERIODIC_DEFRAG = 949, // TODO Any bigger not currently hit }; diff --git a/src/usr/hwas/plat/hwasPlat.C b/src/usr/hwas/plat/hwasPlat.C index 0af9a7ace..365101081 100644 --- a/src/usr/hwas/plat/hwasPlat.C +++ b/src/usr/hwas/plat/hwasPlat.C @@ -108,7 +108,7 @@ errlHndl_t platPresenceDetect(TargetHandleList &io_targets) if (errl != NULL) { // errl was set - this is an error condition. - HWAS_ERR( "pTarget %x (%p) - failed presence detect", + HWAS_ERR( "pTarget %.8X (%p) - failed presence detect", pTarget->getAttr(), pTarget); // commit the error but keep going @@ -116,7 +116,7 @@ errlHndl_t platPresenceDetect(TargetHandleList &io_targets) // errl is now NULL // chip not present -- remove from list - HWAS_DBG( "pTarget %x (%p) - no presence", + HWAS_DBG( "pTarget %.8X (%p) - no presence", pTarget->getAttr(), pTarget); // erase this target, and 'increment' to next @@ -128,15 +128,15 @@ errlHndl_t platPresenceDetect(TargetHandleList &io_targets) if (present == true) { - HWAS_DBG( "pTarget %x (%p) - detected present", - pTarget->getAttr(), pTarget); + HWAS_DBG( "pTarget %.8X (%p) - detected present", + pTarget->getAttr(), pTarget); // advance to next entry in the list pTarget_it++; } else { // chip not present -- remove from list - HWAS_DBG( "pTarget %x (%p) - no presence", + HWAS_DBG( "pTarget %.8X (%p) - no presence", pTarget->getAttr(), pTarget); // erase this target, and 'increment' to next diff --git a/src/usr/scom/test/scomtest.H b/src/usr/scom/test/scomtest.H index 7d92c0a7b..e30770326 100644 --- a/src/usr/scom/test/scomtest.H +++ b/src/usr/scom/test/scomtest.H @@ -203,7 +203,15 @@ public: // Setup some targets to use enum { CENTAUR0, //local + CENTAUR1, //local + CENTAUR2, //local + CENTAUR3, //local + CENTAUR4, //local + CENTAUR5, //local + CENTAUR6, //local + CENTAUR7, //local CENTAUR8, //remote (off PROC1) + CENTAUR9, //remote (off PROC1) NUM_TARGETS }; TARGETING::Target* scom_targets[NUM_TARGETS]; @@ -224,6 +232,31 @@ public: epath.addLast(TARGETING::TYPE_MEMBUF,8); scom_targets[CENTAUR8] = TARGETING::targetService().toTarget(epath); + epath.removeLast(); + epath.addLast(TARGETING::TYPE_MEMBUF,1); + scom_targets[CENTAUR1] = TARGETING::targetService().toTarget(epath); + epath.removeLast(); + epath.addLast(TARGETING::TYPE_MEMBUF,2); + scom_targets[CENTAUR2] = TARGETING::targetService().toTarget(epath); + epath.removeLast(); + epath.addLast(TARGETING::TYPE_MEMBUF,3); + scom_targets[CENTAUR3] = TARGETING::targetService().toTarget(epath); + epath.removeLast(); + epath.addLast(TARGETING::TYPE_MEMBUF,4); + scom_targets[CENTAUR4] = TARGETING::targetService().toTarget(epath); + epath.removeLast(); + epath.addLast(TARGETING::TYPE_MEMBUF,5); + scom_targets[CENTAUR5] = TARGETING::targetService().toTarget(epath); + epath.removeLast(); + epath.addLast(TARGETING::TYPE_MEMBUF,6); + scom_targets[CENTAUR6] = TARGETING::targetService().toTarget(epath); + epath.removeLast(); + epath.addLast(TARGETING::TYPE_MEMBUF,7); + scom_targets[CENTAUR7] = TARGETING::targetService().toTarget(epath); + epath.removeLast(); + epath.addLast(TARGETING::TYPE_MEMBUF,9); + scom_targets[CENTAUR9] = TARGETING::targetService().toTarget(epath); + for( uint64_t x = 0; x < NUM_TARGETS; x++ ) { //only run if the target exists and has FSI enabled. @@ -261,6 +294,17 @@ public: { scom_targets[CENTAUR0], 0x02011403 , 0x1234567800000000 }, { scom_targets[CENTAUR0], 0x02011672 , 0x1122334455667788 }, { scom_targets[CENTAUR8], 0x02011672 , 0x9E9E9E9E9E9E9E9E }, + + { scom_targets[CENTAUR0], 0x02011404 , 0x00000000f0f0f0f0 }, + { scom_targets[CENTAUR1], 0x02011404 , 0x1111111100000000 }, + { scom_targets[CENTAUR2], 0x02011404 , 0x2222222200000000 }, + { scom_targets[CENTAUR3], 0x02011404 , 0x3333333300000000 }, + { scom_targets[CENTAUR4], 0x02011404 , 0x4444444400000000 }, + { scom_targets[CENTAUR5], 0x02011404 , 0x5555555500000000 }, + { scom_targets[CENTAUR6], 0x02011404 , 0x6666666600000000 }, + { scom_targets[CENTAUR7], 0x02011404 , 0x7777777700000000 }, + { scom_targets[CENTAUR8], 0x02011404 , 0x8888888800000000 }, + { scom_targets[CENTAUR9], 0x02011404 , 0x9999999900000000 }, }; const uint64_t NUM_ADDRS = sizeof(test_data)/sizeof(test_data[0]); @@ -1165,6 +1209,12 @@ public: { continue; } + // check to see if the target is functional.. if not.. skip this target + else if (test_data[x].target->getAttr().functional != true) + { + TRACDCOMP( g_trac_scom, "ScomTest::test_translate_scom_MBA_MBS> Target %d is not functional", x ); + continue; + } op_size = sizeof(uint64_t); @@ -1352,6 +1402,12 @@ public: { continue; } + // check to see if the target is functional.. if not.. skip this target + else if (test_data[x].target->getAttr().functional != true) + { + TRACDCOMP( g_trac_scom, "ScomTest::test_translate_scom_ABUS> Target %d is not functional", x ); + continue; + } op_size = sizeof(uint64_t); @@ -1493,7 +1549,7 @@ public: { continue; } - // check to see if the target is functional.. if not.. skip this target + // check to see if the target is functional.. if not.. skip this target else if (test_data[x].target->getAttr().functional != true) { TRACDCOMP( g_trac_scom, "ScomTest::test_translate_scom_XBUS> Target %d is not functional", x ); @@ -1538,6 +1594,12 @@ public: { continue; } + // check to see if the target is functional.. if not.. skip this target + else if (test_data[x].target->getAttr().functional != true) + { + TRACDCOMP( g_trac_scom, "ScomTest::test_translate_scom_XBUS> Target %d is not functional", x ); + continue; + } op_size = sizeof(uint64_t); @@ -1572,9 +1634,6 @@ public: //@todo - write error path testcase for FSI scom using bad address - - //@todo - address translation - }; #endif diff --git a/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml b/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml index 85a236eaa..69d56bc03 100644 --- a/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml +++ b/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml @@ -36,6 +36,11 @@ * each Centaur membuf chip has 2 MBA chiplets * each MBA chiplet has 2 ports * each MBA port connects to 2 dimms + + Note that the logical memory connections are very wacky in their + relationship to the FSI ports: + cMFSI Port 0-7 = Logical MCS Port 4,5,6,7,0,1,2,3 + ================================================================= --> @@ -3599,7 +3604,7 @@ FSI_MASTER_PORT - 4 + 7 FSI_SLAVE_CASCADE @@ -4467,7 +4472,7 @@ FSI_MASTER_PORT - 5 + 6 FSI_SLAVE_CASCADE @@ -7040,7 +7045,7 @@ affinity:sys-0/node-0/proc-0/mcs-0/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-0 @@ -7051,7 +7056,7 @@ FSI_MASTER_PORT - 0 + 4 FSI_SLAVE_CASCADE @@ -7147,7 +7152,7 @@ affinity:sys-0/node-0/proc-0/mcs-1/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-0 @@ -7158,7 +7163,7 @@ FSI_MASTER_PORT - 1 + 5 FSI_SLAVE_CASCADE @@ -7236,7 +7241,7 @@ affinity:sys-0/node-0/proc-0/mcs-2/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-0 @@ -7247,7 +7252,7 @@ FSI_MASTER_PORT - 2 + 6 FSI_SLAVE_CASCADE @@ -7325,7 +7330,7 @@ affinity:sys-0/node-0/proc-0/mcs-3/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-0 @@ -7336,7 +7341,7 @@ FSI_MASTER_PORT - 3 + 7 FSI_SLAVE_CASCADE @@ -7414,7 +7419,7 @@ affinity:sys-0/node-0/proc-0/mcs-4/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-0 @@ -7425,7 +7430,7 @@ FSI_MASTER_PORT - 4 + 0 FSI_SLAVE_CASCADE @@ -7503,7 +7508,7 @@ affinity:sys-0/node-0/proc-0/mcs-5/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-0 @@ -7514,7 +7519,7 @@ FSI_MASTER_PORT - 5 + 1 FSI_SLAVE_CASCADE @@ -7592,7 +7597,7 @@ affinity:sys-0/node-0/proc-0/mcs-6/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-0 @@ -7603,7 +7608,7 @@ FSI_MASTER_PORT - 6 + 2 FSI_SLAVE_CASCADE @@ -7681,7 +7686,7 @@ affinity:sys-0/node-0/proc-0/mcs-7/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-0 @@ -7692,7 +7697,7 @@ FSI_MASTER_PORT - 7 + 3 FSI_SLAVE_CASCADE @@ -7770,7 +7775,7 @@ affinity:sys-0/node-0/proc-1/mcs-0/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-1 @@ -7781,7 +7786,7 @@ FSI_MASTER_PORT - 0 + 4 FSI_SLAVE_CASCADE @@ -7859,7 +7864,7 @@ affinity:sys-0/node-0/proc-1/mcs-1/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-1 @@ -7870,7 +7875,7 @@ FSI_MASTER_PORT - 1 + 5 FSI_SLAVE_CASCADE @@ -7948,7 +7953,7 @@ affinity:sys-0/node-0/proc-1/mcs-2/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-1 @@ -7959,7 +7964,7 @@ FSI_MASTER_PORT - 2 + 6 FSI_SLAVE_CASCADE @@ -8037,7 +8042,7 @@ affinity:sys-0/node-0/proc-1/mcs-3/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-1 @@ -8048,7 +8053,7 @@ FSI_MASTER_PORT - 3 + 7 FSI_SLAVE_CASCADE @@ -8126,7 +8131,7 @@ affinity:sys-0/node-0/proc-1/mcs-4/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-1 @@ -8137,7 +8142,7 @@ FSI_MASTER_PORT - 4 + 0 FSI_SLAVE_CASCADE @@ -8215,7 +8220,7 @@ affinity:sys-0/node-0/proc-1/mcs-5/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-1 @@ -8226,7 +8231,7 @@ FSI_MASTER_PORT - 5 + 1 FSI_SLAVE_CASCADE @@ -8304,7 +8309,7 @@ affinity:sys-0/node-0/proc-1/mcs-6/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-1 @@ -8315,7 +8320,7 @@ FSI_MASTER_PORT - 6 + 2 FSI_SLAVE_CASCADE @@ -8393,7 +8398,7 @@ affinity:sys-0/node-0/proc-1/mcs-7/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-1 @@ -8404,7 +8409,7 @@ FSI_MASTER_PORT - 7 + 3 FSI_SLAVE_CASCADE @@ -8482,7 +8487,7 @@ affinity:sys-0/node-0/proc-2/mcs-0/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-2 @@ -8493,7 +8498,7 @@ FSI_MASTER_PORT - 0 + 4 FSI_SLAVE_CASCADE @@ -8571,7 +8576,7 @@ affinity:sys-0/node-0/proc-2/mcs-1/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-2 @@ -8582,7 +8587,7 @@ FSI_MASTER_PORT - 1 + 5 FSI_SLAVE_CASCADE @@ -8660,7 +8665,7 @@ affinity:sys-0/node-0/proc-2/mcs-2/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-2 @@ -8671,7 +8676,7 @@ FSI_MASTER_PORT - 2 + 6 FSI_SLAVE_CASCADE @@ -8749,7 +8754,7 @@ affinity:sys-0/node-0/proc-2/mcs-3/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-2 @@ -8760,7 +8765,7 @@ FSI_MASTER_PORT - 3 + 7 FSI_SLAVE_CASCADE @@ -8838,7 +8843,7 @@ affinity:sys-0/node-0/proc-2/mcs-4/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-2 @@ -8849,7 +8854,7 @@ FSI_MASTER_PORT - 4 + 0 FSI_SLAVE_CASCADE @@ -8927,7 +8932,7 @@ affinity:sys-0/node-0/proc-2/mcs-5/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-2 @@ -8938,7 +8943,7 @@ FSI_MASTER_PORT - 5 + 1 FSI_SLAVE_CASCADE @@ -9016,7 +9021,7 @@ affinity:sys-0/node-0/proc-2/mcs-6/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-2 @@ -9027,7 +9032,7 @@ FSI_MASTER_PORT - 6 + 2 FSI_SLAVE_CASCADE @@ -9105,7 +9110,7 @@ affinity:sys-0/node-0/proc-2/mcs-7/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-2 @@ -9116,7 +9121,7 @@ FSI_MASTER_PORT - 7 + 3 FSI_SLAVE_CASCADE @@ -9194,7 +9199,7 @@ affinity:sys-0/node-0/proc-3/mcs-0/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-3 @@ -9205,7 +9210,7 @@ FSI_MASTER_PORT - 0 + 4 FSI_SLAVE_CASCADE @@ -9283,7 +9288,7 @@ affinity:sys-0/node-0/proc-3/mcs-1/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-3 @@ -9294,7 +9299,7 @@ FSI_MASTER_PORT - 1 + 5 FSI_SLAVE_CASCADE @@ -9372,7 +9377,7 @@ affinity:sys-0/node-0/proc-3/mcs-2/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-3 @@ -9383,7 +9388,7 @@ FSI_MASTER_PORT - 2 + 6 FSI_SLAVE_CASCADE @@ -9461,7 +9466,7 @@ affinity:sys-0/node-0/proc-3/mcs-3/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-3 @@ -9472,7 +9477,7 @@ FSI_MASTER_PORT - 3 + 7 FSI_SLAVE_CASCADE @@ -9550,7 +9555,7 @@ affinity:sys-0/node-0/proc-3/mcs-4/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-3 @@ -9561,7 +9566,7 @@ FSI_MASTER_PORT - 4 + 0 FSI_SLAVE_CASCADE @@ -9639,7 +9644,7 @@ affinity:sys-0/node-0/proc-3/mcs-5/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-3 @@ -9650,7 +9655,7 @@ FSI_MASTER_PORT - 5 + 1 FSI_SLAVE_CASCADE @@ -9728,7 +9733,7 @@ affinity:sys-0/node-0/proc-3/mcs-6/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-3 @@ -9739,7 +9744,7 @@ FSI_MASTER_PORT - 6 + 2 FSI_SLAVE_CASCADE @@ -9817,7 +9822,7 @@ affinity:sys-0/node-0/proc-3/mcs-7/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-3 @@ -9828,7 +9833,7 @@ FSI_MASTER_PORT - 7 + 3 FSI_SLAVE_CASCADE @@ -9906,7 +9911,7 @@ affinity:sys-0/node-0/proc-4/mcs-0/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-4 @@ -9917,7 +9922,7 @@ FSI_MASTER_PORT - 0 + 4 FSI_SLAVE_CASCADE @@ -9995,7 +10000,7 @@ affinity:sys-0/node-0/proc-4/mcs-1/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-4 @@ -10006,7 +10011,7 @@ FSI_MASTER_PORT - 1 + 5 FSI_SLAVE_CASCADE @@ -10084,7 +10089,7 @@ affinity:sys-0/node-0/proc-4/mcs-2/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-4 @@ -10095,7 +10100,7 @@ FSI_MASTER_PORT - 2 + 6 FSI_SLAVE_CASCADE @@ -10173,7 +10178,7 @@ affinity:sys-0/node-0/proc-4/mcs-3/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-4 @@ -10184,7 +10189,7 @@ FSI_MASTER_PORT - 3 + 7 FSI_SLAVE_CASCADE @@ -10262,7 +10267,7 @@ affinity:sys-0/node-0/proc-4/mcs-4/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-4 @@ -10273,7 +10278,7 @@ FSI_MASTER_PORT - 4 + 0 FSI_SLAVE_CASCADE @@ -10351,7 +10356,7 @@ affinity:sys-0/node-0/proc-4/mcs-5/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-4 @@ -10362,7 +10367,7 @@ FSI_MASTER_PORT - 5 + 1 FSI_SLAVE_CASCADE @@ -10440,7 +10445,7 @@ affinity:sys-0/node-0/proc-4/mcs-6/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-4 @@ -10451,7 +10456,7 @@ FSI_MASTER_PORT - 6 + 2 FSI_SLAVE_CASCADE @@ -10529,7 +10534,7 @@ affinity:sys-0/node-0/proc-4/mcs-7/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-4 @@ -10540,7 +10545,7 @@ FSI_MASTER_PORT - 7 + 3 FSI_SLAVE_CASCADE @@ -10618,7 +10623,7 @@ affinity:sys-0/node-0/proc-5/mcs-0/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-5 @@ -10629,7 +10634,7 @@ FSI_MASTER_PORT - 0 + 4 FSI_SLAVE_CASCADE @@ -10707,7 +10712,7 @@ affinity:sys-0/node-0/proc-5/mcs-1/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-5 @@ -10718,7 +10723,7 @@ FSI_MASTER_PORT - 1 + 5 FSI_SLAVE_CASCADE @@ -10796,7 +10801,7 @@ affinity:sys-0/node-0/proc-5/mcs-2/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-5 @@ -10807,7 +10812,7 @@ FSI_MASTER_PORT - 2 + 6 FSI_SLAVE_CASCADE @@ -10885,7 +10890,7 @@ affinity:sys-0/node-0/proc-5/mcs-3/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-5 @@ -10896,7 +10901,7 @@ FSI_MASTER_PORT - 3 + 7 FSI_SLAVE_CASCADE @@ -10974,7 +10979,7 @@ affinity:sys-0/node-0/proc-5/mcs-4/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-5 @@ -10985,7 +10990,7 @@ FSI_MASTER_PORT - 4 + 0 FSI_SLAVE_CASCADE @@ -11063,7 +11068,7 @@ affinity:sys-0/node-0/proc-5/mcs-5/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-5 @@ -11074,7 +11079,7 @@ FSI_MASTER_PORT - 5 + 1 FSI_SLAVE_CASCADE @@ -11152,7 +11157,7 @@ affinity:sys-0/node-0/proc-5/mcs-6/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-5 @@ -11163,7 +11168,7 @@ FSI_MASTER_PORT - 6 + 2 FSI_SLAVE_CASCADE @@ -11241,7 +11246,7 @@ affinity:sys-0/node-0/proc-5/mcs-7/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-5 @@ -11252,7 +11257,7 @@ FSI_MASTER_PORT - 7 + 3 FSI_SLAVE_CASCADE @@ -11330,7 +11335,7 @@ affinity:sys-0/node-0/proc-6/mcs-0/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-6 @@ -11341,7 +11346,7 @@ FSI_MASTER_PORT - 0 + 4 FSI_SLAVE_CASCADE @@ -11419,7 +11424,7 @@ affinity:sys-0/node-0/proc-6/mcs-1/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-6 @@ -11430,7 +11435,7 @@ FSI_MASTER_PORT - 1 + 5 FSI_SLAVE_CASCADE @@ -11508,7 +11513,7 @@ affinity:sys-0/node-0/proc-6/mcs-2/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-6 @@ -11519,7 +11524,7 @@ FSI_MASTER_PORT - 2 + 6 FSI_SLAVE_CASCADE @@ -11597,7 +11602,7 @@ affinity:sys-0/node-0/proc-6/mcs-3/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-6 @@ -11608,7 +11613,7 @@ FSI_MASTER_PORT - 3 + 7 FSI_SLAVE_CASCADE @@ -11686,7 +11691,7 @@ affinity:sys-0/node-0/proc-6/mcs-4/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-6 @@ -11697,7 +11702,7 @@ FSI_MASTER_PORT - 4 + 0 FSI_SLAVE_CASCADE @@ -11775,7 +11780,7 @@ affinity:sys-0/node-0/proc-6/mcs-5/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-6 @@ -11786,7 +11791,7 @@ FSI_MASTER_PORT - 5 + 1 FSI_SLAVE_CASCADE @@ -11864,7 +11869,7 @@ affinity:sys-0/node-0/proc-6/mcs-6/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-6 @@ -11875,7 +11880,7 @@ FSI_MASTER_PORT - 6 + 2 FSI_SLAVE_CASCADE @@ -11953,7 +11958,7 @@ affinity:sys-0/node-0/proc-6/mcs-7/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-6 @@ -11964,7 +11969,7 @@ FSI_MASTER_PORT - 7 + 3 FSI_SLAVE_CASCADE @@ -12042,7 +12047,7 @@ affinity:sys-0/node-0/proc-7/mcs-0/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-7 @@ -12053,7 +12058,7 @@ FSI_MASTER_PORT - 0 + 4 FSI_SLAVE_CASCADE @@ -12131,7 +12136,7 @@ affinity:sys-0/node-0/proc-7/mcs-1/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-7 @@ -12142,7 +12147,7 @@ FSI_MASTER_PORT - 1 + 5 FSI_SLAVE_CASCADE @@ -12220,7 +12225,7 @@ affinity:sys-0/node-0/proc-7/mcs-2/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-7 @@ -12231,7 +12236,7 @@ FSI_MASTER_PORT - 2 + 6 FSI_SLAVE_CASCADE @@ -12309,7 +12314,7 @@ affinity:sys-0/node-0/proc-7/mcs-3/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-7 @@ -12320,7 +12325,7 @@ FSI_MASTER_PORT - 3 + 7 FSI_SLAVE_CASCADE @@ -12398,7 +12403,7 @@ affinity:sys-0/node-0/proc-7/mcs-4/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-7 @@ -12409,7 +12414,7 @@ FSI_MASTER_PORT - 4 + 0 FSI_SLAVE_CASCADE @@ -12487,7 +12492,7 @@ affinity:sys-0/node-0/proc-7/mcs-5/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-7 @@ -12498,7 +12503,7 @@ FSI_MASTER_PORT - 5 + 1 FSI_SLAVE_CASCADE @@ -12576,7 +12581,7 @@ affinity:sys-0/node-0/proc-7/mcs-6/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-7 @@ -12587,7 +12592,7 @@ FSI_MASTER_PORT - 6 + 2 FSI_SLAVE_CASCADE @@ -12665,7 +12670,7 @@ affinity:sys-0/node-0/proc-7/mcs-7/membuf-0 - + FSI_MASTER_CHIP physical:sys-0/node-0/proc-7 @@ -12676,7 +12681,7 @@ FSI_MASTER_PORT - 7 + 3 FSI_SLAVE_CASCADE @@ -12736,14 +12741,11 @@ - sys0node0proc0wrap chip-processor-venice - HUID0x00070000 + HUID0x00070099 SCOM_SWITCHES useFsiScom1 @@ -12761,7 +12763,7 @@ Target used for FSI wrap-back testing affinity:sys-0/node-0/proc-9 - FSI is connected via wrapback to itself over MFSI-0 + FSI_MASTER_CHIP physical:sys-0/node-0/proc-0 @@ -12785,7 +12787,6 @@ Target used for FSI wrap-back testing VPD_REC_NUM0 --->