From f7cb4b2a4cf432f56d91c12e39e4dae41e8facdf Mon Sep 17 00:00:00 2001 From: Li Meng Date: Tue, 6 Nov 2018 14:37:28 -0600 Subject: Adds LRDIMM MWD coarse training step Change-Id: Ie8317b5a4542cf9a71f85d357cc2071b687d3cda Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68466 Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Tested-by: HWSV CI Reviewed-by: STEPHEN GLANCY Tested-by: Hostboot CI Reviewed-by: Louis Stermole Reviewed-by: Jennifer A. Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68720 Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Christian R. Geddes --- .../chips/p9/procedures/hwp/memory/lib/ccs/ccs.H | 37 ++++++++++++++++++ .../hwp/memory/lib/phy/mss_lrdimm_training.C | 41 +------------------- .../hwp/memory/lib/phy/mss_lrdimm_training.H | 45 ---------------------- .../procedures/hwp/memory/lib/phy/mss_training.C | 12 ++++++ 4 files changed, 50 insertions(+), 85 deletions(-) (limited to 'src') diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H b/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H index 761c31a78..ab7ad1db5 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H @@ -398,6 +398,43 @@ static void mrs_rcd_helper( fapi2::buffer& i_arr0 ) .template clearBit(); } +/// +/// @brief Setup activate command instruction +/// @tparam T the target type of the chiplet which executes the CCS instruction +/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction +/// @param[in] i_target the DIMM this instruction is headed for +/// @param[in] i_rank the rank on this dimm +/// +template< fapi2::TargetType T, typename TT = ccsTraits > +inline instruction_t act_command( const fapi2::Target& i_target, + const uint64_t i_rank) +{ + fapi2::buffer l_boilerplate_arr0; + fapi2::buffer l_boilerplate_arr1; + + // Set all CKE to high + l_boilerplate_arr0.insertFromRight(CKE_HIGH); + + // ACT is high + l_boilerplate_arr0.clearBit(); + + // RAS low, CAS low, WE low + l_boilerplate_arr0.clearBit() + .template clearBit() + .template clearBit(); + + // Just leaving the row addresses to all 0 for now + // row, bg, ba set to 0 + l_boilerplate_arr0.clearBit(); + l_boilerplate_arr0.insertFromRight(0); + l_boilerplate_arr0.clearBit(); + l_boilerplate_arr0.clearBit(); + l_boilerplate_arr0.insertFromRight(0); + l_boilerplate_arr0.clearBit(); + + return instruction_t(i_target, i_rank, l_boilerplate_arr0, l_boilerplate_arr1); +} + /// /// @brief Create, initialize an RCD (RCW - JEDEC) CCS command /// @tparam T the target type of the chiplet which executes the CCS instruction diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.C index bb403190b..5643e96db 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.C @@ -37,7 +37,6 @@ #include #include - #include #include #include @@ -48,8 +47,8 @@ #include #include #include -#include #include +#include #ifdef LRDIMM_CAPABLE #include @@ -692,44 +691,6 @@ uint64_t mrep::calculate_cycles( const fapi2::Target& i_ return 0; } -/// -/// @brief Sets up and runs the calibration step -/// @param[in] i_target - the MCA target on which to operate -/// @param[in] i_rp - the rank pair -/// @param[in] i_abort_on_error - whether or not we are aborting on cal error -/// @return fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS iff ok -/// -fapi2::ReturnCode mwd::run( const fapi2::Target& i_target, - const uint64_t i_rp, - const uint8_t i_abort_on_error ) const -{ - return fapi2::FAPI2_RC_SUCCESS; -} - -/// -/// @brief Executes a cal step with workarounds -/// @param[in] i_target - the MCA target on which to operate -/// @param[in] i_rp - the rank pair -/// @param[in] i_abort_on_error - whether or not we are aborting on cal error -/// @return fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS iff ok -/// -fapi2::ReturnCode mwd::execute( const fapi2::Target& i_target, - const uint64_t i_rp, - const uint8_t i_abort_on_error ) const -{ - return fapi2::FAPI2_RC_SUCCESS; -} - -/// -/// @brief Calculates the number of cycles a given calibration step will take -/// @param[in] i_target - the MCA target on which to operate -/// @return l_cycles - the number of cycles a given calibration step wil take -/// -uint64_t mwd::calculate_cycles( const fapi2::Target& i_target ) const -{ - return 0; -} - /// /// @brief Deconfigures calibration steps depending upon LRDIMM type /// @param[in] i_dimm_type - DIMM type diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.H index 16d258390..229f9efe7 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.H @@ -608,51 +608,6 @@ class mrep : public step }; -/// -/// @brief MPR training step -/// -class mwd : public step -{ - public: - mwd() : - step("MWD") - {} - - /// - /// @brief Default virtual destructor - /// - ~mwd() = default; - - /// - /// @brief Sets up and runs the calibration step - /// @param[in] i_target - the MCA target on which to operate - /// @param[in] i_rp - the rank pair - /// @param[in] i_abort_on_error - whether or not we are aborting on cal error - /// @return fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS iff ok - /// - fapi2::ReturnCode run( const fapi2::Target& i_target, - const uint64_t i_rp, - const uint8_t i_abort_on_error ) const; - - /// - /// @brief Executes a cal step with workarounds - /// @param[in] i_target - the MCA target on which to operate - /// @param[in] i_rp - the rank pair - /// @param[in] i_abort_on_error - whether or not we are aborting on cal error - /// @return fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS iff ok - /// - fapi2::ReturnCode execute( const fapi2::Target& i_target, - const uint64_t i_rp, - const uint8_t i_abort_on_error ) const; - - /// - /// @brief Calculates the number of cycles a given calibration step will take - /// @param[in] i_target - the MCA target on which to operate - /// @return l_cycles - the number of cycles a given calibration step wil take - /// - uint64_t calculate_cycles( const fapi2::Target& i_target ) const; -}; - // TK:LRDIMM Identify if Host Interface Write Leveling (HWL) Mode needs to be updated or if the PHY can handle it // TK:LRDIMM Identify if Host Interface Read Training is any different // TK:LRDIMM Identify if Host Interface Write training Training is any different diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C index 6d854ba63..5c1df9aaf 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C @@ -59,6 +59,7 @@ #ifdef LRDIMM_CAPABLE #include #include + #include #endif namespace mss @@ -1248,6 +1249,17 @@ std::vector> steps_factory(const fapi2::buffer& l_steps.push_back(std::make_shared(i_sim)); } +#ifdef LRDIMM_CAPABLE + + //MWD COARSE + if(i_cal_steps.getBit()) + { + FAPI_INF("LRDIMM: MWD COARSE is enabled"); + l_steps.push_back(std::make_shared()); + } + +#endif + // INITIAL_PAT_WR if(i_cal_steps.getBit()) { -- cgit v1.2.3