From 9ae8a93abe9554bb58660d34cf4c6d7de1de3f86 Mon Sep 17 00:00:00 2001 From: "Richard J. Knight" Date: Fri, 3 Oct 2014 15:21:14 -0500 Subject: SW280992: Add set rx_wt_lane_disabled to io_power_down_lanes to remove dmi_io_dc Change-Id: Id5a854b1cdae67bd146a2afaa887031926b2fae8 CQ:SW280992 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/13758 Reviewed-by: Brian H. Horton Reviewed-by: Richard J. Knight Tested-by: Richard J. Knight Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/13770 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III --- .../hwpf/hwp/bus_training/io_power_down_lanes.C | 317 ++++++++++----------- 1 file changed, 153 insertions(+), 164 deletions(-) (limited to 'src') diff --git a/src/usr/hwpf/hwp/bus_training/io_power_down_lanes.C b/src/usr/hwpf/hwp/bus_training/io_power_down_lanes.C index e03bedd5e..1650e326c 100644 --- a/src/usr/hwpf/hwp/bus_training/io_power_down_lanes.C +++ b/src/usr/hwpf/hwp/bus_training/io_power_down_lanes.C @@ -22,7 +22,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: io_power_down_lanes.C,v 1.13 2014/03/06 11:12:24 varkeykv Exp $ +// $Id: io_power_down_lanes.C,v 1.14 2014/09/29 23:22:56 garyp Exp $ // *!*************************************************************************** // *! (C) Copyright International Business Machines Corp. 1997, 1998 // *! All Rights Reserved -- Property of IBM @@ -33,8 +33,8 @@ // *! DESCRIPTION : Power down bad lanes // *! CONTEXT : // *! -// *! OWNER NAME : Varghese, Varkey Email: varkey.kv@in.ibm.com -// *! BACKUP NAME : Swaminathan, Janani Email: jaswamin@in.ibm.com +// *! OWNER NAME : Steffen, Chris Email: cwsteffen@us.ibm.com +// *! BACKUP NAME : Peterson, Gary Email: garyp@us.ibm.com // *! // *!*************************************************************************** // CHANGE HISTORY: @@ -50,184 +50,173 @@ extern "C" { + using namespace fapi; -using namespace fapi; + /* + This function will perform power down of lanes on any IO target: MEMBUF, MCS ,XBUS, or ABUS + For rx_lanes, it will also set rx_wt_lane_disabled + For a bad lane, it will be called twice: + once with target set to the rx target, rx_lanes populated, and tx_lanes empty + once with target set to the tx target, tx_lanes populated, and rx_lanes empty + */ + ReturnCode io_power_down_lanes(const Target& target, const std::vector &tx_lanes, const std::vector &rx_lanes) { + ReturnCode rc; + ecmdDataBufferBase data(16); + ecmdDataBufferBase mask(16); + ecmdDataBufferBase mode_reg(16); + uint8_t lane=0; + bool msbswap=false; + const uint8_t xbus_lanes_per_group=20; + uint8_t end_lane=0; -/* - This function will perform power down of lanes on any IO target MEMBUF,MCS , XBUS or ABUS - * Bad lanes are powered down , but caller is expected to logically disable lanes by calling restore_repair prior - * to calling this HWP -*/ - -ReturnCode io_power_down_lanes(const Target& target,const std::vector &tx_lanes,const std::vector &rx_lanes) -{ - ReturnCode rc; - ecmdDataBufferBase data(16); - ecmdDataBufferBase mask(16); - ecmdDataBufferBase mode_reg(16); - uint8_t lane=0; - bool msbswap=false; - const uint8_t xbus_lanes_per_group=20; - uint8_t end_lane=0; - io_interface_t interface=CP_IOMC0_P0; // Since G uint32_t rc_ecmd=0; uint8_t clock_group=0; uint8_t start_group=0; - do - { - // Both TX and RX power down bits are on bit 0 - rc_ecmd=mask.flushTo1(); - rc_ecmd=mask.clearBit(0); - if(rc_ecmd) - { - FAPI_ERR("io_power_down_lanes error occured while" - " flushing and clearing bits for mask"); - rc.setEcmdError(rc_ecmd); - break; + do { + // rx_lane_pdwn, tx_lane_pdwn, and rx_wt_lane_disabled are all bit 0; and this routine is setting all 3, so we set up data and mask once + rc_ecmd=mask.flushTo1(); + if(rc_ecmd) { + FAPI_ERR("io_power_down_lanes error occured while flushing bits for mask"); + rc.setEcmdError(rc_ecmd); + break; + } + + rc_ecmd=data.flushTo0(); + if(rc_ecmd) { + FAPI_ERR("io_power_down_lanes error occured while flushing bits for data"); + rc.setEcmdError(rc_ecmd); + break; + } + + rc_ecmd=data.setBit(0); + if(rc_ecmd) { + FAPI_ERR("io_power_down_lanes error occured while clearing bits for data"); + rc.setEcmdError(rc_ecmd); + break; + } + + // Check which type of bus this is and do setup needed + fapi::TargetType l_type= target.getType(); + switch (l_type) { + case fapi::TARGET_TYPE_ABUS_ENDPOINT: + start_group=0; + interface=CP_FABRIC_A0; // base scom for A bus , assume translation to A1 by PLAT + break; + case fapi::TARGET_TYPE_XBUS_ENDPOINT: + start_group=0; + interface=CP_FABRIC_X0; // base scom for X bus + break; + case fapi::TARGET_TYPE_MCS_CHIPLET: + start_group=3; + interface=CP_IOMC0_P0; // base scom for MC bus + break; + case fapi::TARGET_TYPE_MEMBUF_CHIP: + start_group=0; + interface=CEN_DMI; // base scom Centaur chip + break; + default: + FAPI_ERR("Invalid io_power_down_lanes HWP invocation"); + const fapi::Target& TARGET = target; + FAPI_SET_HWP_ERROR(rc, IO_POWER_DOWN_LANES_INVALID_INVOCATION_RC); + break; + } + if (rc) { + break; + } + + FAPI_INF("Power down IO lanes\n"); + + rc = GCR_read( target, interface, tx_mode_pg, start_group, 0, mode_reg); + if(rc) { + FAPI_ERR("GCR_read returned an error while reading tx_mode_pg"); + break; + } + + if(mode_reg.isBitSet(5)) { + FAPI_DBG("TX MSB-LSB SWAP MODE ON on this target %d \n",tx_end_lane_id); + msbswap=true; + } + + //TX Lanes power down; target must be the tx + for(uint8_t i=0;i(xbus_lanes_per_group-1)) { + lane=lane-xbus_lanes_per_group; + clock_group++; + } } - - // Check which type of bus this is and do setup needed - fapi::TargetType l_type= target.getType(); - switch (l_type) - { - case fapi::TARGET_TYPE_ABUS_ENDPOINT: - start_group=0; - interface=CP_FABRIC_A0; // base scom for A bus , assume translation to A1 by PLAT - break; - case fapi::TARGET_TYPE_XBUS_ENDPOINT: - start_group=0; - interface=CP_FABRIC_X0; // base scom for X bus - break; - case fapi::TARGET_TYPE_MCS_CHIPLET: - start_group=3; - interface=CP_IOMC0_P0; // base scom for MC bus - break; - case fapi::TARGET_TYPE_MEMBUF_CHIP: - start_group=0; - interface=CEN_DMI; // base scom Centaur chip - break; - default: - FAPI_ERR("Invalid io_power_down_lanes HWP invocation"); - const fapi::Target &TARGET=target; - FAPI_SET_HWP_ERROR(rc, IO_POWER_DOWN_LANES_INVALID_INVOCATION_RC); - break; + else { + clock_group=start_group; + // MSBLSB SWAP condition can be there in MC or A + if(msbswap) { + // We can read out tx_end_lane_id now for swap correction + rc = GCR_read( target, interface, tx_id3_pg, clock_group, 0, mode_reg); + if(rc) { + FAPI_ERR("GCR_read returned an error during call to read tx_id3_pg"); + break; + } + + rc_ecmd=mode_reg.extract(&end_lane,9,7); + if(rc_ecmd) { + rc.setEcmdError(rc_ecmd); + break; + } + end_lane=end_lane>>1;// move left aligned extract by 1 + FAPI_DBG("END lane id is %d\n",end_lane); + lane=end_lane-tx_lanes[i]; // GFW VPD does not know about MSBSWAP , this adjusts for swapping + } } - if (rc) - { - break; + + //Power down this lane + rc = GCR_write( target, interface, tx_mode_pl, clock_group, lane, data, mask ); + if(rc) { + FAPI_ERR("GCR_write returned an error while writing tx_mode_pl"); + break; } - - FAPI_INF("Power down IO lanes\n"); - - rc_ecmd|=data.flushTo0(); - rc_ecmd|=data.setBit(0); // Power down is on bit 0 always - if(rc_ecmd) - { - FAPI_ERR("io_power_down_lanes error occured while" - " flushing and clearing bits for data"); - rc.setEcmdError(rc_ecmd); - break; + } + + if (rc) { //break out of larger while loop + break; + } + + // Process RX lane powerdown; target must be the rx + for(uint8_t i=0;i(xbus_lanes_per_group-1)) { + lane=lane-xbus_lanes_per_group; + clock_group++; + } } - - rc = GCR_read( target, interface,tx_mode_pg, start_group, 0, mode_reg); - if(rc) - { - FAPI_ERR("GCR_read returned an error while reading tx_mode_pg"); - break; - } - - if(mode_reg.isBitSet(5)) - { - FAPI_DBG("TX MSB-LSB SWAP MODE ON on this target %d \n",tx_end_lane_id); - msbswap=true; + else { + clock_group=start_group; } - - //TX Lanes power down - for(uint8_t i=0;i(xbus_lanes_per_group-1)) - { - lane=lane-xbus_lanes_per_group; - clock_group++; - } - } - else - { - clock_group=start_group; - // MSBLSB SWAP condition can be there in MC or A - if(msbswap) - { - // We can read out tx_end_lane_id now for swap correction - rc = GCR_read( target, interface,tx_id3_pg, clock_group, 0, mode_reg); - if(rc) - { - FAPI_ERR("GCR_read returned an error during call to read tx_id3_pg"); - break; - } - - rc_ecmd=mode_reg.extract(&end_lane,9,7); - if(rc_ecmd) - { - rc.setEcmdError(rc_ecmd); - break; - } - end_lane=end_lane>>1;// move left aligned extract by 1 - FAPI_DBG("END lane id is %d\n",end_lane); - lane=end_lane-tx_lanes[i]; // GFW VPD does not know about MSBSWAP , this adjusts for swapping - } - } - //Power down this lane - rc = GCR_write( target, interface, tx_mode_pl, clock_group, lane, data,mask ); - if(rc) - { - FAPI_ERR("GCR_write returned an error while writing tx_mode_pl"); - break; - } + //Power down this lane + rc = GCR_write( target, interface, rx_mode_pl, clock_group, lane, data, mask ); + if(rc) { + FAPI_ERR("GCR_write returned an error while writing rx_mode_pl"); + break; } - //break out of larger while loop - if (rc) - { - break; + // Set rx_wt_lane_disabled for this lane; see SW244284, SW280992 + rc = GCR_write( target, interface, rx_wt_status_pl, clock_group, lane, data, mask ); + if(rc) { + FAPI_ERR("GCR_write returned an error while writing rx_wt_status_pl"); + break; } - // Process RX lane powerdown - for(uint8_t i=0;i(xbus_lanes_per_group-1)) - { - lane=lane-xbus_lanes_per_group; - clock_group++; - } - } - else - { - clock_group=start_group; - } - //Power down this lane - rc = GCR_write( target, interface, rx_mode_pl, clock_group, lane, data,mask ); - if(rc) - { - FAPI_ERR("GCR_write returned an error while writing rx_mode_pl"); - break; - } - } - }while(0); + } + } while(0); // run loop only once return rc; -} - + } //end io_power_down_lanes } //end extern C -- cgit v1.2.1