From 8f2fbd8180414a5dab93159b6c55974f569f358b Mon Sep 17 00:00:00 2001 From: Alvin Wang Date: Tue, 29 Jan 2019 02:13:09 -0600 Subject: Reinstates exp_draminit_mc with change_addr_mux_sel fix Change-Id: Ief62fadce588bf65e249ae771bd03ab31ed4bddf Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71201 Tested-by: FSP CI Jenkins Dev-Ready: Louis Stermole Tested-by: Jenkins Server Tested-by: HWSV CI Tested-by: Hostboot CI Reviewed-by: Louis Stermole Reviewed-by: STEPHEN GLANCY Reviewed-by: Jennifer A. Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71218 Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Daniel M. Crowell --- .../procedures/hwp/memory/exp_draminit_mc.C | 76 ++++ .../procedures/hwp/memory/exp_draminit_mc.H | 30 ++ .../procedures/hwp/memory/exp_draminit_mc.mk | 8 + .../procedures/hwp/memory/lib/mc/exp_port.H | 111 ++++++ .../procedures/hwp/memory/lib/shared/exp_consts.H | 5 + .../chips/p9/procedures/hwp/memory/lib/mc/port.C | 2 +- .../chips/p9/procedures/hwp/memory/lib/mc/port.H | 305 ++++------------ .../hwp/memory/lib/mss_attribute_accessors.H | 67 ++-- .../procedures/hwp/memory/lib/shared/mss_const.H | 26 +- .../p9/procedures/hwp/memory/p9_mss_draminit.C | 1 + .../xml/attribute_info/memory_mrw_attributes.xml | 15 - .../memory/lib/mss_generic_attribute_getters.H | 22 ++ src/import/generic/memory/lib/utils/index.H | 13 + .../generic/memory/lib/utils/mc/gen_mss_port.H | 393 +++++++++++++++++++++ .../memory/lib/utils/mc/gen_mss_port_traits.H | 29 ++ .../memory/lib/utils/shared/mss_generic_consts.H | 39 ++ .../generic_memory_mrw_attributes.xml | 16 +- 17 files changed, 850 insertions(+), 308 deletions(-) (limited to 'src') diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit_mc.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit_mc.C index 54e135000..9719e612c 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit_mc.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit_mc.C @@ -22,3 +22,79 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ +/// +/// @file exp_mss_draminit_mc.C +/// @brief Initialize the memory controller to take over the DRAM +/// +// *HWP HWP Owner: Louis Stermole +// *HWP HWP Backup: Andre Marin +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: FSP:HB + +#include + +#include +#include +#include + +#include + +extern "C" +{ +/// +/// @brief Initialize the MC now that DRAM is up +/// @param[in] i_target, the MC of the ports +/// @return FAPI2_RC_SUCCESS iff ok +/// + fapi2::ReturnCode exp_draminit_mc( const fapi2::Target& i_target ) + { + + FAPI_INF("%s Start exp_draminit MC", mss::c_str(i_target)); + + //skip this ocmb_chip if we have no DIMM's configured + if(mss::count_dimm(i_target) == 0) + { + FAPI_INF("No DIMM's configured on %s. Skipping this OCMB_CHIP.", mss::c_str(i_target)); + return fapi2::FAPI2_RC_SUCCESS; + } + + // Enable Power management based off of mrw_power_control_requested + FAPI_TRY( mss::enable_power_management(i_target), "%s Failed to enable power management", + mss::c_str(i_target) ); + + // Set the IML Complete bit. Steve Powell to find a bit in the SRQ to use for this purpose + FAPI_TRY( mss::change_iml_complete(i_target, mss::HIGH), "%s Failed to set_ipm_complete", + mss::c_str(i_target)); + + // Set DFI init start requested from Stephen Powell + FAPI_TRY( mss::change_dfi_init_start(i_target, mss::ON ), "%s Failed to change_dfi_init_start", + mss::c_str(i_target)); + + // Re-enable port fails. + FAPI_TRY( mss::change_port_fail_disable(i_target, mss::OFF ), + "%s Failed to change_port_fail_disable", mss::c_str(i_target) ); + + // Start the refresh engines by setting MBAREF0Q(0) = “1”. Note that the remaining bits in + // MBAREF0Q should retain their initialization values. + FAPI_TRY( mss::change_refresh_enable(i_target, mss::HIGH), "%s Failed change_refresh_enable", + mss::c_str(i_target) ); + + // Enable periodic short zq cal + FAPI_TRY( mss::enable_zq_cal(i_target), "%s Failed enable_zq_cal", mss::c_str(i_target) ); + + // Enable ecc checking + FAPI_TRY( mss::enable_read_ecc(i_target), "%s Failed enable_read_ecc", mss::c_str(i_target) ); + + // Apply marks from OCMB VPD + FAPI_TRY( mss::apply_mark_store(i_target), "%s Failed enable_read_ecc", mss::c_str(i_target) ); + + // TODO: Move mss::unmask::after_draminit_mc to generic and call it + // At this point the DDR interface must be monitored for memory errors. Memory related FIRs should be unmasked. + //FAPI_TRY( mss::unmask::after_draminit_mc(i_target), "%s Failed after_draminit_mc", mss::c_str(i_target) ); + + fapi_try_exit: + FAPI_INF("%s End exp_draminit MC", mss::c_str(i_target)); + return fapi2::current_err; + } +} diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit_mc.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit_mc.H index 95f15ff9e..6e049346e 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit_mc.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit_mc.H @@ -22,3 +22,33 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file exp_draminit_mc.H +/// @brief Initialize the memory controller to take over the DRAM +/// +// *HWP HWP Owner: Louis Stermole +// *HWP HWP Backup: Andre Marin +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: FSP:HB + +#ifndef EXP_DRAMINIT_MC_H_ +#define EXP_DRAMINIT_MC_H_ + +#include + +typedef fapi2::ReturnCode (*exp_draminit_mc_FP_t) (const fapi2::Target&); + +extern "C" +{ + + /// + /// @brief Trains the OCMB link + /// @param[in] i_target the OCMB target to operate on + /// @return FAPI2_RC_SUCCESS iff ok + /// + fapi2::ReturnCode exp_draminit_mc(const fapi2::Target& i_target); +} + +#endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit_mc.mk b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit_mc.mk index fde45e8f9..37eb61e73 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit_mc.mk +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit_mc.mk @@ -22,3 +22,11 @@ # permissions and limitations under the License. # # IBM_PROLOG_END_TAG + + + +-include 00exp_common.mk + +PROCEDURE=exp_draminit_mc +$(eval $(call ADD_EXP_MEMORY_INCDIRS,$(PROCEDURE))) +$(call BUILD_PROCEDURE) diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port.H index e144b9c6f..a65375672 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port.H @@ -22,3 +22,114 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file exp_port.H +/// @brief Code to support ports +/// +// *HWP HWP Owner: Stephen Glancy +// *HWP HWP Backup: Andre Marin +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: HB:FSP + +#ifndef __MSS_EXP_PORT_H_ +#define __MSS_EXP_PORT_H_ + +#include +#include +#include +#include +#include +#include +#include +#include + +namespace mss +{ + +/// +/// @brief ATTR_MSS_MEM_MVPD_FWMS getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] uint32_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (G) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Mark store records from MPVD Lx +/// keyword +/// +template<> +inline fapi2::ReturnCode mvpd_fwms(const fapi2::Target& i_target, + uint32_t (&o_array)[mss::MARK_STORE_COUNT]) +{ + return mss::attr::get_mvpd_fwms(i_target, o_array); +} + +/// +/// @class Traits and policy class for port code - specialization for Explorer. The target of registers is TARGET_TYPE_OCMB_CHIP +/// +template<> +class portTraits< mss::mc_type::EXPLORER > +{ + public: + // scom register definition + static constexpr uint64_t MBARPC0Q_REG = EXPLR_SRQ_MBARPC0Q; + + static constexpr uint64_t FARB0Q_REG = EXPLR_SRQ_MBA_FARB0Q; + static constexpr uint64_t FARB5Q_REG = EXPLR_SRQ_MBA_FARB5Q; + static constexpr uint64_t FARB6Q_REG = EXPLR_SRQ_MBA_FARB6Q; + static constexpr uint64_t FARB9Q_REG = EXPLR_SRQ_MBA_FARB9Q; + static constexpr uint64_t REFRESH_REG = EXPLR_SRQ_MBAREF0Q; + static constexpr uint64_t ECC_REG = EXPLR_RDF_RECR; + static constexpr uint64_t DSM0Q_REG = EXPLR_SRQ_MBA_DSM0Q; + static constexpr uint64_t FWMS_REG = EXPLR_RDF_FWMS0; + + static constexpr uint64_t RRQ_REG = EXPLR_SRQ_MBA_RRQ0Q; + static constexpr uint64_t WRQ_REG = EXPLR_SRQ_MBA_WRQ0Q; + + static constexpr uint64_t MAGIC_NUMBER_SIM = 765; + static constexpr uint64_t MAGIC_NUMBER_NOT_SIM = 196605; + + // scom register field definition + enum + { + CFG_MIN_MAX_DOMAINS_ENABLE = EXPLR_SRQ_MBARPC0Q_CFG_MIN_MAX_DOMAINS_ENABLE, + CFG_CCS_INST_RESET_ENABLE = EXPLR_SRQ_MBA_FARB5Q_CFG_CCS_INST_RESET_ENABLE, + CFG_DDR_RESETN = EXPLR_SRQ_MBA_FARB5Q_CFG_DDR_RESETN, + CFG_CCS_ADDR_MUX_SEL = EXPLR_SRQ_MBA_FARB5Q_CFG_CCS_ADDR_MUX_SEL, + //TODO: It's not defined in scom register header file. Change this once it's available in scom address header file + CFG_INIT_COMPLETE = 32, //EXPLR_SRQ_MBA_FARB6Q_CFG_INIT_COMPLETE, + CFG_ZQ_PER_CAL_ENABLE = EXPLR_SRQ_MBA_FARB9Q_CFG_ZQ_PER_CAL_ENABLE, + + REFRESH_ENABLE = EXPLR_SRQ_MBAREF0Q_CFG_REFRESH_ENABLE, + + ECC_CHECK_DISABLE = EXPLR_RDF_RECR_MBSECCQ_DISABLE_MEMORY_ECC_CHECK_CORRECT, + ECC_CORRECT_DISABLE = EXPLR_RDF_RECR_MBSECCQ_DISABLE_MEMORY_ECC_CORRECT, + ECC_USE_ADDR_HASH = EXPLR_RDF_RECR_MBSECCQ_USE_ADDRESS_HASH, + + PORT_FAIL_DISABLE = EXPLR_SRQ_MBA_FARB0Q_CFG_PORT_FAIL_DISABLE, + DFI_INIT_START = EXPLR_SRQ_MBA_FARB0Q_CFG_MISR_FEEDBACK_ENABLE, + RCD_RECOVERY_DISABLE = EXPLR_SRQ_MBA_FARB0Q_CFG_DISABLE_RCD_RECOVERY, + + RECR_TCE_CORRECTION = EXPLR_RDF_RECR_MBSECCQ_ENABLE_TCE_CORRECTION, + RECR_MBSECCQ_DATA_INVERSION = EXPLR_RDF_RECR_MBSECCQ_DATA_INVERSION, + RECR_MBSECCQ_DATA_INVERSION_LEN = EXPLR_RDF_RECR_MBSECCQ_DATA_INVERSION_LEN, + DSM0Q_RDTAG_DLY = EXPLR_SRQ_MBA_DSM0Q_CFG_RDTAG_DLY, + DSM0Q_RDTAG_DLY_LEN = EXPLR_SRQ_MBA_DSM0Q_CFG_RDTAG_DLY_LEN, + DSM0Q_WRDONE_DLY = EXPLR_SRQ_MBA_DSM0Q_CFG_WRDONE_DLY, + DSM0Q_WRDONE_DLY_LEN = EXPLR_SRQ_MBA_DSM0Q_CFG_WRDONE_DLY_LEN, + FARB0Q_RCD_PROTECTION_TIME = EXPLR_SRQ_MBA_FARB0Q_CFG_RCD_PROTECTION_TIME, + FARB0Q_RCD_PROTECTION_TIME_LEN = EXPLR_SRQ_MBA_FARB0Q_CFG_RCD_PROTECTION_TIME_LEN, + + FWMS0_MARK = EXPLR_RDF_FWMS0_MARK, + FWMS0_MARK_LEN = EXPLR_RDF_FWMS0_MARK_LEN, + FWMS0_EXIT_1 = EXPLR_RDF_FWMS0_EXIT_1, + + RRQ_FIFO_MODE = EXPLR_SRQ_MBA_RRQ0Q_CFG_RRQ_FIFO_MODE, + WRQ_FIFO_MODE = EXPLR_SRQ_MBA_WRQ0Q_CFG_WRQ_FIFO_MODE, + }; +}; + + +}// mss + +#endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H index c967d05d5..ab6d347d7 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H @@ -36,8 +36,13 @@ #ifndef EXP_CONSTS_H #define EXP_CONSTS_H +#include + namespace mss { + +constexpr mss::mc_type DEFAULT_MC_TYPE = mss::mc_type::EXPLORER; + namespace exp { diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C index 97e7fa229..75d15c1d1 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C @@ -72,7 +72,7 @@ constexpr uint64_t BIT_SPARE_7 = 15; // 7: SPARE template<> fapi2::ReturnCode enable_periodic_cal( const fapi2::Target& i_target ) { - typedef portTraits TT; + typedef portTraits TT; uint32_t l_memcal_interval = 0; uint32_t l_zqcal_interval = 0; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H index c2023ae27..1f5f06f43 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H @@ -25,7 +25,7 @@ /// /// @file port.H -/// @brief Code to support ports (phy _ mc for certain operations) +/// @brief Code to support ports /// // *HWP HWP Owner: Stephen Glancy // *HWP HWP Backup: Andre Marin @@ -38,35 +38,41 @@ #include -#include -#include #include -#include #include #include -#include #include +#include +#include +#include +#include +#include #include namespace mss { -// I have a dream that port code can be shared among controllers. So, I drive the -// engine from a set of traits. This might be folly. Allow me to dream. BRS - -template< fapi2::TargetType T > -class portTraits; - -// Centaur port traits +/// +/// @brief ATTR_MSS_MVPD_FWMS getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] uint32_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (G) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Mark store records from MPVD Lx +/// keyword +/// template<> -class portTraits +inline fapi2::ReturnCode mvpd_fwms(const fapi2::Target& i_target, + uint32_t (&o_array)[mss::MARK_STORE_COUNT]) { - public: -}; + return mvpd_fwms(i_target, &o_array[0]); +} -// Nimbus port traits +/// +/// @class Traits and policy class for port code - specialization for Nimbus. The target of registers is TARGET_TYPE_MCA. +/// template<> -class portTraits +class portTraits { public: static constexpr uint64_t FARB5Q_REG = MCA_MBA_FARB5Q; @@ -78,6 +84,7 @@ class portTraits static constexpr uint64_t CAL2Q_REG = MCA_MBA_CAL2Q; static constexpr uint64_t CAL3Q_REG = MCA_MBA_CAL3Q; static constexpr uint64_t DSM0Q_REG = MCA_MBA_DSM0Q; + static constexpr uint64_t FWMS_REG = MCA_FWMS0; // Danger Will Robinson MCA_DDRPHY_PC_PER_ZCAL_CONFIG_P0 uses PHY rank ordinal numbers // which are different between PHYs. So if you're playing with this register, be sure to map rank numbers. @@ -112,6 +119,9 @@ class portTraits CFG_DDR_RESETN = MCA_MBA_FARB5Q_CFG_DDR_RESETN, CFG_CCS_ADDR_MUX_SEL = MCA_MBA_FARB5Q_CFG_CCS_ADDR_MUX_SEL, + FWMS0_MARK = MCA_FWMS0_MARK, + FWMS0_EXIT_1 = MCA_FWMS0_EXIT_1, + REFRESH_ENABLE = MCA_MBAREF0Q_CFG_REFRESH_ENABLE, ECC_CHECK_DISABLE = MCA_RECR_MBSECCQ_DISABLE_MEMORY_ECC_CHECK_CORRECT, @@ -231,6 +241,8 @@ class portTraits RECR_ENABLE_UE_NOISE_WINDOW = MCA_RECR_MBSECCQ_ENABLE_UE_NOISE_WINDOW, RECR_TCE_CORRECTION = MCA_RECR_MBSECCQ_ENABLE_TCE_CORRECTION, RECR_READ_POINTER_DLY = MCA_RECR_MBSECCQ_READ_POINTER_DELAY, + RECR_MBSECCQ_DATA_INVERSION = MCA_RECR_MBSECCQ_DATA_INVERSION, + RECR_MBSECCQ_DATA_INVERSION_LEN = MCA_RECR_MBSECCQ_DATA_INVERSION_LEN, RECR_READ_POINTER_DLY_LEN = MCA_RECR_MBSECCQ_READ_POINTER_DELAY_LEN, DSM0Q_RDTAG_DLY = MCA_MBA_DSM0Q_CFG_RDTAG_DLY, DSM0Q_RDTAG_DLY_LEN = MCA_MBA_DSM0Q_CFG_RDTAG_DLY_LEN, @@ -271,43 +283,8 @@ class portTraits }; }; -/// -/// @brief Read the read ECC Control register -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in] i_target the target -/// @param[out] o_buffer the buffer to write the register data into -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template< fapi2::TargetType T, typename TT = portTraits > -fapi2::ReturnCode read_recr_register( const fapi2::Target& i_target, fapi2::buffer& o_buffer ) -{ - FAPI_TRY( mss::getScom(i_target, TT::ECC_REG, o_buffer) ); - - FAPI_INF( "Read ECC Control register is 0x%016lx for %s", uint64_t(o_buffer), mss::c_str(i_target) ); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Write to RECR register -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in] i_target the target -/// @param[in] i_buffer the buffer that holds the register data to write -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template< fapi2::TargetType T, typename TT = portTraits > -fapi2::ReturnCode write_recr_register( const fapi2::Target& i_target, const fapi2::buffer& i_buffer ) -{ - FAPI_INF( "Change Read ECC Control register to 0x%016lx for %s", i_buffer, mss::c_str(i_target) ); - FAPI_TRY( mss::putScom(i_target, TT::ECC_REG, i_buffer) ); -fapi_try_exit: - return fapi2::current_err; -} /// /// @brief Get the read pointer delay value from RECR @@ -316,7 +293,7 @@ fapi_try_exit: /// @param[in] i_data the data buffer containing the RECR register /// @param[out] o_delay READ_POINTER_DLY value (in cycles) /// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > void get_read_pointer_delay( const fapi2::buffer& i_data, uint64_t& o_delay ) { i_data.template extractToRight(o_delay); @@ -331,7 +308,7 @@ void get_read_pointer_delay( const fapi2::buffer& i_data, uint64_t& o_ /// @param[in,out] io_data the target data buffer /// @param[in] i_delay READ_POINTER_DLY value (in cycles) to set /// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > void set_read_pointer_delay( fapi2::buffer& io_data, const uint64_t i_delay ) { FAPI_INF( "Set READ_POINTER_DLY to %d", i_delay); @@ -339,35 +316,6 @@ void set_read_pointer_delay( fapi2::buffer& io_data, const uint64_t i_ io_data.template insertFromRight(i_delay); } -/// -/// @brief Get the tce correction enable value from RECR -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in] i_data the data buffer containing the RECR register -/// @param[out] o_value TCE_CORRECTION_ENABLE value (on or off) -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > -void get_tce_correction( const fapi2::buffer& i_data, mss::states& o_value ) -{ - o_value = i_data.template getBit() ? mss::states::ON : mss::states::OFF; - - FAPI_INF( "TCE_CORRECTION_ENABLE: %lu", o_value ); -} - -/// -/// @brief Sets tce correction enable in buffer -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in,out] io_data the target data buffer -/// @param[in] i_value TCE_CORRECTION_ENABLE value (on or off) to set -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > -void set_tce_correction( fapi2::buffer& io_data, const mss::states i_value ) -{ - FAPI_INF( "Set TCE_CORRECTION_ENABLE to %lu", i_value); - - io_data.template writeBit(i_value); -} /// /// @brief Get the enable_ue_noise_window value from buffer @@ -376,7 +324,7 @@ void set_tce_correction( fapi2::buffer& io_data, const mss::states i_v /// @param[in] i_data the data buffer containing the RECR register /// @param[out] o_value ENABLE_UE_NOISE_WINDOW value (on or off) /// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > void get_enable_ue_noise_window( const fapi2::buffer& i_data, mss::states& o_value ) { o_value = (i_data.template getBit()) ? mss::states::ON : mss::states::OFF; @@ -391,7 +339,7 @@ void get_enable_ue_noise_window( const fapi2::buffer& i_data, mss::sta /// @param[in,out] io_data the target data buffer /// @param[in] i_value ENABLE_UE_NOISE_WINDOW value (on or off) to set /// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > void set_enable_ue_noise_window( fapi2::buffer& io_data, const mss::states i_value ) { FAPI_INF( "Set ENABLE_UE_NOISE_WINDOW to %lu", i_value); @@ -407,7 +355,7 @@ void set_enable_ue_noise_window( fapi2::buffer& io_data, const mss::st /// @param[in] i_target the target /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > fapi2::ReturnCode setup_read_pointer_delay (const fapi2::Target& i_target) { constexpr uint64_t MNFG_REPAIRS_DISABLED_ATTR = 56; @@ -415,7 +363,8 @@ fapi2::ReturnCode setup_read_pointer_delay (const fapi2::Target& i_target) fapi2::buffer l_mnfg_buffer; mss::states l_state = mss::OFF; - FAPI_TRY( mss::read_recr_register(i_target, l_data ), "%s: Failed read_recr_register", mss::c_str(i_target)); + FAPI_TRY( mss::read_recr_register(i_target, l_data ), "%s: Failed read_recr_register", + mss::c_str(i_target)); mss::set_read_pointer_delay(l_data, mss::ON); // Check for manufacturing disable dram repair flag to disable TCE correction @@ -423,7 +372,8 @@ fapi2::ReturnCode setup_read_pointer_delay (const fapi2::Target& i_target) l_state = ( l_mnfg_buffer.getBit() ) ? mss::OFF : mss::ON; mss::set_tce_correction(l_data, l_state); - FAPI_TRY( mss::write_recr_register(i_target, l_data), "%s: Failed write_recr_register", mss::c_str(i_target)); + FAPI_TRY( mss::write_recr_register(i_target, l_data), "%s: Failed write_recr_register", + mss::c_str(i_target)); fapi_try_exit: return fapi2::current_err; @@ -438,7 +388,7 @@ fapi_try_exit: /// @param[out] o_delay the buffer to write the register data into /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename TT = portTraits > +template< fapi2::TargetType T, typename TT = portTraits > fapi2::ReturnCode read_dsm0q_register( const fapi2::Target& i_target, fapi2::buffer& o_delay ) { FAPI_TRY( mss::getScom(i_target, TT::DSM0Q_REG, o_delay) ); @@ -457,7 +407,7 @@ fapi_try_exit: /// @param[in] i_delay the buffer that holds the register data to write /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename TT = portTraits > +template< fapi2::TargetType T, typename TT = portTraits > fapi2::ReturnCode write_dsm0q_register( const fapi2::Target& i_target, const fapi2::buffer i_delay ) { FAPI_INF( "Change Data State machine register to %d for %s", i_delay, mss::c_str(i_target) ); @@ -475,7 +425,7 @@ fapi_try_exit: /// @param[in] i_data the data buffer containing the DSM0Q register /// @param[out] o_delay WRDONE_DLY value (in cycles) /// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > void get_wrdone_delay( const fapi2::buffer& i_data, uint64_t& o_delay ) { i_data.template extractToRight(o_delay); @@ -490,7 +440,7 @@ void get_wrdone_delay( const fapi2::buffer& i_data, uint64_t& o_delay /// @param[in] i_delay WRDONE_DLY value (in cycles) to set /// @param[in,out] io_data the target data buffer /// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > void set_wrdone_delay( const uint64_t i_delay, fapi2::buffer& io_data ) { FAPI_INF( "Set WRDONE_DLY to %d ", i_delay); @@ -506,7 +456,7 @@ void set_wrdone_delay( const uint64_t i_delay, fapi2::buffer& io_data /// @param[in] i_delay WRDONE_DLY value (in cycles) to set /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename TT = portTraits > +template< fapi2::TargetType T, typename TT = portTraits > fapi2::ReturnCode change_wrdone_delay( const fapi2::Target& i_target, const uint64_t i_delay ) { fapi2::buffer l_data; @@ -530,7 +480,7 @@ fapi_try_exit: /// @param[in] i_data the data buffer containing the DSM0Q register /// @param[out] o_delay RDTAG_DLY value (in cycles) /// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > void get_rdtag_delay( const fapi2::buffer& i_data, uint64_t& o_delay ) { i_data.template extractToRight(o_delay); @@ -545,7 +495,7 @@ void get_rdtag_delay( const fapi2::buffer& i_data, uint64_t& o_delay ) /// @param[in] i_delay RDTAG_DLY value (in cycles) to set /// @param[in,out] io_data the target data buffer /// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > void set_rdtag_delay( const uint64_t i_delay, fapi2::buffer& io_data ) { FAPI_DBG( "Set RDTAG_DLY to %d ", i_delay); @@ -562,7 +512,7 @@ void set_rdtag_delay( const uint64_t i_delay, fapi2::buffer& io_data ) /// @param[in] i_delay new RDTAG_DLY value (in cycles) to set /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename TT = portTraits > +template< fapi2::TargetType T, typename TT = portTraits > fapi2::ReturnCode change_rdtag_delay( const fapi2::Target& i_target, const uint64_t i_delay ) { fapi2::buffer l_data; @@ -587,7 +537,7 @@ fapi_try_exit: /// @param[out] o_time the buffer to read the register data into /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename TT = portTraits > +template< fapi2::TargetType T, typename TT = portTraits > fapi2::ReturnCode read_farb0q_register( const fapi2::Target& i_target, fapi2::buffer& o_time ) { FAPI_TRY( mss::getScom(i_target, TT::FARB0Q_REG, o_time) ); @@ -606,7 +556,7 @@ fapi_try_exit: /// @param[in] i_delay the buffer containing the data to be written /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename TT = portTraits > +template< fapi2::TargetType T, typename TT = portTraits > fapi2::ReturnCode write_farb0q_register( const fapi2::Target& i_target, const fapi2::buffer i_time ) { FAPI_INF( "Change FARB0Q_REG to 0x%016lx for %s", uint64_t(i_time), mss::c_str(i_target) ); @@ -624,7 +574,7 @@ fapi_try_exit: /// @param[in] i_data the data buffer containing the FARB0Q register /// @param[out] o_time RCD_PROTECT_TIME value (in cycles) /// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > void get_rcd_protect_time( const fapi2::buffer& i_data, uint64_t& o_time ) { i_data.template extractToRight(o_time); @@ -640,7 +590,7 @@ void get_rcd_protect_time( const fapi2::buffer& i_data, uint64_t& o_ti /// @param[in] i_delay RCD Protect Time value (in cycles) to set /// @param[in,out] io_data the target data buffer /// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > void set_rcd_protect_time( const uint64_t i_time, fapi2::buffer& io_data ) { FAPI_DBG( "Set RCD_PROTECT_TIME to %d ", i_time); @@ -656,7 +606,7 @@ void set_rcd_protect_time( const uint64_t i_time, fapi2::buffer& io_da /// @param[in] i_time RCD Protect Time value (in cycles) to set /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename TT = portTraits > +template< fapi2::TargetType T, typename TT = portTraits > fapi2::ReturnCode change_rcd_protect_time( const fapi2::Target& i_target, const uint64_t i_time ) { fapi2::buffer l_data; @@ -673,28 +623,6 @@ fapi_try_exit: return fapi2::current_err; } -/// -/// @brief Change the state of the port_fail_disable bit -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in] i_target the target -/// @param[in] i_state the state -/// @return FAPI2_RC_SUCCESS if and only if ok -/// @note Disable Port Fail after recurring RCD errors. -/// -template< fapi2::TargetType T, typename TT = portTraits > -fapi2::ReturnCode change_port_fail_disable( const fapi2::Target& i_target, states i_state ) -{ - fapi2::buffer l_data; - - FAPI_DBG("Change port fail disable to %s %s", (i_state == HIGH ? "high" : "low"), mss::c_str(i_target)); - FAPI_TRY( mss::getScom(i_target, TT::FARB0Q_REG, l_data) ); - l_data.writeBit(i_state); - FAPI_TRY( mss::putScom(i_target, TT::FARB0Q_REG, l_data) ); - -fapi_try_exit: - return fapi2::current_err; -} /// /// @brief Change the state of the RCD recovery bit @@ -704,7 +632,7 @@ fapi_try_exit: /// @param[in] i_state the state /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename TT = portTraits > +template< fapi2::TargetType T, typename TT = portTraits > fapi2::ReturnCode change_rcd_recovery_disable( const fapi2::Target& i_target, states i_state ) { fapi2::buffer l_data; @@ -726,7 +654,7 @@ fapi_try_exit: /// @param[in] i_state the state /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename TT = portTraits > +template< fapi2::TargetType T, typename TT = portTraits > fapi2::ReturnCode change_oe_always_on( const fapi2::Target& i_target, states i_state ) { fapi2::buffer l_data; @@ -740,50 +668,6 @@ fapi_try_exit: return fapi2::current_err; } -/// -/// @brief Change the state of the addr_mux_sel bit -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in] i_target the target -/// @param[in] i_state the state -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template< fapi2::TargetType T, typename TT = portTraits > -fapi2::ReturnCode change_addr_mux_sel( const fapi2::Target& i_target, states i_state ) -{ - fapi2::buffer l_data; - - FAPI_DBG("Change addr_mux_sel to %s %s", (i_state == HIGH ? "high" : "low"), mss::c_str(i_target)); - FAPI_TRY( mss::getScom(i_target, TT::FARB5Q_REG, l_data) ); - l_data.writeBit(i_state); - FAPI_TRY( mss::putScom(i_target, TT::FARB5Q_REG, l_data) ); - -fapi_try_exit: - return fapi2::current_err; -} - - -/// -/// @brief Change the state of the MC Refresh enable bit -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in] i_target the target -/// @param[in] i_state the state -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template< fapi2::TargetType T, typename TT = portTraits > -fapi2::ReturnCode change_refresh_enable( const fapi2::Target& i_target, states i_state ) -{ - fapi2::buffer l_data; - - FAPI_DBG("Change refresh enable to %s %s", (i_state == HIGH ? "high" : "low"), mss::c_str(i_target)); - FAPI_TRY( mss::getScom(i_target, TT::REFRESH_REG, l_data) ); - l_data.writeBit(i_state); - FAPI_TRY( mss::putScom(i_target, TT::REFRESH_REG, l_data) ); - -fapi_try_exit: - return fapi2::current_err; -} /// /// @brief Enable the MC Periodic calibration functionality @@ -792,7 +676,7 @@ fapi_try_exit: /// @param[in] i_target the target /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename TT = portTraits > +template< fapi2::TargetType T, typename TT = portTraits > fapi2::ReturnCode enable_periodic_cal( const fapi2::Target& i_target ); /// @@ -803,45 +687,6 @@ fapi2::ReturnCode enable_periodic_cal( const fapi2::Target& i_target ); template<> fapi2::ReturnCode enable_periodic_cal( const fapi2::Target& i_target ); -/// -/// @brief Enable Read ECC checking -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in] i_target the target -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template< fapi2::TargetType T, typename TT = portTraits > -fapi2::ReturnCode enable_read_ecc( const fapi2::Target& i_target ) -{ - fapi2::buffer l_data; - - uint8_t l_sim = 0; - FAPI_TRY( mss::is_simulation(l_sim) ); - - FAPI_DBG("Enable Read ECC %s", mss::c_str(i_target)); - - FAPI_TRY( mss::getScom(i_target, TT::ECC_REG, l_data) ); - l_data.clearBit(); - l_data.clearBit(); - - // VBU tests assume good ECC and we don't have good ECC (since we're not writing everything) - // so we can't run with address checking. Disable address checking in sim. - l_data.writeBit(l_sim ? 0 : 1); - - // The preferred operating mode is 11 (INVERT_DATA_TOGGLE_CHECKS) which stores data complemented - // (because most bits are '0', and the dram bus pulls up, so transmitting 1s is least power) but - // still flips the inversion of check bits to aid RAS. Per Brad Michael 12/15 - // Leave un-inverted for sim. This allows the DIMM loader to write 0's and effect good ECC - l_data.insertFromRight(l_sim ? 0b00 : 0b11); - - // bits: 60 MBSTRQ_CFG_MAINT_RCE_WITH_CE - // cfg_maint_rce_with_ce - not implemented. Need to investigate if needed for nimbus. - - FAPI_TRY( mss::putScom(i_target, TT::ECC_REG, l_data) ); - -fapi_try_exit: - return fapi2::current_err; -} // // We expect to come in to draminit with the following setup: @@ -860,7 +705,7 @@ fapi_try_exit: // This is in this header as it's hoped to be able to be shared. Seems to make more // Might make more sense in p9_mss_draminit.C ... BRS /// -template< fapi2::TargetType T, typename TT = portTraits > +template< fapi2::TargetType T, typename TT = portTraits > inline fapi2::ReturnCode draminit_entry_invariant( const fapi2::Target& i_target ) { fapi2::buffer l_data; @@ -889,7 +734,7 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS if and only if ok /// @note this might need a port id added for Centaur/MBA controllers /// -template< fapi2::TargetType T, typename TT = portTraits > +template< fapi2::TargetType T, typename TT = portTraits > fapi2::ReturnCode drive_mem_clks( const fapi2::Target& i_target, const uint64_t i_pclk, const uint64_t i_nclk ) { fapi2::buffer l_data; @@ -918,7 +763,7 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS if and only if ok /// @note this might need a port id added for Centaur/MBA controllers /// -template< fapi2::TargetType T, typename TT = portTraits > +template< fapi2::TargetType T, typename TT = portTraits > fapi2::ReturnCode ddr_resetn( const fapi2::Target& i_target, const bool i_state ) { fapi2::buffer l_data; @@ -950,36 +795,6 @@ fapi_try_exit: return fapi2::current_err; } -/// -/// @brief Apply mark store bits from module VPD -/// @tparam T, the fapi2 target type of the target -/// @tparam TT, the class traits for the port -/// @param[in] i_target A target representing a port -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template< fapi2::TargetType T, typename TT = portTraits > -fapi2::ReturnCode apply_mark_store( const fapi2::Target& i_target ) -{ - FAPI_INF("Enable marks from MVPD"); - - uint32_t l_fwms[MARK_STORE_COUNT]; - - FAPI_TRY( mss::mvpd_fwms(i_target, &(l_fwms[0])) ); - - for (size_t l_mark = 0; l_mark < MARK_STORE_COUNT; ++l_mark) - { - if (l_fwms[l_mark] != 0) - { - fapi2::buffer l_fwms_data; - l_fwms_data.insertFromRight < MCA_FWMS0_MARK, MCA_FWMS0_EXIT_1 - MCA_FWMS0_MARK + 1 > (l_fwms[l_mark]); - FAPI_TRY( mss::putScom(i_target, MCA_FWMS0 + l_mark, l_fwms_data) ); - } - } - -fapi_try_exit: - return fapi2::current_err; -} - /// /// @brief Reset the ZCAL config register. /// @warning This maps PHY rank numbers per target @@ -987,7 +802,7 @@ fapi_try_exit: /// @param[in] i_target A target representing a port /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename TT = portTraits > +template< fapi2::TargetType T, typename TT = portTraits > fapi2::ReturnCode reset_zqcal_config( const fapi2::Target& i_target ) { fapi2::buffer l_phy_zqcal_config; @@ -1016,7 +831,7 @@ fapi_try_exit: /// inline fapi2::ReturnCode configure_wrq(const fapi2::Target& i_target, const mss::states i_state) { - typedef portTraits TT; + typedef portTraits TT; fapi2::buffer l_data; @@ -1064,7 +879,7 @@ fapi_try_exit: /// inline fapi2::ReturnCode configure_rrq(const fapi2::Target& i_target, const mss::states i_state) { - typedef portTraits TT; + typedef portTraits TT; fapi2::buffer l_data; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H index e27f82f69..d5840df40 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H @@ -14329,28 +14329,6 @@ fapi_try_exit: return fapi2::current_err; } -/// -/// @brief ATTR_MSS_MRW_POWER_CONTROL_REQUESTED getter -/// @param[out] uint8_t& reference to store the value -/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory power control settings programmed during IPL Used by OCC when exiting -/// idle power-save -/// mode -/// -inline fapi2::ReturnCode mrw_power_control_requested(uint8_t& o_value) -{ - - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_POWER_CONTROL_REQUESTED, fapi2::Target(), - o_value) ); - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_MRW_POWER_CONTROL_REQUESTED: 0x%lx (system target)", - uint64_t(fapi2::current_err)); - return fapi2::current_err; -} - /// /// @brief ATTR_MSS_MRW_IDLE_POWER_CONTROL_REQUESTED getter /// @param[out] uint8_t& reference to store the value @@ -21478,6 +21456,51 @@ fapi_try_exit: } +/// +/// @brief ATTR_MEM_MRW_IS_PLANAR getter +/// @param[in] const ref to the TARGET_TYPE_OCMB_CHIP +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generateParameters (PROC_CHIP) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Indicates if the DIMM connected to this controller are in a planar +/// configuration +/// +inline fapi2::ReturnCode mem_mrw_is_planar(const fapi2::Target& i_target, + uint8_t& o_value) +{ + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_MRW_IS_PLANAR, i_target, o_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed accessing ATTR_MEM_MRW_IS_PLANAR: 0x%lx", + uint64_t(fapi2::current_err)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MSS_MRW_POWER_CONTROL_REQUESTED getter +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Memory power control settings programmed during IPL Used by OCC when exiting +/// idle power-save +/// mode +/// +inline fapi2::ReturnCode mrw_power_control_requested(uint8_t& o_value) +{ + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_POWER_CONTROL_REQUESTED, fapi2::Target(), + o_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed accessing ATTR_MSS_MRW_POWER_CONTROL_REQUESTED: 0x%lx (system target)", + uint64_t(fapi2::current_err)); + return fapi2::current_err; +} + + } #endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H index 7c89b99a6..510cc1a19 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H @@ -43,6 +43,8 @@ namespace mss { +constexpr mss::mc_type DEFAULT_MC_TYPE = mss::mc_type::NIMBUS; + enum sizes { PORTS_PER_MCS = 2, @@ -74,7 +76,6 @@ enum sizes NUM_LRDIMM_TRAINING_PATTERNS = 5, ///< Used for ATTR_MSS_LRDIMM_TRAINING_PATTERN - MARK_STORE_COUNT = 8, ///< Elements in a VPD mark/store array BAD_DQ_BYTE_COUNT = 10, ///< Elements in a BAD_DQ_BITMAP attribute array ROW_REPAIR_BYTE_COUNT = 4, ///< Elements in a ROW_REPAIR_DATA attribute array. @@ -216,29 +217,6 @@ enum ffdc_function_codes MREP_CALL_OUT = 131, }; -enum states -{ - LOW = 0, - HIGH = 1, - START = 1, - STOP = 0, - START_N = 0, - STOP_N = 1, - ON = 1, - OFF = 0, - ON_N = 0, - OFF_N = 1, - YES = 1, - NO = 0, - YES_N = 0, - NO_N = 1, - // Uses "_" in the name for INVALID as INVALID is defined as a macro in the - // FSP code. If we just use INVALID as an enum name, then the preprocessor - // compile phase changes it to be the macro. - _INVALID_ = 0xFF, - NO_CHIP_SELECT_ACTIVE = 0xFF, -}; - // Static consts describing the bits used in the cal_step_enable attribute // These are bit positions. 0 is the left most bit. enum cal_steps : uint64_t diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.C index f5d6aaefd..4e102cd20 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.C @@ -41,6 +41,7 @@ #include #include #include +#include using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_MCA; diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml index 609ca575b..2e8fb7167 100755 --- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml @@ -241,21 +241,6 @@ - - ATTR_MSS_MRW_POWER_CONTROL_REQUESTED - TARGET_TYPE_SYSTEM - - Memory power control settings programmed during IPL - Used by OCC when exiting idle power-save mode - - uint8 - OFF = 0x00, POWER_DOWN = 0x01, PD_AND_STR = 0x02, PD_AND_STR_CLK_STOP = 0x03 - - OFF - - mrw_power_control_requested - - ATTR_MSS_MRW_IDLE_POWER_CONTROL_REQUESTED TARGET_TYPE_SYSTEM diff --git a/src/import/generic/memory/lib/mss_generic_attribute_getters.H b/src/import/generic/memory/lib/mss_generic_attribute_getters.H index f6bcf81fd..96024c17e 100644 --- a/src/import/generic/memory/lib/mss_generic_attribute_getters.H +++ b/src/import/generic/memory/lib/mss_generic_attribute_getters.H @@ -2761,6 +2761,28 @@ fapi_try_exit: } +/// +/// @brief ATTR_MSS_MRW_POWER_CONTROL_REQUESTED getter +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_other_attr_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Memory power control settings programmed during IPL Used by OCC when exiting idle +/// power-save mode +/// +inline fapi2::ReturnCode get_mrw_power_control_requested(uint8_t& o_value) +{ + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_POWER_CONTROL_REQUESTED, fapi2::Target(), + o_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MSS_MRW_POWER_CONTROL_REQUESTED: 0x%lx", + uint64_t(fapi2::current_err)); + return fapi2::current_err; +} + + } // attr } // mss diff --git a/src/import/generic/memory/lib/utils/index.H b/src/import/generic/memory/lib/utils/index.H index 828dc3fa6..dc60b8c19 100644 --- a/src/import/generic/memory/lib/utils/index.H +++ b/src/import/generic/memory/lib/utils/index.H @@ -90,6 +90,19 @@ inline size_t index(const fapi2::Target& i_target) return mss::pos(i_target) % TT::MCS_PER_MC; } +/// +/// @brief Return an attribute array index from a OCMB target +/// @param[in] i_target a MEM_PORT target representing the OCMB in question +/// @return size_t the attribute array index. +/// +template<> +inline size_t index(const fapi2::Target& i_target) +{ + typedef procTraits TT; + // We may need to revisit this later if we get an OCMB that has more than one port. + return mss::pos(i_target) % TT::EXP_PORTS_PER_OCMB; +} + /// /// @brief Return an attribute array index from a rank number /// @param[in] i_rank uint64_t a rank number DIMM0 {0, 1, 2, 3} DIMM1 {0, 1, 2, 3} diff --git a/src/import/generic/memory/lib/utils/mc/gen_mss_port.H b/src/import/generic/memory/lib/utils/mc/gen_mss_port.H index bb3725d94..e44601ac2 100644 --- a/src/import/generic/memory/lib/utils/mc/gen_mss_port.H +++ b/src/import/generic/memory/lib/utils/mc/gen_mss_port.H @@ -22,3 +22,396 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file gen_mss_port.H +/// @brief Code to support ports +/// +// *HWP HWP Owner: Stephen Glancy +// *HWP HWP Backup: Andre Marin +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: HB:FSP + + +#ifndef _GEN_MSS_PORT_H_ +#define _GEN_MSS_PORT_H_ + +#include +#include +#include +#include +#include + +namespace mss +{ + +/// +/// @brief ATTR_MSS_MVPD_FWMS getter declare +/// @tparam MC the memory controller type +/// @tparam T the fapi2 target type of the target +/// @param[in] const ref to the fapi2::Target +/// @param[out] uint32_t* memory to store the value +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Mark store records from MPVD Lx +/// keyword +/// +template< mss::mc_type MC = DEFAULT_MC_TYPE, fapi2::TargetType T> +inline fapi2::ReturnCode mvpd_fwms(const fapi2::Target< T>& i_target, uint32_t (&o_array)[MARK_STORE_COUNT]); + +/// +/// @brief Enable power management +/// @tparam MC the memory controller type +/// @tparam T the fapi2 target type of the target +/// @tparam TT the class traits for the port +/// @param[in] i_target the target +/// @return FAPI2_RC_SUCCESS if and only if ok +/// +template< mss::mc_type MC = DEFAULT_MC_TYPE, fapi2::TargetType T, typename TT = portTraits > +fapi2::ReturnCode enable_power_management( const fapi2::Target& i_target ) +{ + //Enable Power management based off of mrw_power_control_requested + FAPI_INF("%s Enable Power min max domains", mss::c_str(i_target)); + + bool is_pwr_cntrl = true; + fapi2::buffer l_data; + uint8_t l_pwr_cntrl = 0; + + // Get the value from attribute and write it to scom register + FAPI_TRY(fapi2::getScom(i_target, TT::MBARPC0Q_REG, l_data)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_POWER_CONTROL_REQUESTED, fapi2::Target(), + l_pwr_cntrl)); + + is_pwr_cntrl = ((l_pwr_cntrl == fapi2::ENUM_ATTR_MSS_MRW_POWER_CONTROL_REQUESTED_POWER_DOWN) + || (l_pwr_cntrl == fapi2::ENUM_ATTR_MSS_MRW_IDLE_POWER_CONTROL_REQUESTED_PD_AND_STR) + || (l_pwr_cntrl == fapi2::ENUM_ATTR_MSS_MRW_IDLE_POWER_CONTROL_REQUESTED_PD_AND_STR_CLK_STOP)); + + l_data.writeBit< TT::CFG_MIN_MAX_DOMAINS_ENABLE>(is_pwr_cntrl); + FAPI_TRY( fapi2::putScom(i_target, TT::MBARPC0Q_REG, l_data) ); + + +fapi_try_exit: + return fapi2::current_err; +} + + +/// +/// @brief Set the IML init complete bit +/// @tparam MC the memory controller type +/// @tparam T the fapi2 target type of the target +/// @tparam TT the class traits for the port +/// @param[in] i_target the target +/// @param[in] i_state the state +/// @return FAPI2_RC_SUCCESS if and only if ok +/// +template< mss::mc_type MC = DEFAULT_MC_TYPE, fapi2::TargetType T, typename TT = portTraits > +fapi2::ReturnCode change_iml_complete( const fapi2::Target& i_target, states i_state ) +{ + fapi2::buffer l_data; + + FAPI_DBG("Change the IML init complete bit to high for %s %s", (i_state == HIGH ? "high" : "low"), + mss::c_str(i_target)); + FAPI_TRY( mss::getScom(i_target, TT::FARB6Q_REG, l_data) ); + l_data.writeBit(i_state); + FAPI_TRY( mss::putScom(i_target, TT::FARB6Q_REG, l_data) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Read the read ECC Control register +/// @tparam MC the memory controller type +/// @tparam T the fapi2 target type of the target +/// @tparam TT the class traits for the port +/// @param[in] i_target the target +/// @param[out] o_buffer the buffer to write the register data into +/// @return FAPI2_RC_SUCCESS if and only if ok +/// +template< mss::mc_type MC = DEFAULT_MC_TYPE, fapi2::TargetType T, typename TT = portTraits > +fapi2::ReturnCode read_recr_register( const fapi2::Target& i_target, fapi2::buffer& o_buffer ) +{ + FAPI_TRY( mss::getScom(i_target, TT::ECC_REG, o_buffer) ); + + FAPI_INF( "Read ECC Control register is 0x%016lx for %s", uint64_t(o_buffer), mss::c_str(i_target) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Write to RECR register +/// @tparam MC the memory controller type +/// @tparam T the fapi2 target type of the target +/// @tparam TT the class traits for the port +/// @param[in] i_target the target +/// @param[in] i_buffer the buffer that holds the register data to write +/// @return FAPI2_RC_SUCCESS if and only if ok +/// +template< mss::mc_type MC = DEFAULT_MC_TYPE, fapi2::TargetType T, typename TT = portTraits > +fapi2::ReturnCode write_recr_register( const fapi2::Target& i_target, const fapi2::buffer& i_buffer ) +{ + FAPI_INF( "Change Read ECC Control register to 0x%016lx for %s", i_buffer, mss::c_str(i_target) ); + + FAPI_TRY( mss::putScom(i_target, TT::ECC_REG, i_buffer) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Get the tce correction enable value from RECR +/// @tparam MC the memory controller type +/// @tparam TT the class traits for the port +/// @param[in] i_data the data buffer containing the RECR register +/// @param[out] o_value TCE_CORRECTION_ENABLE value (on or off) +/// +template< mss::mc_type MC = DEFAULT_MC_TYPE, typename TT = portTraits > +void get_tce_correction( const fapi2::buffer& i_data, mss::states& o_value ) +{ + o_value = i_data.template getBit() ? mss::states::ON : mss::states::OFF; + + FAPI_INF( "TCE_CORRECTION_ENABLE: %lu", o_value ); +} + +/// +/// @brief Sets tce correction enable in buffer +/// @tparam MC the memory controller type +/// @tparam TT the class traits for the port +/// @param[in,out] io_data the target data buffer +/// @param[in] i_value TCE_CORRECTION_ENABLE value (on or off) to set +/// +template< mss::mc_type MC = DEFAULT_MC_TYPE, typename TT = portTraits > +void set_tce_correction( fapi2::buffer& io_data, const mss::states i_value ) +{ + FAPI_INF( "Set TCE_CORRECTION_ENABLE to %lu", i_value); + + io_data.template writeBit(i_value); +} + +/// +/// @brief Setup TCE correction +/// @tparam MC the memory controller type +/// @tparam T the fapi2 target type of the target +/// @tparam TT the class traits for the port +/// @param[in] i_target the target +/// @return FAPI2_RC_SUCCESS if and only if ok +/// +template< mss::mc_type MC = DEFAULT_MC_TYPE, fapi2::TargetType T, typename TT = portTraits > +fapi2::ReturnCode setup_tce_correction (const fapi2::Target& i_target) +{ + constexpr uint64_t MNFG_REPAIRS_DISABLED_ATTR = 56; + fapi2::buffer l_data; + fapi2::buffer l_mnfg_buffer; + mss::states l_state = mss::OFF; + + FAPI_TRY( mss::read_recr_register(i_target, l_data ), "%s: Failed read_recr_register", mss::c_str(i_target)); + + // Check for manufacturing disable dram repair flag to disable TCE correction + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MNFG_FLAGS, fapi2::Target(), l_mnfg_buffer), + "%s: Failed mnfg_flags check", mss::c_str(i_target) ); + l_state = ( l_mnfg_buffer.getBit() ) ? mss::OFF : mss::ON; + mss::set_tce_correction(l_data, l_state); + + FAPI_TRY( mss::write_recr_register(i_target, l_data), "%s: Failed write_recr_register", mss::c_str(i_target)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Change the state of the port_fail_disable bit +/// @tparam MC the memory controller type +/// @tparam T the fapi2 target type of the target +/// @tparam TT the class traits for the port +/// @param[in] i_target the target +/// @param[in] i_state the state +/// @return FAPI2_RC_SUCCESS if and only if ok +/// @note Disable Port Fail after recurring RCD errors. +/// +template< mss::mc_type MC = DEFAULT_MC_TYPE, fapi2::TargetType T, typename TT = portTraits > +fapi2::ReturnCode change_port_fail_disable( const fapi2::Target& i_target, states i_state ) +{ + fapi2::buffer l_data; + + FAPI_DBG("Change port fail disable to %s %s", (i_state == HIGH ? "high" : "low"), mss::c_str(i_target)); + FAPI_TRY( mss::getScom(i_target, TT::FARB0Q_REG, l_data) ); + l_data.writeBit(i_state); + FAPI_TRY( mss::putScom(i_target, TT::FARB0Q_REG, l_data) ); + +fapi_try_exit: + return fapi2::current_err; +} + + +/// +/// @brief Change the state of the dfi init start bit +/// @tparam MC the memory controller type +/// @tparam T the fapi2 target type of the target +/// @tparam TT the class traits for the port +/// @param[in] i_target the target +/// @param[in] i_state the state +/// @return FAPI2_RC_SUCCESS if and only if ok +/// +template< mss::mc_type MC = DEFAULT_MC_TYPE, fapi2::TargetType T, typename TT = portTraits > +fapi2::ReturnCode change_dfi_init_start( const fapi2::Target& i_target, states i_state ) +{ + fapi2::buffer l_data; + + FAPI_DBG("Change rcd recovery disable to %s %s", (i_state == HIGH ? "high" : "low"), mss::c_str(i_target)); + FAPI_TRY( mss::getScom(i_target, TT::FARB0Q_REG, l_data) ); + l_data.writeBit(i_state); + FAPI_TRY( mss::putScom(i_target, TT::FARB0Q_REG, l_data) ); + +fapi_try_exit: + return fapi2::current_err; +} + + +/// +/// @brief Change the state of the addr_mux_sel bit +/// @tparam MC the memory controller type +/// @tparam T the fapi2 target type of the target +/// @tparam TT the class traits for the port +/// @param[in] i_target the target +/// @param[in] i_state the state +/// @return FAPI2_RC_SUCCESS if and only if ok +/// +template< mss::mc_type MC = DEFAULT_MC_TYPE, fapi2::TargetType T, typename TT = portTraits > +fapi2::ReturnCode change_addr_mux_sel( const fapi2::Target& i_target, states i_state ) +{ + fapi2::buffer l_data; + + FAPI_DBG("Change addr_mux_sel to %s %s", (i_state == HIGH ? "high" : "low"), mss::c_str(i_target)); + FAPI_TRY( mss::getScom(i_target, TT::FARB5Q_REG, l_data) ); + l_data.writeBit(i_state); + FAPI_TRY( mss::putScom(i_target, TT::FARB5Q_REG, l_data) ); + +fapi_try_exit: + return fapi2::current_err; +} + + +/// +/// @brief Change the state of the MC Refresh enable bit +/// @tparam MC the memory controller type +/// @tparam T the fapi2 target type of the target +/// @tparam TT the class traits for the port +/// @param[in] i_target the target +/// @param[in] i_state the state +/// @return FAPI2_RC_SUCCESS if and only if ok +/// +template< mss::mc_type MC = DEFAULT_MC_TYPE, fapi2::TargetType T, typename TT = portTraits > +fapi2::ReturnCode change_refresh_enable( const fapi2::Target& i_target, states i_state ) +{ + fapi2::buffer l_data; + + FAPI_DBG("Change refresh enable to %s %s", (i_state == HIGH ? "high" : "low"), mss::c_str(i_target)); + FAPI_TRY( mss::getScom(i_target, TT::REFRESH_REG, l_data) ); + l_data.writeBit(i_state); + FAPI_TRY( mss::putScom(i_target, TT::REFRESH_REG, l_data) ); + +fapi_try_exit: + return fapi2::current_err; +} + + +/// +/// @brief Enable periodic zq cal +/// @tparam MC the memory controller type +/// @tparam T the fapi2 target type of the target +/// @tparam TT the class traits for the port +/// @param[in] i_target the target +/// @return FAPI2_RC_SUCCESS if and only if ok +/// +template< mss::mc_type MC = DEFAULT_MC_TYPE, fapi2::TargetType T, typename TT = portTraits > +fapi2::ReturnCode enable_zq_cal( const fapi2::Target& i_target ) +{ + fapi2::buffer l_data; + + FAPI_DBG("Enable periodic zq cal for %s", mss::c_str(i_target)); + FAPI_TRY( mss::getScom(i_target, TT::FARB9Q_REG, l_data) ); + l_data.writeBit(mss::HIGH); + FAPI_TRY( mss::putScom(i_target, TT::FARB9Q_REG, l_data) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Enable Read ECC checking +/// @tparam MC the memory controller type +/// @tparam T the fapi2 target type of the target +/// @tparam TT the class traits for the port +/// @param[in] i_target the target +/// @return FAPI2_RC_SUCCESS if and only if ok +/// +template< mss::mc_type MC = DEFAULT_MC_TYPE, fapi2::TargetType T, typename TT = portTraits > +fapi2::ReturnCode enable_read_ecc( const fapi2::Target& i_target ) +{ + fapi2::buffer l_data; + + uint8_t l_sim = 0; + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION, fapi2::Target(), l_sim) ); + + FAPI_DBG("Enable Read ECC %s", mss::c_str(i_target)); + + FAPI_TRY( mss::getScom(i_target, TT::ECC_REG, l_data) ); + l_data.clearBit(); + l_data.clearBit(); + + // VBU tests assume good ECC and we don't have good ECC (since we're not writing everything) + // so we can't run with address checking. Disable address checking in sim. + l_data.writeBit(l_sim ? 0 : 1); + + // The preferred operating mode is 11 (INVERT_DATA_TOGGLE_CHECKS) which stores data complemented + // (because most bits are '0', and the dram bus pulls up, so transmitting 1s is least power) but + // still flips the inversion of check bits to aid RAS. Per Brad Michael 12/15 + // Leave un-inverted for sim. This allows the DIMM loader to write 0's and effect good ECC + l_data.insertFromRight(l_sim ? 0b00 : 0b11); + + // bits: 60 MBSTRQ_CFG_MAINT_RCE_WITH_CE + // cfg_maint_rce_with_ce - not implemented. Need to investigate if needed for nimbus. + + FAPI_TRY( mss::putScom(i_target, TT::ECC_REG, l_data) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Apply mark store bits from module VPD +/// @tparam MC the memory controller type +/// @tparam T, the fapi2 target type of the target +/// @tparam TT, the class traits for the port +/// @param[in] i_target A target representing a port +/// @return FAPI2_RC_SUCCESS if and only if ok +/// +template< mss::mc_type MC = DEFAULT_MC_TYPE, fapi2::TargetType T, typename TT = portTraits > +fapi2::ReturnCode apply_mark_store( const fapi2::Target& i_target ) +{ + FAPI_INF("Enable marks from MVPD %s", mss::c_str(i_target)); + + uint32_t l_fwms[MARK_STORE_COUNT]; + + FAPI_TRY( mss::mvpd_fwms(i_target, l_fwms) ); + + for (size_t l_mark = 0; l_mark < MARK_STORE_COUNT; ++l_mark) + { + if (l_fwms[l_mark] != 0) + { + fapi2::buffer l_fwms_data; + // This assumes the attribute contents are in the same format as the register fields, + // ending just before the EXIT_1 bit + l_fwms_data.insertFromRight < TT::FWMS0_MARK, TT::FWMS0_EXIT_1 - TT::FWMS0_MARK + 1 > (l_fwms[l_mark]); + FAPI_TRY( mss::putScom(i_target, TT::FWMS_REG + l_mark, l_fwms_data) ); + } + } + +fapi_try_exit: + return fapi2::current_err; +} + +}// ns mss + +#endif diff --git a/src/import/generic/memory/lib/utils/mc/gen_mss_port_traits.H b/src/import/generic/memory/lib/utils/mc/gen_mss_port_traits.H index 3d1dea5e6..34184a04b 100644 --- a/src/import/generic/memory/lib/utils/mc/gen_mss_port_traits.H +++ b/src/import/generic/memory/lib/utils/mc/gen_mss_port_traits.H @@ -22,3 +22,32 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file gen_mss_port_traits.H +/// @brief Contains the port traits definition +/// +// *HWP HWP Owner: Stephen Glancy +// *HWP HWP Backup: Andre Marin +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: HB:FSP + +#ifndef _GEN_MSS_PORT_TRAITS_H_ +#define _GEN_MSS_PORT_TRAITS_H_ + +#include + +namespace mss +{ + +/// +/// @class Traits and policy class for port +/// @tparam MC the memory controller type +/// +template< mss::mc_type MC> +class portTraits; + +} // ns mss + +#endif diff --git a/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H b/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H index ae4f9c2fc..4e7ed05d3 100644 --- a/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H +++ b/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H @@ -83,6 +83,7 @@ enum conversions enum generic_sizes { NUM_MAX_FREQS = 5, ///< Used for ATTR_MAX_ALLOWED_DIMM_FREQ + MARK_STORE_COUNT = 8, ///< Elements in a VPD mark/store array }; /// @@ -189,6 +190,30 @@ enum ddr_dimm_speeds DDR5_MAX_SPEED = 4800, }; +enum states +{ + LOW = 0, + HIGH = 1, + START = 1, + STOP = 0, + START_N = 0, + STOP_N = 1, + ON = 1, + OFF = 0, + ON_N = 0, + OFF_N = 1, + YES = 1, + NO = 0, + YES_N = 0, + NO_N = 1, + // Uses "_" in the name for INVALID as INVALID is defined as a macro in the + // FSP code. If we just use INVALID as an enum name, then the preprocessor + // compile phase changes it to be the macro. + _INVALID_ = 0xFF, + NO_CHIP_SELECT_ACTIVE = 0xFF, +}; + + namespace spd { @@ -294,6 +319,20 @@ struct procTraits }; }; +/// +/// @brief Trait classes for proc_type - AXONE specialization +/// +/// TODO: Need to add mc_type +template< > +struct procTraits +{ + enum + { + EXP_PORTS_PER_OCMB = 1, + }; +}; + + }// mss #endif diff --git a/src/import/generic/procedures/xml/attribute_info/generic_memory_mrw_attributes.xml b/src/import/generic/procedures/xml/attribute_info/generic_memory_mrw_attributes.xml index ba699ad18..faf8a75fb 100644 --- a/src/import/generic/procedures/xml/attribute_info/generic_memory_mrw_attributes.xml +++ b/src/import/generic/procedures/xml/attribute_info/generic_memory_mrw_attributes.xml @@ -22,7 +22,7 @@ - + ATTR_MEM_MRW_IS_PLANAR TARGET_TYPE_OCMB_CHIP @@ -38,4 +38,18 @@ mem_mrw_is_planar + + ATTR_MSS_MRW_POWER_CONTROL_REQUESTED + TARGET_TYPE_SYSTEM + + Memory power control settings programmed during IPL + Used by OCC when exiting idle power-save mode + + uint8 + OFF = 0x00, POWER_DOWN = 0x01, PD_AND_STR = 0x02, PD_AND_STR_CLK_STOP = 0x03 + + OFF + + mrw_power_control_requested + -- cgit v1.2.1