From 818acb95a2dc8ff8e94c652e0964f013c1bf34cb Mon Sep 17 00:00:00 2001 From: Ilya Smirnov Date: Tue, 11 Jul 2017 11:39:08 -0500 Subject: IPL Time Checkstop Analysis Part 1: Load OCC First part of the IPL Time Checkstop Analysis story. The OCC image gets loaded from the PNOR directly into SRAM in istep 6.11. The OCC is reset in step 21.1 and the image is reloaded to HOMER. Change-Id: I73ce96b81b311d7ae54356c64aeec816d52fafbb RTC:155065 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43574 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Zane C. Shelley Reviewed-by: Daniel M. Crowell --- src/include/usr/isteps/istep06list.H | 3 - src/include/usr/isteps/istep14list.H | 1 + src/include/usr/isteps/istep16list.H | 3 - src/include/usr/isteps/pm/occCheckstop.H | 32 +- src/include/usr/util/utillidmgr.H | 1 - src/usr/diag/HBconfig | 2 +- .../isteps/istep06/host_start_occ_xstop_handler.C | 102 +++---- src/usr/isteps/istep06/makefile | 2 +- src/usr/isteps/istep14/call_mss_memdiag.C | 2 - src/usr/isteps/istep21/call_host_runtime_setup.C | 2 +- src/usr/isteps/pm/occAccess.C | 5 +- src/usr/isteps/pm/occCheckstop.C | 340 +++++++-------------- src/usr/isteps/pm/pm.mk | 4 + src/usr/isteps/pm/pm_common.C | 144 +++++---- src/usr/isteps/pm/pm_common.H | 4 +- 15 files changed, 263 insertions(+), 384 deletions(-) (limited to 'src') diff --git a/src/include/usr/isteps/istep06list.H b/src/include/usr/isteps/istep06list.H index 073093812..fb14022b3 100644 --- a/src/include/usr/isteps/istep06list.H +++ b/src/include/usr/isteps/istep06list.H @@ -236,9 +236,6 @@ const DepModInfo g_istep06Dependancies = { DEP_LIB(libsbe.so), DEP_LIB(libpm.so), DEP_LIB(libp9_cpuWkup.so), -#ifdef CONFIG_IPLTIME_CHECKSTOP_ANALYSIS - DEP_LIB(libocc.so), -#endif NULL } }; diff --git a/src/include/usr/isteps/istep14list.H b/src/include/usr/isteps/istep14list.H index 5c57dfa87..b8b80af9b 100644 --- a/src/include/usr/isteps/istep14list.H +++ b/src/include/usr/isteps/istep14list.H @@ -198,6 +198,7 @@ const DepModInfo g_istep14Dependancies = { DEP_LIB(libistep14.so), DEP_LIB(libdump.so), DEP_LIB(libisteps_mss.so), + DEP_LIB(libpm.so), NULL } }; diff --git a/src/include/usr/isteps/istep16list.H b/src/include/usr/isteps/istep16list.H index bc7a05e0b..e11f02a5f 100644 --- a/src/include/usr/isteps/istep16list.H +++ b/src/include/usr/isteps/istep16list.H @@ -161,9 +161,6 @@ const DepModInfo g_istep16Dependancies = { DEP_LIB(libp9_cpuWkup.so), DEP_LIB(libisteps_mss.so), DEP_LIB(libpm.so), -#ifdef CONFIG_IPLTIME_CHECKSTOP_ANALYSIS - DEP_LIB(libocc.so), -#endif NULL } }; diff --git a/src/include/usr/isteps/pm/occCheckstop.H b/src/include/usr/isteps/pm/occCheckstop.H index 4fa55bfd4..10efd4897 100644 --- a/src/include/usr/isteps/pm/occCheckstop.H +++ b/src/include/usr/isteps/pm/occCheckstop.H @@ -47,17 +47,21 @@ namespace HBOCC NOT_FIR_MASTER = 0x00000000, IS_FIR_MASTER = 0x00000001, - // SRAM Address for OCC Main App - OCC_SRAM_ADDRESS = 0xFFF80000, + // SRAM Addresses for OCC Main App and GPE0 app + OCC_405_SRAM_ADDRESS = 0xFFF40000, + OCC_GPE0_SRAM_ADDRESS = 0xFFF01000, + OCC_GPE1_SRAM_ADDRESS = 0xFFF10000, // SRAM Address and length for FIR HOMER data - OCC_SRAM_FIR_DATA = 0xFFFF5000, - OCC_SRAM_FIR_LENGTH = 0x1000, + OCC_SRAM_FIR_DATA = 0xFFFBA000, + OCC_SRAM_FIR_LENGTH = 0x3000, // offsets for OCC loading during IPL - OCC_OFFSET_LENGTH = 0x48, - OCC_OFFSET_IPL_FLAG = 0x82, - OCC_OFFSET_FREQ = 0x84, + OCC_OFFSET_LENGTH = 0x48, + OCC_OFFSET_GPE0_LENGTH = 0x64, + OCC_OFFSET_GPE1_LENGTH = 0x68, + OCC_OFFSET_IPL_FLAG = 0x92, + OCC_OFFSET_FREQ = 0x94, }; @@ -92,6 +96,20 @@ namespace HBOCC const PRDF::HwInitialized_t i_curHw = PRDF::ALL_HARDWARE); #endif +#ifdef CONFIG_IPLTIME_CHECKSTOP_ANALYSIS + /** + * @brief Loads the OCC image from PNOR to SRAM + * + * @param[in] i_target: the proc we're operating on (should be masterproc) + * @param[in] i_occVirtAddr: the address of the page allocated for OCC + * bootloader. + * + * @return errlHndl_t Error log if load fails + */ + errlHndl_t loadOCCImageDuringIpl(TARGETING::Target* i_target, + void* i_occVirtAddr); +#endif + /** * @brief Execute procedures and steps required to load * OCC data in a specified processor diff --git a/src/include/usr/util/utillidmgr.H b/src/include/usr/util/utillidmgr.H index 9939fbe64..cda762f66 100644 --- a/src/include/usr/util/utillidmgr.H +++ b/src/include/usr/util/utillidmgr.H @@ -191,7 +191,6 @@ class UtilLidMgr */ errlHndl_t releaseLidImage(void); -// @todo RTC 155065 IPL Time Checkstop Analysis Enablement #ifdef CONFIG_IPLTIME_CHECKSTOP_ANALYSIS /** * @brief Get lid managers' pointer to the lid vaddr. diff --git a/src/usr/diag/HBconfig b/src/usr/diag/HBconfig index 3c46d6e02..cf4aa6da8 100644 --- a/src/usr/diag/HBconfig +++ b/src/usr/diag/HBconfig @@ -10,7 +10,7 @@ config ENABLE_CHECKSTOP_ANALYSIS post-checkstop analysis by PRD on system reboot config IPLTIME_CHECKSTOP_ANALYSIS - default n + default y help Enable collection of FIR data by the OCC for checkstops during the IPL. diff --git a/src/usr/isteps/istep06/host_start_occ_xstop_handler.C b/src/usr/isteps/istep06/host_start_occ_xstop_handler.C index d21756260..d75a9ec62 100644 --- a/src/usr/isteps/istep06/host_start_occ_xstop_handler.C +++ b/src/usr/isteps/istep06/host_start_occ_xstop_handler.C @@ -29,83 +29,65 @@ #include #include #include +#include +#include +#include +#include namespace ISTEP_06 { void* host_start_occ_xstop_handler( void *io_pArgs ) { -// errlHndl_t l_err = NULL; - ISTEP_ERROR::IStepError l_stepError; + ISTEP_ERROR::IStepError l_stepError; - TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "host_start_occ_xstop_handler entry" ); - -//TODO RTC 125486 add host_start_occ_xstop_handler -#if 0 -/// This is a bunch of stuff that was put into P8 and git didn't handle -/// merging correctly. Some of this may be a useful starting point for -/// enabling OCC checkstop handling. -- Patrick - - "host_cancontinue_clear entry" ); - errlHndl_t errl = NULL; - #ifdef CONFIG_IPLTIME_CHECKSTOP_ANALYSIS - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "host_cancontinue_clear: calling activateOCCs" ); - errl = HBOCC::activateOCCs(true); - if (errl) + errlHndl_t l_errl = NULL; + TARGETING::Target * l_sys = nullptr; + TARGETING::targetService().getTopLevelTarget( l_sys ); + assert(l_sys != nullptr); + + TARGETING::Target* masterproc = NULL; + TARGETING::targetService().masterProcChipTargetHandle(masterproc); + + void* l_homerVirtAddrBase = reinterpret_cast + (VmmManager::INITIAL_MEM_SIZE); + uint64_t l_homerPhysAddrBase = mm_virt_to_phys(l_homerVirtAddrBase); + uint64_t l_commonPhysAddr = l_homerPhysAddrBase + VMM_HOMER_REGION_SIZE; + + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "host_start_occ_xstop_handler:" + " l_homerPhysAddrBase=0x%x, l_commonPhysAddr=0x%x", + l_homerPhysAddrBase, l_commonPhysAddr); + do { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "activateOCCs failed"); - } -#endif - - //Create IStep error log and cross reference error that occurred - l_stepError.addErrorDetails(errl); - - // Commit Error - errlCommit(errl, HWPF_COMP_ID); - - // Don't keep calling proc_enable_reconfig. Treat as a fatal - // unexpected unrecoverable error and terminate the IPL. - break ; // break with error - } - // Success + l_errl = HBPM::loadPMComplex(masterproc, + l_homerPhysAddrBase, + l_commonPhysAddr, + HBPM::PM_LOAD, + true); + if(l_errl) + { TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, - "Successfully ran proc_enable_reconfig HWP on " - "MCS target HUID %.8X", l_currMcsHuid); - } // for + "loadPMComplex failed"); + l_stepError.addErrorDetails(l_errl); + ERRORLOG::errlCommit(l_errl, HWPF_COMP_ID); + break; + } -#if defined(CONFIG_IPLTIME_CHECKSTOP_ANALYSIS) && !defined(__HOSTBOOT_RUNTIME) - // update firdata inputs for OCC - TARGETING::Target* masterproc = NULL; - TARGETING::targetService().masterProcChipTargetHandle(masterproc); - errl = HBOCC::loadHostDataToSRAM(masterproc, - PRDF::MASTER_PROC_CORE); - if (errl) + //l_errl = HBPM::startPMComplex(masterproc); + if(l_errl) { TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, - "Error returned from call to HBOCC::loadHostDataToSRAM"); - - //Create IStep error log and cross reference error that occurred - l_stepError.addErrorDetails(errl); - - // Commit Error - errlCommit(errl, HWPF_COMP_ID); + "startPMComplex failed"); + l_stepError.addErrorDetails(l_errl); + ERRORLOG::errlCommit(l_errl, HWPF_COMP_ID); break; } -#endif - } - while(0); - - TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "host_prd_hwreconfig exit" ); - // end task, returning any errorlogs to IStepDisp - return l_stepError.getErrorHandle(); + }while(0); #endif - - TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "host_start_occ_xstop_handler exit" ); return l_stepError.getErrorHandle(); diff --git a/src/usr/isteps/istep06/makefile b/src/usr/isteps/istep06/makefile index 0cef7c3f6..e18d1c2e5 100644 --- a/src/usr/isteps/istep06/makefile +++ b/src/usr/isteps/istep06/makefile @@ -62,7 +62,7 @@ EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/procedures/hwp/pm/include/registe EXTRAINCDIR += ${LIB_HWP_PATH} EXTRAINCDIR += ${CORE_HWP_PATH} EXTRAINCDIR += ${CACHE_HWP_PATH} - +EXTRAINCDIR += ${ROOTPATH}/src/usr/isteps #Required include before all the procedure.mk are included include ${ROOTPATH}/procedure.rules.mk diff --git a/src/usr/isteps/istep14/call_mss_memdiag.C b/src/usr/isteps/istep14/call_mss_memdiag.C index 52ca66af0..46793b35d 100644 --- a/src/usr/isteps/istep14/call_mss_memdiag.C +++ b/src/usr/isteps/istep14/call_mss_memdiag.C @@ -96,8 +96,6 @@ void* call_mss_memdiag (void* io_pArgs) TARGETING::targetService().masterProcChipTargetHandle(masterproc); #ifdef CONFIG_IPLTIME_CHECKSTOP_ANALYSIS - // @TODO-RTC: 155065 - // update firdata inputs for OCC errl = HBOCC::loadHostDataToSRAM(masterproc, PRDF::ALL_PROC_MEM_MASTER_CORE); assert(nullptr == errl, diff --git a/src/usr/isteps/istep21/call_host_runtime_setup.C b/src/usr/isteps/istep21/call_host_runtime_setup.C index dcad3c89b..48bda6b9b 100644 --- a/src/usr/isteps/istep21/call_host_runtime_setup.C +++ b/src/usr/isteps/istep21/call_host_runtime_setup.C @@ -270,7 +270,7 @@ void* call_host_runtime_setup (void *io_pArgs) uint64_t l_occAppData[(sz_data+(sz_dw-1))/sz_dw]; memset( l_occAppData, 0x00, sizeof(l_occAppData) ); - const uint32_t l_SramAddrApp = HBOCC::OCC_SRAM_ADDRESS; + const uint32_t l_SramAddrApp = HBOCC::OCC_405_SRAM_ADDRESS; l_err = HBOCC::writeSRAM( masterproc, l_SramAddrApp, l_occAppData, sz_data ); if(l_err) diff --git a/src/usr/isteps/pm/occAccess.C b/src/usr/isteps/pm/occAccess.C index 99e93681e..6d3ea9320 100644 --- a/src/usr/isteps/pm/occAccess.C +++ b/src/usr/isteps/pm/occAccess.C @@ -248,7 +248,7 @@ errlHndl_t accessOCBIndirectChannel(accessOCBIndirectCmd i_cmd, { TRACFCOMP( g_fapiImpTd, ERR_MRK"accessOCBIndirectChannel:" " Error [0x%X] in call to " - " FAPI_INVOKE_HWP(p8_ocb_indir_setup_linear)", + " FAPI_INVOKE_HWP(p9_pm_ocb_indir_setup_linear)", l_errl->reasonCode()); break; // return with error } @@ -270,11 +270,10 @@ errlHndl_t accessOCBIndirectChannel(accessOCBIndirectCmd i_cmd, { TRACFCOMP( g_fapiImpTd, ERR_MRK"accessOCBIndirectChannel:" " Error [0x%X] in call to" - " FAPI_INVOKE_HWP(p8_ocb_indir_access)", + " FAPI_INVOKE_HWP(p9_pm_ocb_indir_access)", l_errl->reasonCode()); break; // return with error } - } while (0); diff --git a/src/usr/isteps/pm/occCheckstop.C b/src/usr/isteps/pm/occCheckstop.C index d63eb969e..62d1ad8f8 100644 --- a/src/usr/isteps/pm/occCheckstop.C +++ b/src/usr/isteps/pm/occCheckstop.C @@ -27,6 +27,7 @@ #include #include +#include #include #include @@ -52,6 +53,11 @@ #include #include +#include + +#include +#include +#include #ifdef CONFIG_ENABLE_CHECKSTOP_ANALYSIS #include @@ -62,90 +68,45 @@ #define TRACUCOMP(args...) extern trace_desc_t* g_fapiTd; +extern trace_desc_t* g_fapiImpTd; using namespace TARGETING; namespace HBOCC { -// @todo RTC 155065 IPL Time Checkstop Analysis Enablement + #ifdef CONFIG_IPLTIME_CHECKSTOP_ANALYSIS - errlHndl_t loadOCCImageDuringIpl( TARGETING::Target* i_target, - void* i_occVirtAddr) + errlHndl_t loadOCCImageDuringIpl(TARGETING::Target* i_target, + void* i_occVirtAddr) { - TRACUCOMP( g_fapiTd, - ENTER_MRK"loadOCCImageDuringIpl(%p)", - i_occVirtAddr); + TRACUCOMP(g_fapiTd, + ENTER_MRK"loadOCCImageDuringIpl(%p)", + i_occVirtAddr); errlHndl_t l_errl = NULL; - size_t lidSize = 0; - void* l_occImage = NULL; + uint8_t* l_occImage = NULL; + void* l_modifiedSectionPtr = NULL; do { + //The OCC image should always be in the virtual address space UtilLidMgr lidMgr(HBOCC::OCC_LIDID); - - // Get the size of the OCC lid - l_errl = lidMgr.getLidSize(lidSize); - if(l_errl) - { - TRACFCOMP( g_fapiImpTd, - ERR_MRK"loadOCCImageDuringIpl: " - "Error getting lid size. lidId=0x%.8x", - OCC_LIDID); - break; - } - - // Check if lid is in virtual address space to save on allocating - // a large local buffer to copy data to. - bool l_lidInVirtMem = false; - // Try to use virtual address space for accessing the lid - l_occImage = const_cast(lidMgr.getLidVirtAddr()); - // Get lid from non virtual address space. - if( l_occImage == NULL ) - { - // allocate memory big enough for all OCC - l_occImage = reinterpret_cast(malloc(1*MEGABYTE)); - - // Ensure occ lid size is less than memory allocated for it - assert(lidSize <= 1*MEGABYTE); - - // Get the entire OCC lid and write it into temporary memory - l_errl = lidMgr.getLid(l_occImage, lidSize); - if(l_errl) - { - TRACFCOMP( g_fapiImpTd, - ERR_MRK"loadOCCImageDuringIpl: " - "Error getting lid. lidId=0x%.8x", - OCC_LIDID); - break; - } - } - else - { - l_lidInVirtMem = true; - } - - // Pointer to OCC LID - char *l_occLid = reinterpret_cast(l_occImage); + void* l_tmpOccImage = const_cast(lidMgr.getLidVirtAddr()); + l_occImage = (uint8_t*)l_tmpOccImage; // Get system target in order to access ATTR_NEST_FREQ_MHZ - TARGETING::TargetService & tS = TARGETING::targetService(); - TARGETING::Target * sysTarget = NULL; - tS.getTopLevelTarget( sysTarget ); - assert( sysTarget != NULL ); - - // Save Nest Frequency; - ATTR_NEST_FREQ_MHZ_type l_nestFreq = - sysTarget->getAttr(); - - size_t l_length = 0; // length of this section - size_t l_startOffset = 0; // offset to start of the section + TARGETING::TargetService & l_tS = TARGETING::targetService(); + TARGETING::Target * l_sysTarget = NULL; + l_tS.getTopLevelTarget(l_sysTarget); + assert(l_sysTarget != NULL); - // offset to length of the section - size_t l_offsetToLength = OCC_OFFSET_LENGTH; + //Save Nest Frequency: + ATTR_FREQ_PB_MHZ_type l_nestFreq = + l_sysTarget->getAttr(); + size_t l_length = 0; // length of current section - // Get length of OCC bootloader - uint32_t *ptrToLength = (uint32_t *)(l_occLid + l_offsetToLength); - l_length = *ptrToLength; + uint32_t* l_ptrToLength = (uint32_t*) + ((char*)l_occImage + OCC_OFFSET_LENGTH); + l_length = *l_ptrToLength; // Length of the bootloader // We only have PAGESIZE to work with so make sure we do not exceed // limit. @@ -154,158 +115,96 @@ namespace HBOCC memcpy(i_occVirtAddr, l_occImage, l_length); // OCC Main Application - l_startOffset = l_length; // after the Boot image - char * l_occMainAppPtr = reinterpret_cast(l_occLid) + - l_startOffset; - - // Get the length of the OCC Main application - ptrToLength = (uint32_t *)(l_occMainAppPtr + l_offsetToLength); - l_length = *ptrToLength; - size_t l_occMainLength = l_length; - - // If LID is in vaddr space we do not want to modify directly. - if (l_lidInVirtMem) + char* l_occMainAppPtr = reinterpret_cast(l_occImage) + + l_length; + l_ptrToLength = (uint32_t*)(l_occMainAppPtr + OCC_OFFSET_LENGTH); + l_length = *l_ptrToLength; // Length of the OCC Main + + // Write 405 Main application to SRAM + l_errl = HBOCC::writeSRAM(i_target, + HBOCC::OCC_405_SRAM_ADDRESS, + (uint64_t*)l_occMainAppPtr, + l_length); + if(l_errl) { - // Allocate memory for size of modified section. - // [ipl flag and freq] - l_length = OCC_OFFSET_FREQ + sizeof(ATTR_NEST_FREQ_MHZ_type); - l_occImage = reinterpret_cast(malloc(l_length)); - // Fill in modify buffer from pnor vaddr. - memcpy(l_occImage, l_occMainAppPtr, l_length); - // Move occ main app pointer - l_occMainAppPtr = reinterpret_cast(l_occImage); + TRACFCOMP(g_fapiImpTd, "loadOCCImageDuringIpl:" + " failed to write Main app to SRAM"); + break; } - // write the IPL flag and the nest freq into OCC main app. - // IPL_FLAG is a two byte field. OR a 1 into these two bytes. - // FREQ is the 4 byte nest frequency value that goes into - // the same field in the HOMER. - - uint16_t *ptrToIplFlag = - (uint16_t *)((char *)l_occMainAppPtr + OCC_OFFSET_IPL_FLAG); - - uint32_t *ptrToFreq = - (uint32_t *)((char *)l_occMainAppPtr + OCC_OFFSET_FREQ); - - *ptrToIplFlag |= 0x0001; - *ptrToFreq = l_nestFreq; - - // Store the OCC Main applicatoin into ecmdDataBuffer - // so we may write it to SRAM - TRACDCOMP( g_fapiImpTd, "loadOCCImageDuringIpl: " - "ecmdDataBufferBase size = 0x%X", - l_occMainLength); - - ecmdDataBufferBase l_occAppData(l_occMainLength * 8 /* bits */); - assert(l_length < l_occMainLength, - "Cannot write more OCC data than the ECMD buffer " - "has rooom for. write size = 0x%X, ECMD buffer size = 0x%X", - l_length, l_occMainLength); - uint32_t rc = l_occAppData.insert( - reinterpret_cast(l_occMainAppPtr), - 0, - l_length * 8 /* bits */); - if (rc) + l_modifiedSectionPtr = malloc(OCC_OFFSET_FREQ + sizeof(l_nestFreq)); + // Populate this section with data from PNOR + memcpy(l_modifiedSectionPtr, l_occMainAppPtr, OCC_OFFSET_FREQ + + sizeof(l_nestFreq)); + + // Change the fequency and set the IPL flag + uint16_t* l_ptrToIplFlag = (uint16_t*)((char*)l_modifiedSectionPtr + + OCC_OFFSET_IPL_FLAG); + uint32_t* l_ptrToFreq = (uint32_t*)((char*)l_modifiedSectionPtr + + OCC_OFFSET_FREQ); + + *l_ptrToIplFlag |= 0x001; + *l_ptrToFreq = l_nestFreq; + + // Overwrite the part of Main we modified above in SRAM: + l_errl = HBOCC::writeSRAM(i_target, + HBOCC::OCC_405_SRAM_ADDRESS, + (uint64_t*)l_modifiedSectionPtr, + (uint32_t)OCC_OFFSET_FREQ + + sizeof(l_nestFreq)); + if(l_errl) { TRACFCOMP( g_fapiImpTd, ERR_MRK"loadOCCImageDuringIpl: " - "Error %d doing insert, write size = 0x%X, " - "ECMD buffer size = 0x%X", - rc, l_length, l_occMainLength); - /*@ - * @errortype - * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE - * @moduleid fapi::MOD_LOAD_OCC_IMAGE_DURING_IPL - * @reasoncode fapi::RC_ECMD_INSERT_FAILED - * @userdata1 Return Code - * @userdata2 Data size to insert - * @devdesc ecmd insert failed for l_occAppData - * @custdesc A problem occurred during the IPL - * of the system. - */ - l_errl = new ERRORLOG::ErrlEntry( - ERRORLOG::ERRL_SEV_UNRECOVERABLE, - fapi::MOD_LOAD_OCC_IMAGE_DURING_IPL, - fapi::RC_ECMD_INSERT_FAILED, - rc, - l_length, - true); - l_errl->collectTrace(FAPI_TRACE_NAME,256); - l_errl->collectTrace(FAPI_IMP_TRACE_NAME,256); + "Failed to overwrite OCC Main app in SRAM"); break; } - // If the lid is in vaddr space we only wrote the modify length to - // ECMD buffer. Now need to write the rest here. - if(l_lidInVirtMem) + // GPE0 application is stored right after the 405 main in memory + char* l_gpe0AppPtr = l_occMainAppPtr + l_length; + uint32_t* l_ptrToGpe0Length = + (uint32_t*)(l_occMainAppPtr + OCC_OFFSET_GPE0_LENGTH); + l_length = *l_ptrToGpe0Length; + l_errl = HBOCC::writeSRAM(i_target, + HBOCC::OCC_GPE0_SRAM_ADDRESS, + (uint64_t*)l_gpe0AppPtr, + l_length); + if(l_errl) { - size_t l_remainingSize = (l_occMainLength - l_length); - // Move occ main pointer back to PNOR vaddr + modified length - l_occMainAppPtr = reinterpret_cast(l_occLid) + - l_startOffset + l_length; - - // Write to rest of OCC Main to buffer. This means Main app size - // minus the modified size. - rc = l_occAppData.insert( - reinterpret_cast(l_occMainAppPtr), - l_length * 8 /* bits */, - l_remainingSize * 8 /* bits */); - if (rc) - { - TRACFCOMP( g_fapiImpTd, - ERR_MRK"loadOCCImageDuringIpl: " - "Error %d doing insert of remaining data, " - "write size = 0x%X, ECMD buffer size = 0x%X", - rc, - l_remainingSize, - l_occMainLength); - /*@ - * @errortype - * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE - * @moduleid fapi::MOD_LOAD_OCC_IMAGE_DURING_IPL - * @reasoncode fapi::RC_ECMD_INSERT_REMAINING_FAILED - * @userdata1 Return Code - * @userdata2 Remaining data size to insert - * @devdesc ecmd insert failed for l_occAppData - * @custdesc A problem occurred during the IPL - * of the system. - */ - l_errl = new ERRORLOG::ErrlEntry( - ERRORLOG::ERRL_SEV_UNRECOVERABLE, - fapi::MOD_LOAD_OCC_IMAGE_DURING_IPL, - fapi::RC_ECMD_INSERT_REMAINING_FAILED, - rc, - l_remainingSize, - true); - l_errl->collectTrace(FAPI_TRACE_NAME,256); - l_errl->collectTrace(FAPI_IMP_TRACE_NAME,256); - break; - } + TRACFCOMP( g_fapiImpTd, + ERR_MRK"loadOCCImageDuringIpl: " + "Failed to load GPE0 app to SRAM"); + break; } - // Write the OCC Main app into SRAM - const uint32_t l_SramAddrApp = OCC_SRAM_ADDRESS; - l_errl = HBOCC::writeSRAM(i_target, l_SramAddrApp, l_occAppData); + char* l_gpe1AppPtr = l_gpe0AppPtr + l_length; + uint32_t* l_ptrToGpe1Length = + (uint32_t*)(l_occMainAppPtr + OCC_OFFSET_GPE1_LENGTH); + l_length = *l_ptrToGpe1Length; + l_errl = HBOCC::writeSRAM(i_target, + HBOCC::OCC_GPE1_SRAM_ADDRESS, + (uint64_t*)l_gpe1AppPtr, + l_length); if(l_errl) { TRACFCOMP( g_fapiImpTd, ERR_MRK"loadOCCImageDuringIpl: " - "Error in writeSRAM of app"); + "Failed to load GPE1 app to SRAM"); break; } - }while(0); - //free memory used for OCC lid - free(l_occImage); + } while(0); + free(l_modifiedSectionPtr); - TRACUCOMP( g_fapiTd, + TRACUCOMP(g_fapiTd, EXIT_MRK"loadOCCImageDuringIpl"); return l_errl; } + + #endif -// @todo RTC 155065 IPL Time Checkstop Analysis Enablement #if defined(CONFIG_IPLTIME_CHECKSTOP_ANALYSIS) && !defined(__HOSTBOOT_RUNTIME) /** * @brief Sets up OCC Host data in SRAM @@ -313,15 +212,14 @@ namespace HBOCC errlHndl_t loadHostDataToSRAM( TARGETING::Target* i_proc, const PRDF::HwInitialized_t i_curHw) { - TRACUCOMP( g_fapiTd, - ENTER_MRK"loadHostDataToSRAM i_curHw=%d",i_curHw); + TRACUCOMP(g_fapiTd, ENTER_MRK"loadHostDataToSRAM i_curHw=%d",i_curHw); errlHndl_t l_errl = NULL; //Treat virtual address as starting pointer //for config struct - HBOCC::occHostConfigDataArea_t * config_data = - new HBOCC::occHostConfigDataArea_t(); + HBPM::occHostConfigDataArea_t * config_data = + new HBPM::occHostConfigDataArea_t(); // Get top level system target TARGETING::TargetService & tS = TARGETING::targetService(); @@ -331,8 +229,6 @@ namespace HBOCC uint32_t nestFreq = sysTarget->getAttr(); - - config_data->version = HBOCC::OccHostDataVersion; config_data->nestFrequency = nestFreq; @@ -357,47 +253,17 @@ namespace HBOCC } else { - const uint32_t l_SramAddrFir = OCC_SRAM_FIR_DATA; - ecmdDataBufferBase l_occFirData(OCC_SRAM_FIR_LENGTH * 8 /* bits */); - /// copy config_data in here - uint32_t rc = l_occFirData.insert( - (uint32_t *)config_data->firdataConfig, - 0, - sizeof(config_data->firdataConfig) * 8 /* bits */); - if (rc) + l_errl = HBOCC::writeSRAM(i_proc, OCC_SRAM_FIR_DATA, + (uint64_t*)config_data->firdataConfig, + sizeof(config_data->firdataConfig)); + if(l_errl) { TRACFCOMP( g_fapiImpTd, - ERR_MRK"loadHostDataToSRAM: Error %d doing insert", - rc); - /*@ - * @errortype - * @moduleid fapi::MOD_OCC_LOAD_HOST_DATA_TO_SRAM - * @reasoncode fapi::RC_ECMD_INSERT_FAILED - * @userdata1 Return Code - * @userdata2 0 - * @devdesc ecmd insert failed for l_occFirData - * @custdesc A problem occurred during the IPL - * of the system. - */ - l_errl = new ERRORLOG::ErrlEntry( - ERRORLOG::ERRL_SEV_UNRECOVERABLE, - fapi::MOD_OCC_LOAD_HOST_DATA_TO_SRAM, - fapi::RC_ECMD_INSERT_FAILED, - rc, 0); - } - else - { - l_errl = HBOCC::writeSRAM(i_proc, l_SramAddrFir, l_occFirData); - if(l_errl) - { - TRACFCOMP( g_fapiImpTd, - ERR_MRK"loadHostDataToSRAM: Error in writeSRAM"); - } + ERR_MRK"loadHostDataToSRAM: Error in writeSRAM"); } } - - TRACUCOMP( g_fapiTd, - EXIT_MRK"loadHostDataToSRAM"); + TRACUCOMP( g_fapiTd, EXIT_MRK"loadHostDataToSRAM"); + delete(config_data); return l_errl; } // loadHostDataToSRAM diff --git a/src/usr/isteps/pm/pm.mk b/src/usr/isteps/pm/pm.mk index 4e9f9dc67..b5f107821 100644 --- a/src/usr/isteps/pm/pm.mk +++ b/src/usr/isteps/pm/pm.mk @@ -52,10 +52,14 @@ EXTRAINCDIR += ${NEST_UTIL_PATH} ## NOTE: add the base istep dir here. EXTRAINCDIR += ${ROOTPATH}/src/usr/isteps/ +EXTRAINCDIR += ${ROOTPATH}/src/usr/pnor/ +EXTRAINCDIR += ${ROOTPATH}/src/include/usr/pnor/ +EXTRAINCDIR += ${ROOTPATH}/src/include/usr/util/ #common PM Complex functions between ipl and runtime OBJS += pm_common.o OBJS += occAccess.o +OBJS += occCheckstop.o ## NOTE: add a new directory onto the vpaths when you add a new HWP VPATH += ${HWP_PM_PATH} ${HWP_CUST_PATH} ${HWP_ACC_PATH} diff --git a/src/usr/isteps/pm/pm_common.C b/src/usr/isteps/pm/pm_common.C index e4d48217e..caaa717b6 100644 --- a/src/usr/isteps/pm/pm_common.C +++ b/src/usr/isteps/pm/pm_common.C @@ -71,6 +71,8 @@ #include #include +#include + #ifdef CONFIG_ENABLE_CHECKSTOP_ANALYSIS #include #endif @@ -98,6 +100,7 @@ namespace HBPM { constexpr uint32_t OCC_SRAM_RSP_ADDR = 0xFFFBF000; constexpr uint16_t OCC_CHKPT_COMPLETE = 0x0EFF; + const uint32_t IPL_FLAG_AND_FREQ_SIZE = sizeof(uint32_t) + sizeof(uint16_t); std::shared_ptr g_pOccLidMgr (nullptr); @@ -192,7 +195,6 @@ namespace HBPM } #ifdef CONFIG_ENABLE_CHECKSTOP_ANALYSIS -// @todo RTC 155065 IPL Time Checkstop Analysis Enablement // Figure out the FIR master TARGETING::Target* masterproc = nullptr; tS.masterProcChipTargetHandle( masterproc ); @@ -615,7 +617,8 @@ namespace HBPM errlHndl_t loadPMComplex(TARGETING::Target * i_target, uint64_t i_homerPhysAddr, uint64_t i_commonPhysAddr, - loadPmMode i_mode) + loadPmMode i_mode, + bool i_useSRAM) { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, ENTER_MRK"loadPMComplex: %s", @@ -626,7 +629,7 @@ namespace HBPM do { // Reset the PM complex for LOAD only - if( PM_LOAD == i_mode) + if(PM_LOAD == i_mode) { l_errl = resetPMComplex(i_target); if( l_errl ) @@ -650,7 +653,7 @@ namespace HBPM } // Zero out the HOMER memory for LOAD only - if(PM_LOAD == i_mode) + if(PM_LOAD == i_mode && !i_useSRAM) { memset(l_homerVAddr, 0, VMM_HOMER_INSTANCE_SIZE); } @@ -659,7 +662,6 @@ namespace HBPM + HOMER_OFFSET_TO_OCC_IMG; uint64_t l_occImgVaddr = reinterpret_cast (l_homerVAddr) + HOMER_OFFSET_TO_OCC_IMG; - l_errl = loadOCCSetup(i_target, l_occImgPaddr, l_occImgVaddr, @@ -675,96 +677,110 @@ namespace HBPM l_occImgVaddr, i_commonPhysAddr ); break; } - -#if 0 // @todo RTC 155065 IPL Time Checkstop Analysis Enablement #ifdef CONFIG_IPLTIME_CHECKSTOP_ANALYSIS - if (i_useSRAM) + if(i_useSRAM) { - void* occVirt = reinterpret_cast(i_occImgVaddr); - l_errl = loadOCCImageDuringIpl( i_target, occVirt ); - if( l_errl ) + void* l_occVirt = reinterpret_cast(l_occImgVaddr); + l_errl = HBOCC::loadOCCImageDuringIpl(i_target, l_occVirt); + if(l_errl) { TRACFCOMP(g_fapiImpTd, - ERR_MRK"loadOCC: loadOCCImageDuringIpl failed!"); + ERR_MRK"loadPMComplex:" + " loadOCCImageDuringIpl failed!"); break; } } else +#endif { - // clear (up to and including) the IPL Flag - const uint32_t l_SramAddrApp = OCC_SRAM_ADDRESS; - ecmdDataBufferBase - l_occAppData((OCC_OFFSET_IPL_FLAG + 6) * 8 /* bits */); - l_errl = HBOCC::writeSRAM(i_target,l_SramAddrApp,l_occAppData); +#ifdef CONFIG_IPLTIME_CHECKSTOP_ANALYSIS + //If we're in Checkstop analysis and get here, we need + //to clear the IPL flag that got set during istep 6 + const uint32_t l_sramAddrApp = HBOCC::OCC_405_SRAM_ADDRESS; + uint8_t l_occAppData[HBOCC::OCC_OFFSET_IPL_FLAG + + IPL_FLAG_AND_FREQ_SIZE]; + memset(l_occAppData, 0, HBOCC::OCC_OFFSET_IPL_FLAG + + IPL_FLAG_AND_FREQ_SIZE); + l_errl = HBOCC::writeSRAM(i_target, l_sramAddrApp, + (uint64_t*) l_occAppData, HBOCC::OCC_OFFSET_IPL_FLAG + + IPL_FLAG_AND_FREQ_SIZE); if(l_errl) { - TRACFCOMP( g_fapiImpTd, - ERR_MRK"loadOCC: Error in writeSRAM of 0"); + TRACFCOMP(g_fapiImpTd, + "loadPMComplex: Error erasing IPL flag"); break; } - } -#endif #endif - l_errl = loadOCCImageToHomer(i_target, - l_occImgPaddr, - l_occImgVaddr, - i_mode); - if(l_errl) - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - ERR_MRK"loadPMComplex: " - "loading OCC failed! " - "HUID=0x%08X OCC_Phys=0x%0lX " - "OCC_Virt=0x%0lX Mode=%s", - get_huid(i_target), l_occImgPaddr, l_occImgVaddr, - (PM_LOAD == i_mode) ? "LOAD" : "RELOAD" ); - break; + l_errl = loadOCCImageToHomer(i_target, + l_occImgPaddr, + l_occImgVaddr, + i_mode); + if(l_errl) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + ERR_MRK"loadPMComplex: " + "loading OCC failed! " + "HUID=0x%08X OCC_Phys=0x%0lX " + "OCC_Virt=0x%0lX Mode=%s", + get_huid(i_target), l_occImgPaddr, l_occImgVaddr, + (PM_LOAD == i_mode) ? "LOAD" : "RELOAD" ); + break; + } } - - void* l_occDataVaddr = reinterpret_cast (l_occImgVaddr + - HOMER_OFFSET_TO_OCC_HOST_DATA); - -#if 0 // @todo RTC 155065 IPL Time Checkstop Analysis Enablement #if defined(CONFIG_IPLTIME_CHECKSTOP_ANALYSIS) && !defined(__HOSTBOOT_RUNTIME) - if (i_useSRAM) + if(i_useSRAM) { //============================== //Setup host data area in SRAM //============================== l_errl = HBOCC::loadHostDataToSRAM(i_target, - PRDF::MASTER_PROC_CORE); + PRDF::MASTER_PROC_CORE); if( l_errl != NULL ) { - TRACFCOMP( g_fapiImpTd, ERR_MRK"loading Host Data Area failed!" ); + TRACFCOMP(g_fapiImpTd, + ERR_MRK"loading Host Data Area failed!"); break; } } + else #endif -#endif - l_errl = loadHostDataToHomer(i_target, - l_occDataVaddr); - if(l_errl) { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - ERR_MRK"loadPMComplex: " - "loading Host Data Area failed! " - "HUID=0x%08X OCC_Host_Data_Virt=0x%0lX", - get_huid(i_target), l_occDataVaddr ); - break; + void* l_occDataVaddr = reinterpret_cast (l_occImgVaddr + + HOMER_OFFSET_TO_OCC_HOST_DATA); + + l_errl = loadHostDataToHomer(i_target, + l_occDataVaddr); + if(l_errl) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + ERR_MRK"loadPMComplex: " + "loading Host Data Area failed! " + "HUID=0x%08X OCC_Host_Data_Virt=0x%0lX", + get_huid(i_target), l_occDataVaddr ); + break; + } + + l_errl = loadHcode(i_target, + l_homerVAddr, + i_mode); + if(l_errl) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + ERR_MRK"loadPMComplex: " + "loadHcode failed! " + "HUID=0x%08X HOMER_Virt=0x%0lX Mode=%s", + get_huid(i_target), l_occImgVaddr, + (PM_LOAD == i_mode) ? "LOAD" : "RELOAD" ); + break; + } } - l_errl = loadHcode(i_target, - l_homerVAddr, - i_mode); - if(l_errl) + //If i_useSRAM is true, then we're in istep 6.11. This address needs + //to be reset here, so that it's recalculated again in istep 21.1 + //where this function is called. + if(i_useSRAM) { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - ERR_MRK"loadPMComplex: " - "loadHcode failed! " - "HUID=0x%08X HOMER_Virt=0x%0lX Mode=%s", - get_huid(i_target), l_occImgVaddr, - (PM_LOAD == i_mode) ? "LOAD" : "RELOAD" ); - break; + i_target->setAttr(0); } } while(0); diff --git a/src/usr/isteps/pm/pm_common.H b/src/usr/isteps/pm/pm_common.H index 35a72d0ce..eafbdb983 100644 --- a/src/usr/isteps/pm/pm_common.H +++ b/src/usr/isteps/pm/pm_common.H @@ -126,13 +126,15 @@ namespace HBPM * RELOAD == i_mode * - Reload OCC lid, rewrite OCC config data, build Pstate * Parameter Blocks, and rebuild Hcode + * @param[in] i_useSRAM: Use SRAM to write data (default: false) * * @return errlHndl_t Error log if loadPMComplex failed */ errlHndl_t loadPMComplex(TARGETING::Target * i_target, uint64_t i_homerPhysAddr, uint64_t i_commonPhysAddr, - loadPmMode i_mode); + loadPmMode i_mode, + bool i_useSRAM = false); /** * @brief Start PM Complex. -- cgit v1.2.1