From 47845536df2e76c019b1289fd72d443498b9c102 Mon Sep 17 00:00:00 2001 From: LiuYangFan Date: Fri, 1 Apr 2016 03:25:41 -0500 Subject: Update RAM procedures. Changes included: p9_ram_core: 1. Add special case support for get/put NIA/MSR/CR/FPSCR 2. Add thread stop state check in setup 3. Add error handling when ram_setup/get_reg/put_reg p9_ram_get_all_reg/p9_ram_put_all_reg: Add get/put all registers function for test p9_ram_spr_test: New file to test SPR, verify with SPY read, for Cronus use p9_ram_after_checkstop: New file to test ram after checkstop p9_ram_addr_error_test: New file to test ram after bad address access p9_ram_wrap: Update to support the new tests Change-Id: Ia4da55eae26e9f3a667446bc984b358c064fdd8a Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22746 Reviewed-by: Joseph J. McGill Tested-by: Jenkins Server Reviewed-by: Thi N. Tran Tested-by: PPE CI Reviewed-by: PARVATHI RACHAKONDA Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27696 Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell --- .../chips/p9/procedures/hwp/perv/p9_ram_core.C | 647 ++++++++++++++++----- .../chips/p9/procedures/hwp/perv/p9_ram_core.H | 14 +- .../chips/p9/procedures/hwp/perv/p9_ram_getreg.H | 11 +- .../chips/p9/procedures/hwp/perv/p9_ram_getspr.C | 19 +- .../chips/p9/procedures/hwp/perv/p9_ram_getspr.H | 9 +- .../chips/p9/procedures/hwp/perv/p9_ram_putreg.H | 11 +- .../chips/p9/procedures/hwp/perv/p9_ram_putspr.C | 19 +- .../chips/p9/procedures/hwp/perv/p9_ram_putspr.H | 2 +- .../chips/p9/procedures/hwp/perv/p9_spr_name_map.C | 92 ++- .../chips/p9/procedures/hwp/perv/p9_spr_name_map.H | 361 +++++++----- .../p9/procedures/xml/error_info/p9_ram_errors.xml | 17 +- 11 files changed, 838 insertions(+), 364 deletions(-) (limited to 'src') diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.C b/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.C index 6553c03f8..b31b73ef2 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.C @@ -24,7 +24,7 @@ //----------------------------------------------------------------------------------- // *HWP HWP Owner : Liu Yang Fan // *HWP HWP Backup Owner : Gou Peng Fei -// *HWP FW Owner : Sachin Gupta +// *HWP FW Owner : Thi Tran // *HWP Team : Perv // *HWP Level : 2 // *HWP Consumed by : SBE @@ -35,19 +35,66 @@ #include "p9_quad_scom_addresses.H" #include "p9_quad_scom_addresses_fld.H" +// identifiers for special registers +const uint32_t RAM_REG_NIA = 2000; +const uint32_t RAM_REG_MSR = 2001; +const uint32_t RAM_REG_CR = 2002; +const uint32_t RAM_REG_FPSCR = 2003; + // opcode for ramming -const uint32_t OPCODE_MTSPR_FROM_GPR0_TO_SPRD = 0x7C1543A6; -const uint32_t OPCODE_MTSPR_FROM_GPR1_TO_SPRD = 0x7C3543A6; -const uint32_t OPCODE_MFSPR_FROM_SPRD_TO_GPR0 = 0x7C1542A6; -const uint32_t OPCODE_MFSPR_FROM_SPRD_TO_GPR1 = 0x7C3542A6; -const uint32_t OPCODE_MFSPR_FROM_SPR0_TO_GPR0 = 0x7C0002A6; -const uint32_t OPCODE_MTSPR_FROM_GPR0_TO_SPR0 = 0x7C0003A6; -const uint32_t OPCODE_MFFPRD_FROM_FPR0_TO_GPR0 = 0x7C000066; -const uint32_t OPCODE_MTFPRD_FROM_GPR0_TO_FPR0 = 0x7C000166; -const uint32_t OPCODE_MFVSRD_FROM_VSR0_TO_GPR0 = 0x7C000067; -const uint32_t OPCODE_MTVSRD_FROM_GPR0_TO_VSR0 = 0x7C000167; -const uint32_t OPCODE_MFVSRLD_FROM_VSR0_TO_GPR0 = 0x7C000267; -const uint32_t OPCODE_MTVSRDD_FROM_GPR1_0_TO_VSR0 = 0x7C010367; +const uint32_t OPCODE_MTSPR_FROM_GPR0_TO_SPRD = 0x7C1543A6; +const uint32_t OPCODE_MTSPR_FROM_GPR1_TO_SPRD = 0x7C3543A6; +const uint32_t OPCODE_MFSPR_FROM_SPRD_TO_GPR0 = 0x7C1542A6; +const uint32_t OPCODE_MFSPR_FROM_SPRD_TO_GPR1 = 0x7C3542A6; +const uint32_t OPCODE_MFSPR_FROM_SPR0_TO_GPR0 = 0x7C0002A6; +const uint32_t OPCODE_MTSPR_FROM_GPR0_TO_SPR0 = 0x7C0003A6; +const uint32_t OPCODE_MFFPRD_FROM_FPR0_TO_GPR0 = 0x7C000066; +const uint32_t OPCODE_MTFPRD_FROM_GPR0_TO_FPR0 = 0x7C000166; +const uint32_t OPCODE_MFVSRD_FROM_VSR0_TO_GPR0 = 0x7C000066; +const uint32_t OPCODE_MFVSRD_FROM_VSR32_TO_GPR0 = 0x7C000067; +const uint32_t OPCODE_MFVSRLD_FROM_VSR0_TO_GPR0 = 0x7C000266; +const uint32_t OPCODE_MFVSRLD_FROM_VSR32_TO_GPR0 = 0x7C000267; +const uint32_t OPCODE_MTVSRDD_FROM_GPR1_0_TO_VSR0 = 0x7C010366; +const uint32_t OPCODE_MTVSRDD_FROM_GPR1_0_TO_VSR32 = 0x7C010367; +const uint32_t OPCODE_MFSPR_FROM_LR_TO_GPR0 = 0x7C0802A6; +const uint32_t OPCODE_MTSPR_FROM_GPR0_TO_LR = 0x7C0803A6; +const uint32_t OPCODE_MTMSR_L0 = 0x7C000124; +const uint32_t OPCODE_MTMSRD_L0 = 0x7C000164; +const uint32_t OPCODE_MTSPR_IAMR = 0x7C1D0BA6; +const uint32_t OPCODE_MTSPR_PIDR = 0x7C100BA6; +const uint32_t OPCODE_MTSPR_LPIDR = 0x7C1F4BA6; +const uint32_t OPCODE_MTSPR_LPCR = 0x7C1E4BA6; +const uint32_t OPCODE_MTSPR_MMCRA = 0x7C12C3A6; +const uint32_t OPCODE_MTSPR_MMCR1 = 0x7C1EC3A6; +const uint32_t OPCODE_MTSPR_SEIDBAR = 0x7C1F7BA6; +const uint32_t OPCODE_MTSPR_XER = 0x7C0103A6; +const uint32_t OPCODE_MFSPR_XER = 0x7C0102A6; +const uint32_t OPCODE_MFFS = 0xFC00048E; +const uint32_t OPCODE_SLBMFEE = 0x7C000726; +const uint32_t OPCODE_SLBMFEV = 0x7C0006A6; +const uint32_t OPCODE_DCBZ = 0x7C0007EC; +const uint32_t OPCODE_DCBF = 0x7C0000AC; +const uint32_t OPCODE_LD = 0xE8000000; +const uint32_t OPCODE_STD = 0xF8000000; +const uint32_t OPCODE_LFD = 0xC8000000; +const uint32_t OPCODE_STFD = 0xD8000000; +const uint32_t OPCODE_LVX = 0x7C0000CE; +const uint32_t OPCODE_STVX = 0x7C0001CE; +const uint32_t OPCODE_LXVD2X = 0x7C000698; +const uint32_t OPCODE_STXVD2X = 0x7C000798; +const uint32_t OPCODE_MFMSR_TO_GPR0 = 0x7C0000A6; +const uint32_t OPCODE_MFCR_TO_GPR0 = 0x7C000026; +const uint32_t OPCODE_MTCRF_FROM_GPR0 = 0x7C0FF120; +const uint32_t OPCODE_MTFSF_FROM_GPR0 = 0xFE00058E; + +// TODO: make sure these special PPC are final version in PC workbook table 9-2 +const uint32_t OPCODE_MFNIA_RT = 0x001ac804; +const uint32_t OPCODE_MTNIA_LR = 0x4c1e00a4; +const uint32_t OPCODE_GPR_MOVE = 0x00000010; +const uint32_t OPCODE_VSR_MOVE_HI = 0x00000110; +const uint32_t OPCODE_VSR_MOVE_LO = 0x00000210; +const uint32_t OPCODE_XER_MOVE = 0x00000310; +const uint32_t OPCODE_CR_MOVE = 0x00000410; // poll count for check ram status const uint32_t RAM_CORE_STAT_POLL_CNT = 10; @@ -55,6 +102,7 @@ const uint32_t RAM_CORE_STAT_POLL_CNT = 10; // Scom register field // TODO: replace the const with FLD macro define when it's ready const uint32_t C_RAM_MODEREG_ENABLE = 0; +const uint32_t C_RAS_STATUS_CORE_MAINT = 0; const uint32_t C_THREAD_INFO_VTID0_ACTIVE = 0; const uint32_t C_RAM_CTRL_VTID = 0; const uint32_t C_RAM_CTRL_VTID_LEN = 2; @@ -74,13 +122,15 @@ RamCore::RamCore(const fapi2::Target& i_target, const u { iv_target = i_target; iv_thread = i_thread; - iv_ram_enable = false; - iv_ram_setup = false; - iv_write_gpr0 = false; - iv_write_gpr1 = false; - iv_backup_buf0 = 0; - iv_backup_buf1 = 0; - iv_backup_buf2 = 0; + iv_ram_enable = false; + iv_ram_scr0_save = false; + iv_ram_setup = false; + iv_ram_err = false; + iv_write_gpr0 = false; + iv_write_gpr1 = false; + iv_backup_buf0 = 0; + iv_backup_buf1 = 0; + iv_backup_buf2 = 0; } RamCore::~RamCore() @@ -94,16 +144,28 @@ RamCore::~RamCore() //----------------------------------------------------------------------------------- fapi2::ReturnCode RamCore::ram_setup() { - FAPI_INF("Start ram setup"); + FAPI_DBG("Start ram setup"); fapi2::buffer l_data = 0; uint32_t l_opcode = 0; bool l_thread_active = false; + uint8_t l_thread_stop = 0; // set RAM_MODEREG Scom to enable RAM mode FAPI_TRY(fapi2::getScom(iv_target, C_RAM_MODEREG, l_data)); l_data.setBit(); FAPI_TRY(fapi2::putScom(iv_target, C_RAM_MODEREG, l_data)); + // read RAS_STATUS Scom to check the thread is stopped for ramming + l_data.flush<0>(); + FAPI_TRY(fapi2::getScom(iv_target, C_RAS_STATUS, l_data)); + FAPI_DBG("RAS_STATUS:%#lx", l_data()); + FAPI_TRY(l_data.extractToRight(l_thread_stop, C_RAS_STATUS_CORE_MAINT + 8 * iv_thread, 2)); + + FAPI_ASSERT(l_thread_stop == 3, + fapi2::P9_RAM_THREAD_NOT_STOP_ERR() + .set_THREAD(iv_thread), + "Thread to perform ram is not stopped"); + // read THREAD_INFO Scom to check the thread is active for ramming l_data.flush<0>(); FAPI_TRY(fapi2::getScom(iv_target, C_THREAD_INFO, l_data)); @@ -117,9 +179,10 @@ fapi2::ReturnCode RamCore::ram_setup() iv_ram_enable = true; - // backup registers SCR0/GPR0/GPR1 + // backup registers SCR0/GPR0/GPR1/LR //SCR0->iv_backup_buf0 FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, iv_backup_buf0)); + iv_ram_scr0_save = true; //GPR0->iv_backup_buf1 //1.setup SPRC to use SCRO as SPRD @@ -150,14 +213,22 @@ fapi2::ReturnCode RamCore::ram_setup() iv_ram_setup = true; fapi_try_exit: - FAPI_INF("Exiting ram setup"); + + // Error happened and SCR0 saved, to restore SCR0 + // Do not use "FAPI_TRY" to avoid endless loop + if((fapi2::current_err != fapi2::FAPI2_RC_SUCCESS) && iv_ram_scr0_save) + { + fapi2::putScom(iv_target, C_SCR0, iv_backup_buf0); + } + + FAPI_DBG("Exiting ram setup"); return fapi2::current_err; } //----------------------------------------------------------------------------------- fapi2::ReturnCode RamCore::ram_cleanup() { - FAPI_INF("Start ram cleanup"); + FAPI_DBG("Start ram cleanup"); uint32_t l_opcode = 0; fapi2::buffer l_data = 0; @@ -165,26 +236,30 @@ fapi2::ReturnCode RamCore::ram_cleanup() fapi2::P9_RAM_NOT_SETUP_ERR(), "Attempting to cleanup ram without setup before"); - // restore GPR1/GPR0/SCR0 - if(!iv_write_gpr0 && !iv_write_gpr1) + // setup SPRC to use SCRO as SPRD + FAPI_TRY(fapi2::getScom(iv_target, C_SPR_MODE, l_data)); + FAPI_TRY(l_data.setBit(C_SPR_MODE_MODEREG_SPRC_LT0_SEL + iv_thread)); + FAPI_TRY(fapi2::putScom(iv_target, C_SPR_MODE, l_data)); + l_data.flush<0>(); + FAPI_TRY(fapi2::getScom(iv_target, C_SCOMC, l_data)); + l_data.insertFromRight(0); + FAPI_TRY(fapi2::putScom(iv_target, C_SCOMC, l_data)); + + // restore GPR1 + if(!iv_write_gpr1) { //iv_backup_buf2->GPR1 - //1.setup SPRC to use SCRO as SPRD - FAPI_TRY(fapi2::getScom(iv_target, C_SPR_MODE, l_data)); - FAPI_TRY(l_data.setBit(C_SPR_MODE_MODEREG_SPRC_LT0_SEL + iv_thread)); - FAPI_TRY(fapi2::putScom(iv_target, C_SPR_MODE, l_data)); - l_data.flush<0>(); - FAPI_TRY(fapi2::getScom(iv_target, C_SCOMC, l_data)); - l_data.insertFromRight(0); - FAPI_TRY(fapi2::putScom(iv_target, C_SCOMC, l_data)); - - //2.put restore data into SCR0 + //1.put restore data into SCR0 FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, iv_backup_buf2)); - //3.create mfsprd opcode, ram into thread to restore GPR1 + //2.create mfsprd opcode, ram into thread to restore GPR1 l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR1; FAPI_TRY(ram_opcode(l_opcode, true)); + } + // restore GPR0 + if(!iv_write_gpr0) + { //iv_backup_buf1->GPR0 //1.put restore data into SCR0 FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, iv_backup_buf1)); @@ -192,62 +267,10 @@ fapi2::ReturnCode RamCore::ram_cleanup() //2.create mfsprd opcode, ram into thread to restore GPR0 l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; FAPI_TRY(ram_opcode(l_opcode, true)); - - //iv_backup_buf0->SCR0 - FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, iv_backup_buf0)); - } - // restore GPR0/SCR0 - else if(!iv_write_gpr0 && iv_write_gpr1) - { - //iv_backup_buf1->GPR0 - //1.setup SPRC to use SCRO as SPRD - FAPI_TRY(fapi2::getScom(iv_target, C_SPR_MODE, l_data)); - FAPI_TRY(l_data.setBit(C_SPR_MODE_MODEREG_SPRC_LT0_SEL + iv_thread)); - FAPI_TRY(fapi2::putScom(iv_target, C_SPR_MODE, l_data)); - l_data.flush<0>(); - FAPI_TRY(fapi2::getScom(iv_target, C_SCOMC, l_data)); - l_data.insertFromRight(0); - FAPI_TRY(fapi2::putScom(iv_target, C_SCOMC, l_data)); - - //2.put restore data into SCR0 - FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, iv_backup_buf1)); - - //3.create mfsprd opcode, ram into thread to restore GPR0 - l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; - FAPI_TRY(ram_opcode(l_opcode, true)); - - //iv_backup_buf0->SCR0 - FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, iv_backup_buf0)); } - // restore GPR1/SCR0 - else if(iv_write_gpr0 && !iv_write_gpr1) - { - //iv_backup_buf2->GPR1 - //1.setup SPRC to use SCRO as SPRD - FAPI_TRY(fapi2::getScom(iv_target, C_SPR_MODE, l_data)); - FAPI_TRY(l_data.setBit(C_SPR_MODE_MODEREG_SPRC_LT0_SEL + iv_thread)); - FAPI_TRY(fapi2::putScom(iv_target, C_SPR_MODE, l_data)); - l_data.flush<0>(); - FAPI_TRY(fapi2::getScom(iv_target, C_SCOMC, l_data)); - l_data.insertFromRight(0); - FAPI_TRY(fapi2::putScom(iv_target, C_SCOMC, l_data)); - - //2.put restore data into SCR0 - FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, iv_backup_buf2)); - //3.create mfsprd opcode, ram into thread to restore GPR1 - l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR1; - FAPI_TRY(ram_opcode(l_opcode, true)); - - //iv_backup_buf0->SCR0 - FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, iv_backup_buf0)); - } - // restore SCR0 - else - { - //iv_backup_buf0->SCR0 - FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, iv_backup_buf0)); - } + //iv_backup_buf0->SCR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, iv_backup_buf0)); // set RAM_MODEREG Scom to clear RAM mode l_data.flush<0>(); @@ -255,23 +278,24 @@ fapi2::ReturnCode RamCore::ram_cleanup() l_data.clearBit(); FAPI_TRY(fapi2::putScom(iv_target, C_RAM_MODEREG, l_data)); - iv_ram_enable = false; - iv_ram_setup = false; - iv_write_gpr0 = false; - iv_write_gpr1 = false; + iv_ram_enable = false; + iv_ram_scr0_save = false; + iv_ram_setup = false; + iv_write_gpr0 = false; + iv_write_gpr1 = false; fapi_try_exit: - FAPI_INF("Exiting ram cleanup"); + FAPI_DBG("Exiting ram cleanup"); return fapi2::current_err; } //----------------------------------------------------------------------------------- fapi2::ReturnCode RamCore::ram_opcode(const uint32_t i_opcode, const bool i_allow_mult) { - FAPI_INF("Start ram opcode"); + FAPI_DBG("Start ram opcode"); fapi2::buffer l_data = 0; - uint8_t l_predecode = 0; - uint8_t l_poll_count = RAM_CORE_STAT_POLL_CNT; + uint8_t l_predecode = 0; + uint32_t l_poll_count = RAM_CORE_STAT_POLL_CNT; bool l_is_load_store = false; // check the opcode for load/store @@ -343,32 +367,94 @@ fapi2::ReturnCode RamCore::ram_opcode(const uint32_t i_opcode, const bool i_allo } fapi_try_exit: - FAPI_INF("Exiting ram opcode"); + + if(fapi2::current_err != fapi2::FAPI2_RC_SUCCESS) + { + iv_ram_err = true; + } + + FAPI_DBG("Exiting ram opcode"); return fapi2::current_err; } //----------------------------------------------------------------------------------- uint8_t RamCore::gen_predecode(const uint32_t i_opcode) { - //TODO: implement when the PC workbook is updated - return 0; + //TODO: make sure they are final version in PC workbook table 9-1 and 9-2 + uint8_t l_predecode = 0; + uint32_t l_opcode_pattern0 = i_opcode & 0xFC0007FE; + uint32_t l_opcode_pattern1 = i_opcode & 0xFC1FFFFE; + + if((i_opcode == OPCODE_MFNIA_RT) || + (i_opcode == OPCODE_GPR_MOVE) || + (i_opcode == OPCODE_VSR_MOVE_HI) || + (i_opcode == OPCODE_VSR_MOVE_LO) || + (i_opcode == OPCODE_XER_MOVE) || + (i_opcode == OPCODE_CR_MOVE)) + { + l_predecode = 2; + } + else if((i_opcode == OPCODE_MTNIA_LR) || + (l_opcode_pattern0 == OPCODE_MTMSR_L0) || + (l_opcode_pattern0 == OPCODE_MTMSRD_L0)) + { + l_predecode = 8; + } + else if((l_opcode_pattern1 == OPCODE_MTSPR_IAMR) || + (l_opcode_pattern1 == OPCODE_MTSPR_PIDR) || + (l_opcode_pattern1 == OPCODE_MTSPR_LPIDR) || + (l_opcode_pattern1 == OPCODE_MTSPR_LPCR) || + (l_opcode_pattern1 == OPCODE_MTSPR_MMCRA) || + (l_opcode_pattern1 == OPCODE_MTSPR_MMCR1) || + (l_opcode_pattern1 == OPCODE_MTSPR_SEIDBAR) || + (l_opcode_pattern1 == OPCODE_MTSPR_XER) || + (l_opcode_pattern1 == OPCODE_MFSPR_XER) || + (l_opcode_pattern0 == OPCODE_MFFS) || + (l_opcode_pattern0 == OPCODE_SLBMFEE) || + (l_opcode_pattern0 == OPCODE_SLBMFEV)) + { + l_predecode = 4; + } + + return l_predecode; } //----------------------------------------------------------------------------------- bool RamCore::is_load_store(const uint32_t i_opcode) { - //TODO: implement when the PC workbook is updated - return false; + //TODO: make sure they are final version in PC workbook table 9-1 + bool l_load_store = false; + uint32_t l_opcode_pattern0 = i_opcode & 0xFC0007FE; + uint32_t l_opcode_pattern1 = i_opcode & 0xFC000000; + + if((l_opcode_pattern0 == OPCODE_DCBZ) || + (l_opcode_pattern0 == OPCODE_DCBF) || + (l_opcode_pattern1 == OPCODE_LD) || + (l_opcode_pattern1 == OPCODE_LFD) || + (l_opcode_pattern1 == OPCODE_STD) || + (l_opcode_pattern1 == OPCODE_LFD) || + (l_opcode_pattern1 == OPCODE_STFD) || + (l_opcode_pattern0 == OPCODE_LVX) || + (l_opcode_pattern0 == OPCODE_STVX) || + (l_opcode_pattern0 == OPCODE_LXVD2X) || + (l_opcode_pattern0 == OPCODE_STXVD2X)) + { + l_load_store = true; + } + + return l_load_store; } //----------------------------------------------------------------------------------- fapi2::ReturnCode RamCore::get_reg(const Enum_RegType i_type, const uint32_t i_reg_num, fapi2::buffer* o_buffer, const bool i_allow_mult) { - FAPI_INF("Start get register"); + FAPI_DBG("Start get register"); uint32_t l_opcode = 0; uint32_t l_spr_regnum_lo = 0; uint32_t l_spr_regnum_hi = 0; + fapi2::buffer l_backup_gpr0 = 0; + fapi2::buffer l_backup_fpr0 = 0; // ram_setup if(!i_allow_mult) @@ -380,6 +466,14 @@ fapi2::ReturnCode RamCore::get_reg(const Enum_RegType i_type, const uint32_t i_r fapi2::P9_RAM_NOT_SETUP_ERR(), "Attempting to get register without setup before"); + //backup GPR0 if it is written + if(iv_write_gpr0) + { + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, l_backup_gpr0)); + } + // get register value if(i_type == REG_GPR) { @@ -393,20 +487,88 @@ fapi2::ReturnCode RamCore::get_reg(const Enum_RegType i_type, const uint32_t i_r } else if(i_type == REG_SPR) { - //1.create mfspr opcode, ram into thread - l_opcode = OPCODE_MFSPR_FROM_SPR0_TO_GPR0; - l_spr_regnum_lo = i_reg_num & 0x0000001F; - l_spr_regnum_hi = i_reg_num & 0x000003E0; - l_opcode += (l_spr_regnum_lo << 16); - l_opcode += (l_spr_regnum_hi << 11); - FAPI_TRY(ram_opcode(l_opcode, true)); + if(i_reg_num == RAM_REG_NIA) + { + //1.ram MFNIA_RT opcode + l_opcode = OPCODE_MFNIA_RT; + FAPI_TRY(ram_opcode(l_opcode, true)); - //2.create mtsprd opcode, ram into thread - l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; - FAPI_TRY(ram_opcode(l_opcode, true)); + //2.get NIA from GPR0 + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); - //3.get GPR value from SCR0 - FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[0])); + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[0])); + } + else if(i_reg_num == RAM_REG_MSR) + { + //1.create mfmsr opcode, ram into thread + l_opcode = OPCODE_MFMSR_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //2.get MSR value from SCR0 + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[0])); + } + else if(i_reg_num == RAM_REG_CR) + { + //1.create mfcr opcode, ram into thread + l_opcode = OPCODE_MFCR_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //2.get MSR value from SCR0 + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[0])); + } + else if(i_reg_num == RAM_REG_FPSCR) + { + //1.backup FPR0 + l_opcode = OPCODE_MFFPRD_FROM_FPR0_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, l_backup_fpr0)); + + //2.create mffs opcode, ram into thread + l_opcode = OPCODE_MFFS; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //3.get FPSCR value from SCR0 + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[0])); + + //4.restore FPR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, l_backup_fpr0)); + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + l_opcode = OPCODE_MTFPRD_FROM_GPR0_TO_FPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + } + else + { + //1.create mfspr opcode, ram into thread + l_opcode = OPCODE_MFSPR_FROM_SPR0_TO_GPR0; + l_spr_regnum_lo = i_reg_num & 0x0000001F; + l_spr_regnum_hi = i_reg_num & 0x000003E0; + l_opcode += (l_spr_regnum_lo << 16); + l_opcode += (l_spr_regnum_hi << 6); + FAPI_TRY(ram_opcode(l_opcode, true)); + + //2.create mtsprd opcode, ram into thread + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //3.get GPR value from SCR0 + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[0])); + } } else if(i_type == REG_FPR) { @@ -422,11 +584,22 @@ fapi2::ReturnCode RamCore::get_reg(const Enum_RegType i_type, const uint32_t i_r //3.get GPR value from SCR0 FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[0])); } + +#ifndef __PPE__ else if(i_type == REG_VSR) { - //1.create mfvsrd#SX=1 opcode, ram into thread to get dw0 - l_opcode = OPCODE_MFVSRD_FROM_VSR0_TO_GPR0; - l_opcode += (i_reg_num << 21); + //1.create mfvsrd opcode, ram into thread to get dw0 + if(i_reg_num < 32) + { + l_opcode = OPCODE_MFVSRD_FROM_VSR0_TO_GPR0; + l_opcode += (i_reg_num << 21); + } + else + { + l_opcode = OPCODE_MFVSRD_FROM_VSR32_TO_GPR0; + l_opcode += ((i_reg_num - 32) << 21); + } + FAPI_TRY(ram_opcode(l_opcode, true)); //2.create mtsprd opcode, ram into thread @@ -436,9 +609,18 @@ fapi2::ReturnCode RamCore::get_reg(const Enum_RegType i_type, const uint32_t i_r //3.get VSR dw0 value from SCR0 FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[0])); - //4.create mfvrld#SX=1 opcode, ram into thread to get dw1 - l_opcode = OPCODE_MFVSRLD_FROM_VSR0_TO_GPR0; - l_opcode += (i_reg_num << 21); + //4.create mfvrld opcode, ram into thread to get dw1 + if(i_reg_num < 32) + { + l_opcode = OPCODE_MFVSRLD_FROM_VSR0_TO_GPR0; + l_opcode += (i_reg_num << 21); + } + else + { + l_opcode = OPCODE_MFVSRLD_FROM_VSR32_TO_GPR0; + l_opcode += ((i_reg_num - 32) << 21); + } + FAPI_TRY(ram_opcode(l_opcode, true)); //5.create mtsprd opcode, ram into thread @@ -448,6 +630,8 @@ fapi2::ReturnCode RamCore::get_reg(const Enum_RegType i_type, const uint32_t i_r //6.get VSR dw1 value from SCR0 FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[1])); } + +#endif else { FAPI_ASSERT(false, @@ -456,6 +640,14 @@ fapi2::ReturnCode RamCore::get_reg(const Enum_RegType i_type, const uint32_t i_r "Type of reg is not supported"); } + //restore GPR0 if necessary + if(iv_write_gpr0) + { + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, l_backup_gpr0)); + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + } + // ram_cleanup if(!i_allow_mult) { @@ -463,18 +655,33 @@ fapi2::ReturnCode RamCore::get_reg(const Enum_RegType i_type, const uint32_t i_r } fapi_try_exit: - FAPI_INF("Exiting get register"); - return fapi2::current_err; + // Error happened and it's not ram error, call ram_cleanup to restore the backup registers + // If it is ram error, do not call ram_cleanup, so that no new ramming will be executed + // Do not use "FAPI_TRY" to avoid endless loop + fapi2::ReturnCode first_err = fapi2::current_err; + + if((fapi2::current_err != fapi2::FAPI2_RC_SUCCESS) && !iv_ram_err && iv_ram_setup) + { + ram_cleanup(); + } + + FAPI_DBG("Exiting get register"); + return first_err; } //----------------------------------------------------------------------------------- fapi2::ReturnCode RamCore::put_reg(const Enum_RegType i_type, const uint32_t i_reg_num, const fapi2::buffer* i_buffer, const bool i_allow_mult) { - FAPI_INF("Start put register"); + FAPI_DBG("Start put register"); uint32_t l_opcode = 0; uint32_t l_spr_regnum_lo = 0; uint32_t l_spr_regnum_hi = 0; + bool l_write_gpr0 = false; + fapi2::buffer l_backup_lr = 0; + fapi2::buffer l_backup_gpr0 = 0; + fapi2::buffer l_backup_gpr1 = 0; + fapi2::buffer l_backup_fpr0 = 0; // ram_setup if(!i_allow_mult) @@ -486,6 +693,26 @@ fapi2::ReturnCode RamCore::put_reg(const Enum_RegType i_type, const uint32_t i_r fapi2::P9_RAM_NOT_SETUP_ERR(), "Attempting to put register without setup before"); + //backup GPR0 if it is written + if(iv_write_gpr0) + { + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, l_backup_gpr0)); + } + +#ifndef __PPE__ + + //backup GPR1 if it is written + if(iv_write_gpr1 && (i_type == REG_VSR)) + { + l_opcode = OPCODE_MTSPR_FROM_GPR1_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, l_backup_gpr1)); + } + +#endif + // put register value if(i_type == REG_GPR) { @@ -500,6 +727,7 @@ fapi2::ReturnCode RamCore::put_reg(const Enum_RegType i_type, const uint32_t i_r if(i_reg_num == 0) { iv_write_gpr0 = true; + l_write_gpr0 = true; } if(i_reg_num == 1) @@ -509,20 +737,111 @@ fapi2::ReturnCode RamCore::put_reg(const Enum_RegType i_type, const uint32_t i_r } else if(i_type == REG_SPR) { - //1.put SPR value into SCR0 - FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, i_buffer[0])); + if(i_reg_num == RAM_REG_NIA) + { + //1.backup LR + l_opcode = OPCODE_MFSPR_FROM_LR_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); - //2.create mfsprd opcode, ram into thread - l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; - FAPI_TRY(ram_opcode(l_opcode, true)); + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); - //3.create mtspr opcode, ram into thread - l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPR0; - l_spr_regnum_lo = i_reg_num & 0x0000001F; - l_spr_regnum_hi = i_reg_num & 0x000003E0; - l_opcode += (l_spr_regnum_lo << 16); - l_opcode += (l_spr_regnum_hi << 11); - FAPI_TRY(ram_opcode(l_opcode, true)); + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, l_backup_lr)); + + //2.put NIA value into LR + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, i_buffer[0])); + + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_LR; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //3.ram MTNIA_LR opcode + l_opcode = OPCODE_MTNIA_LR; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //4.restore LR + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, l_backup_lr)); + + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_LR; + FAPI_TRY(ram_opcode(l_opcode, true)); + } + else if(i_reg_num == RAM_REG_MSR) + { + //1.put SPR value into SCR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, i_buffer[0])); + + //2.create mfsprd opcode, ram into thread + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //3.create mtmsrd opcode, ram into thread + l_opcode = OPCODE_MTMSRD_L0; + FAPI_TRY(ram_opcode(l_opcode, true)); + } + else if(i_reg_num == RAM_REG_CR) + { + //1.put SPR value into SCR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, i_buffer[0])); + + //2.create mfsprd opcode, ram into thread + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //3.create mtcrf opcode, ram into thread + l_opcode = OPCODE_MTCRF_FROM_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + } + else if(i_reg_num == RAM_REG_FPSCR) + { + //1.backup FPR0 + l_opcode = OPCODE_MFFPRD_FROM_FPR0_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD; + FAPI_TRY(ram_opcode(l_opcode, true)); + + FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, l_backup_fpr0)); + + //2.put SPR value into GPR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, i_buffer[0])); + + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //3.create mtfsf opcode, ram into thread + l_opcode = OPCODE_MTFSF_FROM_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //4.restore FPR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, l_backup_fpr0)); + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + l_opcode = OPCODE_MTFPRD_FROM_GPR0_TO_FPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + } + else + { + //1.put SPR value into SCR0 + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, i_buffer[0])); + + //2.create mfsprd opcode, ram into thread + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + + //3.create mtspr opcode, ram into thread + l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPR0; + l_spr_regnum_lo = i_reg_num & 0x0000001F; + l_spr_regnum_hi = i_reg_num & 0x000003E0; + l_opcode += (l_spr_regnum_lo << 16); + l_opcode += (l_spr_regnum_hi << 6); + FAPI_TRY(ram_opcode(l_opcode, true)); + } } else if(i_type == REG_FPR) { @@ -538,6 +857,8 @@ fapi2::ReturnCode RamCore::put_reg(const Enum_RegType i_type, const uint32_t i_r l_opcode += (i_reg_num << 21); FAPI_TRY(ram_opcode(l_opcode, true)); } + +#ifndef __PPE__ else if(i_type == REG_VSR) { //1.put VSR dw1 value into SCR0 @@ -556,10 +877,21 @@ fapi2::ReturnCode RamCore::put_reg(const Enum_RegType i_type, const uint32_t i_r FAPI_TRY(ram_opcode(l_opcode, true)); //5.create mtvsrdd opcode, ram into thread - l_opcode = OPCODE_MTVSRDD_FROM_GPR1_0_TO_VSR0; - l_opcode += (i_reg_num << 21); + if(i_reg_num < 32) + { + l_opcode = OPCODE_MTVSRDD_FROM_GPR1_0_TO_VSR0; + l_opcode += (i_reg_num << 21); + } + else + { + l_opcode = OPCODE_MTVSRDD_FROM_GPR1_0_TO_VSR32; + l_opcode += ((i_reg_num - 32) << 21); + } + FAPI_TRY(ram_opcode(l_opcode, true)); } + +#endif else { FAPI_ASSERT(false, @@ -568,6 +900,26 @@ fapi2::ReturnCode RamCore::put_reg(const Enum_RegType i_type, const uint32_t i_r "Type of reg is not supported"); } + //restore GPR0 if necessary + if(iv_write_gpr0 && !l_write_gpr0) + { + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, l_backup_gpr0)); + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0; + FAPI_TRY(ram_opcode(l_opcode, true)); + } + +#ifndef __PPE__ + + //restore GPR1 if necessary + if(iv_write_gpr1 && (i_type == REG_VSR)) + { + FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, l_backup_gpr1)); + l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR1; + FAPI_TRY(ram_opcode(l_opcode, true)); + } + +#endif + // ram_cleanup if(!i_allow_mult) { @@ -575,7 +927,18 @@ fapi2::ReturnCode RamCore::put_reg(const Enum_RegType i_type, const uint32_t i_r } fapi_try_exit: - FAPI_INF("Exiting put register"); - return fapi2::current_err; + // Error happened and it's not ram error, call ram_cleanup to restore the backup registers + // If it is ram error, do not call ram_cleanup, so that no new ramming will be executed + // Do not use "FAPI_TRY" to avoid endless loop + fapi2::ReturnCode first_err = fapi2::current_err; + + if((fapi2::current_err != fapi2::FAPI2_RC_SUCCESS) && !iv_ram_err && iv_ram_setup) + { + ram_cleanup(); + } + + FAPI_DBG("Exiting put register"); + return first_err; } + diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.H b/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.H index 1e2d9d11b..2384bc8b4 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.H +++ b/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.H @@ -24,7 +24,7 @@ //----------------------------------------------------------------------------------- // *HWP HWP Owner : Liu Yang Fan // *HWP HWP Backup Owner : Gou Peng Fei -// *HWP FW Owner : Sachin Gupta +// *HWP FW Owner : Thi Tran // *HWP Team : Perv // *HWP Level : 2 // *HWP Consumed by : SBE @@ -132,11 +132,13 @@ class RamCore private: fapi2::Target iv_target; // core target - uint8_t iv_thread; // thread number - bool iv_ram_enable; // ram mode is enabled - bool iv_ram_setup; // ram mode is enabled and register backup is done - bool iv_write_gpr0; // putGPR0 operation is executed - bool iv_write_gpr1; // putGPR1 operatoin is executed + uint8_t iv_thread; // thread number + bool iv_ram_enable; // ram mode is enabled + bool iv_ram_scr0_save; // SCR0 is saved when setup + bool iv_ram_setup; // ram mode is enabled and register backup is done + bool iv_ram_err; // error happened during ram + bool iv_write_gpr0; // putGPR0 operation is executed + bool iv_write_gpr1; // putGPR1 operatoin is executed fapi2::buffer iv_backup_buf0; // register backup data fapi2::buffer iv_backup_buf1; // register backup data fapi2::buffer iv_backup_buf2; // register backup data diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_ram_getreg.H b/src/import/chips/p9/procedures/hwp/perv/p9_ram_getreg.H index d17c884b3..d74e3b1d9 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_ram_getreg.H +++ b/src/import/chips/p9/procedures/hwp/perv/p9_ram_getreg.H @@ -52,11 +52,11 @@ extern "C" { // Function prototype //----------------------------------------------------------------------------------- // @brief Implement Get Register(GPR/FPR/VSR) by ramming -/// @param[in] i_target => core target -/// @param[in] i_thread => thread number -/// @param[in] i_type => register access type (REG_GPR/REG_FPR/REG_VSR) -/// @param[in] i_reg_num => register number -/// @param[out] o_buffer => register value +/// @param[in] i_target => core target +/// @param[in] i_thread => thread number +/// @param[in] i_type => register access type (REG_GPR/REG_FPR/REG_VSR) +/// @param[in] i_reg_num => register number +/// @param[out] o_buffer => register value /// @return FAPI_RC_SUCCESS if the setup completes successfully // fapi2::ReturnCode p9_ram_getreg(const fapi2::Target& i_target, @@ -70,4 +70,3 @@ extern "C" { #endif //_P9_RAM_GETREG_H_ - diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_ram_getspr.C b/src/import/chips/p9/procedures/hwp/perv/p9_ram_getspr.C index fc10a1fbf..51356c066 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_ram_getspr.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_ram_getspr.C @@ -46,12 +46,24 @@ fapi2::ReturnCode p9_ram_getspr(const fapi2::Target& i_ { FAPI_INF("Start"); uint32_t spr_num = 0; + bool l_check_flag = false; // instantiate the basic RamCore class RamCore ram(i_target, i_thread); - // map spr register name to number - FAPI_TRY(p9_spr_name_map_init()); - FAPI_TRY(p9_spr_name_map(i_name, false, spr_num)); + + // init SPR_MAP + l_check_flag = p9_spr_name_map_init(); + FAPI_ASSERT(l_check_flag, + fapi2::P9_SPR_NAME_MAP_INIT_ERR(), + "SPR name map is not empty when initialization"); + + // map spr name to spr number + l_check_flag = p9_spr_name_map(i_name, false, spr_num); + FAPI_ASSERT(l_check_flag, + fapi2::P9_SPR_NAME_MAP_ACCESS_ERR() + .set_REGNAME(i_name), + "SPR name map access failed"); + // call RamCore get_reg method FAPI_TRY(ram.get_reg(REG_SPR, spr_num, o_buffer)); @@ -60,3 +72,4 @@ fapi_try_exit: return fapi2::current_err; } + diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_ram_getspr.H b/src/import/chips/p9/procedures/hwp/perv/p9_ram_getspr.H index e7e01cb2b..3fe4912b1 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_ram_getspr.H +++ b/src/import/chips/p9/procedures/hwp/perv/p9_ram_getspr.H @@ -52,10 +52,10 @@ extern "C" { // Function prototype //----------------------------------------------------------------------------------- /// @brief Implement Get SPR Register by ramming -/// @param[in] i_target => core target -/// @param[in] i_thread => thread number -/// @param[in] i_name => register name -/// @param[out] o_buffer => register value +/// @param[in] i_target => core target +/// @param[in] i_thread => thread number +/// @param[in] i_name => register name +/// @param[out] o_buffer => register value /// @return FAPI_RC_SUCCESS if the setup completes successfully // fapi2::ReturnCode p9_ram_getspr(const fapi2::Target& i_target, @@ -67,3 +67,4 @@ extern "C" { #endif //_P9_RAM_GETSPR_H_ + diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_ram_putreg.H b/src/import/chips/p9/procedures/hwp/perv/p9_ram_putreg.H index 314df8706..e1ce116e1 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_ram_putreg.H +++ b/src/import/chips/p9/procedures/hwp/perv/p9_ram_putreg.H @@ -52,11 +52,11 @@ extern "C" { // Function prototype //----------------------------------------------------------------------------------- /// @brief Implement Put Register(GPR/FPR/VSR) by ramming -/// @param[in] i_target => core target -/// @param[in] i_thread => thread number -/// @param[in] i_type => register access type (REG_GPR/REG_FPR/REG_VSR) -/// @param[in] i_reg_num => register number -/// @param[in] i_buffer => register value +/// @param[in] i_target => core target +/// @param[in] i_thread => thread number +/// @param[in] i_type => register access type (REG_GPR/REG_FPR/REG_VSR) +/// @param[in] i_reg_num => register number +/// @param[in] i_buffer => register value /// @return FAPI_RC_SUCCESS if the setup completes successfully // fapi2::ReturnCode p9_ram_putreg(const fapi2::Target& i_target, @@ -72,3 +72,4 @@ extern "C" { + diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_ram_putspr.C b/src/import/chips/p9/procedures/hwp/perv/p9_ram_putspr.C index 922983879..8573513f1 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_ram_putspr.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_ram_putspr.C @@ -46,12 +46,24 @@ fapi2::ReturnCode p9_ram_putspr(const fapi2::Target& i_ { FAPI_INF("Start"); uint32_t spr_num = 0; + bool l_check_flag = false; // instantiate the basic RamCore class RamCore ram(i_target, i_thread); - // map spr register name to number - FAPI_TRY(p9_spr_name_map_init()); - FAPI_TRY(p9_spr_name_map(i_name, true, spr_num)); + + // init SPR_MAP + l_check_flag = p9_spr_name_map_init(); + FAPI_ASSERT(l_check_flag, + fapi2::P9_SPR_NAME_MAP_INIT_ERR(), + "SPR name map is not empty when initialization"); + + // map spr name to spr number + l_check_flag = p9_spr_name_map(i_name, true, spr_num); + FAPI_ASSERT(l_check_flag, + fapi2::P9_SPR_NAME_MAP_ACCESS_ERR() + .set_REGNAME(i_name), + "SPR name map access failed"); + // call RamCore put_reg method FAPI_TRY(ram.put_reg(REG_SPR, spr_num, i_buffer)); @@ -60,3 +72,4 @@ fapi_try_exit: return fapi2::current_err; } + diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_ram_putspr.H b/src/import/chips/p9/procedures/hwp/perv/p9_ram_putspr.H index c653c6534..9fd8106df 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_ram_putspr.H +++ b/src/import/chips/p9/procedures/hwp/perv/p9_ram_putspr.H @@ -62,8 +62,8 @@ extern "C" { const uint8_t i_thread, const std::string i_name, const fapi2::buffer* i_buffer); + } //extern"C" #endif //_P9_RAM_PUTSPR_H_ - diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_spr_name_map.C b/src/import/chips/p9/procedures/hwp/perv/p9_spr_name_map.C index 5f66efa4c..5f9046693 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_spr_name_map.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_spr_name_map.C @@ -36,26 +36,28 @@ //----------------------------------------------------------------------------------- #include +std::map SPR_MAP; +bool spr_map_initialized = false; + //----------------------------------------------------------------------------------- // Function definitions //----------------------------------------------------------------------------------- -std::map spr_map; - -fapi2::ReturnCode p9_spr_name_map_init() +bool p9_spr_name_map_init() { - FAPI_INF("Start SPR name map init"); - - FAPI_ASSERT(spr_map.empty(), - fapi2::P9_SPR_NAME_MAP_INIT_ERR(), - "SPR name map is not empty when initialization"); + if (spr_map_initialized) + { + return true; + } + if (!SPR_MAP.empty()) { - LIST_SPR_REG(DO_SPR_MAP) + return false; } -fapi_try_exit: - FAPI_INF("Exiting SPR name map init"); - return fapi2::current_err; + LIST_SPR_REG(DO_SPR_MAP) + spr_map_initialized = true; + + return true; } //----------------------------------------------------------------------------------- @@ -67,33 +69,63 @@ bool p9_spr_name_map_check_flag(unsigned char i_reg_flag, bool i_write) } //----------------------------------------------------------------------------------- -fapi2::ReturnCode p9_spr_name_map(const std::string i_name, const bool i_write, uint32_t& o_number) +bool p9_spr_name_map(const std::string i_name, const bool i_write, uint32_t& o_number) { - FAPI_INF("Start SPR name map"); bool l_check_flag = false; - if(spr_map.find(i_name) != spr_map.end()) + if(SPR_MAP.find(i_name) != SPR_MAP.end()) + { + l_check_flag = p9_spr_name_map_check_flag(SPR_MAP[i_name].flag, i_write); + + if(l_check_flag) + { + o_number = SPR_MAP[i_name].number; + } + } + + return l_check_flag; +} + +//----------------------------------------------------------------------------------- +bool p9_get_share_type(const std::string i_name, Enum_ShareType& o_share_type) +{ + bool l_rc = false; + + if(SPR_MAP.find(i_name) != SPR_MAP.end()) { - l_check_flag = p9_spr_name_map_check_flag(spr_map[i_name].flag, i_write); + o_share_type = SPR_MAP[i_name].share_type; + l_rc = true; + } - FAPI_ASSERT(l_check_flag, - fapi2::P9_SPR_INVALID_RW_MODE_ACCESS_ERR() - .set_REGNAME(i_name) - .set_RWFLAG(spr_map[i_name].flag), - "SPR RW mode check failed"); + return l_rc; +} - o_number = spr_map[i_name].number; +//----------------------------------------------------------------------------------- +bool p9_get_bit_length(const std::string i_name, uint8_t& o_bit_length) +{ + bool l_rc = false; + + if(SPR_MAP.find(i_name) != SPR_MAP.end()) + { + o_bit_length = SPR_MAP[i_name].bit_length; + l_rc = true; } - else + + return l_rc; +} + +//----------------------------------------------------------------------------------- +bool p9_get_spr_entry(const std::string i_name, SPRMapEntry& o_spr_entry) +{ + bool l_rc = false; + + if(SPR_MAP.find(i_name) != SPR_MAP.end()) { - FAPI_ASSERT(false, - fapi2::P9_SPR_INVALID_NAME_ACCESS_ERR() - .set_REGNAME(i_name), - "SPR name is invalid"); + o_spr_entry = SPR_MAP[i_name]; + l_rc = true; } -fapi_try_exit: - FAPI_INF("Exiting SPR name map"); - return fapi2::current_err; + return l_rc; } + diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_spr_name_map.H b/src/import/chips/p9/procedures/hwp/perv/p9_spr_name_map.H index 0e9892109..70a4bbc8d 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_spr_name_map.H +++ b/src/import/chips/p9/procedures/hwp/perv/p9_spr_name_map.H @@ -37,7 +37,6 @@ // Includes //----------------------------------------------------------------------------------- #include -#include // Read-Write mode flag for each SPR register const unsigned char FLAG_READ_ONLY = 0x1; @@ -47,172 +46,196 @@ const unsigned char FLAG_READ_WRITE = 0x3; //----------------------------------------------------------------------------------- // Structure definitions //----------------------------------------------------------------------------------- +enum Enum_ShareType +{ + SPR_PER_CORE, + SPR_PER_LPAR_PT, + SPR_PER_LPAR_VT, + SPR_PER_PT, + SPR_PER_VT, + SPR_SHARED, + SPR_PARTIAL_SHARED, + SPR_SHARE_NA // unknown, or dependent on certain conditions +}; + typedef struct { int number; std::string spy_name; // 0x1: read-only; 0x2: write-only; 0x3 read-write unsigned char flag; + Enum_ShareType share_type; + uint8_t bit_length; } SPRMapEntry; +//----------------------------------------------------------------------------------- +// Global variable definitions +//----------------------------------------------------------------------------------- +extern std::map SPR_MAP; +extern bool spr_map_initialized; +typedef std::map::iterator SPR_MAP_IT; // List all the SPR registers(name, number, spy_name, flag) // Reference on the P9 care bringup wiki // Note: // when ram is enabled, the hardware forces HV=1 PR=0 // current spy names are got from +// For the SPY names, should be replaced with thread ID, should be +// replaced with core ID. #define LIST_SPR_REG(_op_)\ - _op_(XER ,1 , Reserved ,FLAG_READ_WRITE)\ - _op_(DSCR_RU ,3 , Reserved ,FLAG_READ_WRITE)\ - _op_(LR ,8 , Reserved ,FLAG_READ_WRITE)\ - _op_(CTR ,9 , Reserved ,FLAG_READ_WRITE)\ - _op_(UAMR ,13 , Reserved ,FLAG_READ_WRITE)\ - _op_(DSCR ,17 , Reserved ,FLAG_READ_WRITE)\ - _op_(DSISR ,18 , Reserved ,FLAG_READ_WRITE)\ - _op_(DAR ,19 , Reserved ,FLAG_READ_WRITE)\ - _op_(DEC ,22 , V_DEC ,FLAG_READ_WRITE)\ - _op_(SDR1 ,25 , Reserved ,FLAG_READ_WRITE)\ - _op_(SRR0 ,26 , Reserved ,FLAG_READ_WRITE)\ - _op_(SRR1 ,27 , Reserved ,FLAG_READ_WRITE)\ - _op_(CFAR ,28 , Reserved ,FLAG_READ_WRITE)\ - _op_(AMR ,29 , Reserved ,FLAG_READ_WRITE)\ - _op_(PIDR ,48 , Reserved ,FLAG_READ_WRITE)\ - _op_(IAMR ,61 , Reserved ,FLAG_READ_WRITE)\ - _op_(TFHAR ,128 , Reserved ,FLAG_READ_WRITE)\ - _op_(TFIAR ,129 , Reserved ,FLAG_READ_WRITE)\ - _op_(TEXASR ,130 , Reserved ,FLAG_READ_WRITE)\ - _op_(TEXASRU ,131 , Reserved ,FLAG_READ_WRITE)\ - _op_(CTRL_RU ,136 , CTRL ,FLAG_READ_ONLY )\ - _op_(TIDR ,144 , CTRL ,FLAG_READ_WRITE)\ - _op_(CTRL ,152 , Reserved ,FLAG_WRITE_ONLY)\ - _op_(FSCR ,153 , Reserved ,FLAG_READ_WRITE)\ - _op_(UAMOR ,157 , Reserved ,FLAG_READ_WRITE)\ - _op_(GSR ,158 , Reserved ,FLAG_READ_WRITE)\ - _op_(PSPB ,159 , V_PSPB ,FLAG_READ_WRITE)\ - _op_(DPDES ,176 , DPDES ,FLAG_READ_WRITE)\ - _op_(DAWR0 ,180 , Reserved ,FLAG_READ_WRITE)\ - _op_(RPR ,186 , Reserved ,FLAG_READ_WRITE)\ - _op_(CIABR ,187 , Reserved ,FLAG_READ_WRITE)\ - _op_(DAWRX0 ,188 , Reserved ,FLAG_READ_WRITE)\ - _op_(HFSCR ,190 , Reserved ,FLAG_READ_WRITE)\ - _op_(VRSAVE ,256 , Reserved ,FLAG_READ_WRITE)\ - _op_(SPRG3_RU ,259 , T_SPRG3 ,FLAG_READ_ONLY )\ - _op_(TB ,268 , L_TB ,FLAG_READ_ONLY )\ - _op_(TBU_RU ,269 , L_TBU ,FLAG_READ_ONLY )\ - _op_(SPRG0 ,272 , T_SPRG0 ,FLAG_READ_WRITE)\ - _op_(SPRG1 ,273 , T_SPRG1 ,FLAG_READ_WRITE)\ - _op_(SPRG2 ,274 , T_SPRG2 ,FLAG_READ_WRITE)\ - _op_(SPRG3 ,275 , T_SPRG3 ,FLAG_READ_WRITE)\ - _op_(SPRC ,276 , Reserved ,FLAG_READ_WRITE)\ - _op_(SPRD ,277 , Reserved ,FLAG_READ_WRITE)\ - _op_(CIR ,283 , CIR ,FLAG_READ_ONLY )\ - _op_(TBL ,284 , V_TBL ,FLAG_WRITE_ONLY)\ - _op_(TBLU ,285 , L_TBU ,FLAG_WRITE_ONLY)\ - _op_(TBU40 ,286 , L_TBU40 ,FLAG_WRITE_ONLY)\ - _op_(PVR ,287 , PVR ,FLAG_READ_ONLY )\ - _op_(HSPRG0 ,304 , T_HSPRG0 ,FLAG_READ_WRITE)\ - _op_(HSPRG1 ,305 , T_HSPRG1 ,FLAG_READ_WRITE)\ - _op_(HDSISR ,306 , Reserved ,FLAG_READ_WRITE)\ - _op_(HDAR ,307 , Reserved ,FLAG_READ_WRITE)\ - _op_(SPURR ,308 , V_SPURR ,FLAG_READ_WRITE)\ - _op_(PURR ,309 , V_PURR ,FLAG_READ_WRITE)\ - _op_(HDEC ,310 , L_HDEC ,FLAG_READ_WRITE)\ - _op_(RMOR ,312 , Reserved ,FLAG_READ_WRITE)\ - _op_(HRMOR ,313 , Reserved ,FLAG_READ_WRITE)\ - _op_(HSRR0 ,314 , Reserved ,FLAG_READ_WRITE)\ - _op_(HSRR1 ,315 , Reserved ,FLAG_READ_WRITE)\ - _op_(TFMR ,317 , V_TFMR ,FLAG_READ_WRITE)\ - _op_(LPCR ,318 , Reserved ,FLAG_READ_WRITE)\ - _op_(LPIDR ,319 , Reserved ,FLAG_READ_WRITE)\ - _op_(HMER ,336 , V_HMER ,FLAG_READ_WRITE)\ - _op_(HMEER ,337 , HMEER ,FLAG_READ_WRITE)\ - _op_(PCR ,338 , L_PCR ,FLAG_READ_WRITE)\ - _op_(HEIR ,339 , Reserved ,FLAG_READ_WRITE)\ - _op_(AMOR ,349 , Reserved ,FLAG_READ_WRITE)\ - _op_(TIR ,446 , TIR ,FLAG_READ_ONLY )\ - _op_(PTCR ,464 , Reserved ,FLAG_READ_WRITE)\ - _op_(USPRG0 ,496 , Reserved ,FLAG_READ_WRITE)\ - _op_(USPRG1 ,497 , Reserved ,FLAG_READ_WRITE)\ - _op_(UDAR ,499 , Reserved ,FLAG_READ_WRITE)\ - _op_(SEIDR ,504 , Reserved ,FLAG_READ_WRITE)\ - _op_(URMOR ,505 , Reserved ,FLAG_READ_WRITE)\ - _op_(USRR0 ,506 , Reserved ,FLAG_READ_WRITE)\ - _op_(USRR1 ,507 , Reserved ,FLAG_READ_WRITE)\ - _op_(UEIR ,509 , Reserved ,FLAG_READ_WRITE)\ - _op_(ACMCR ,510 , Reserved ,FLAG_READ_WRITE)\ - _op_(SEIDBAR ,511 , Reserved ,FLAG_READ_WRITE)\ - _op_(SIER_RU ,768 , Reserved ,FLAG_READ_ONLY )\ - _op_(MMCR2_RU ,769 , Reserved ,FLAG_READ_ONLY )\ - _op_(MMCRA_RU ,770 , Reserved ,FLAG_READ_ONLY )\ - _op_(PMC1_RU ,771 , Reserved ,FLAG_READ_ONLY )\ - _op_(PMC2_RU ,772 , Reserved ,FLAG_READ_ONLY )\ - _op_(PMC3_RU ,773 , Reserved ,FLAG_READ_ONLY )\ - _op_(PMC4_RU ,774 , Reserved ,FLAG_READ_ONLY )\ - _op_(PMC5_RU ,775 , Reserved ,FLAG_READ_ONLY )\ - _op_(PMC6_RU ,776 , Reserved ,FLAG_READ_ONLY )\ - _op_(MMCR0_RU ,779 , Reserved ,FLAG_READ_ONLY )\ - _op_(SIAR_RU ,780 , Reserved ,FLAG_READ_ONLY )\ - _op_(SDAR_RU ,781 , Reserved ,FLAG_READ_ONLY )\ - _op_(MMCR1_RU ,782 , Reserved ,FLAG_READ_ONLY )\ - _op_(SIER ,784 , T_SIER ,FLAG_READ_WRITE)\ - _op_(MMCR2 ,785 , T_MMCR2 ,FLAG_READ_WRITE)\ - _op_(MMCRA ,786 , T_MMCRA ,FLAG_READ_WRITE)\ - _op_(PMC1 ,787 , T_PMC1 ,FLAG_READ_WRITE)\ - _op_(PMC2 ,788 , T_PMC2 ,FLAG_READ_WRITE)\ - _op_(PMC3 ,789 , T_PMC3 ,FLAG_READ_WRITE)\ - _op_(PMC4 ,790 , T_PMC4 ,FLAG_READ_WRITE)\ - _op_(PMC5 ,791 , T_PMC5 ,FLAG_READ_WRITE)\ - _op_(PMC6 ,792 , T_PMC6 ,FLAG_READ_WRITE)\ - _op_(MMCR0 ,795 , T_MMCR0 ,FLAG_READ_WRITE)\ - _op_(SIAR ,796 , Reserved ,FLAG_READ_WRITE)\ - _op_(SDAR ,797 , Reserved ,FLAG_READ_WRITE)\ - _op_(MMCR1 ,798 , T_MMCR1 ,FLAG_READ_WRITE)\ - _op_(IMC ,799 , Reserved ,FLAG_READ_WRITE)\ - _op_(BESCRS ,800 , Reserved ,FLAG_READ_WRITE)\ - _op_(BESCRSU ,801 , Reserved ,FLAG_READ_WRITE)\ - _op_(BESCRR ,802 , Reserved ,FLAG_READ_WRITE)\ - _op_(BESCRRU ,803 , Reserved ,FLAG_READ_WRITE)\ - _op_(EBBHR ,804 , Reserved ,FLAG_READ_WRITE)\ - _op_(EBBRR ,805 , Reserved ,FLAG_READ_WRITE)\ - _op_(BESCR ,806 , Reserved ,FLAG_READ_WRITE)\ - _op_(LMRR ,813 , Reserved ,FLAG_READ_WRITE)\ - _op_(LMSER ,814 , Reserved ,FLAG_READ_WRITE)\ - _op_(TAR ,815 , Reserved ,FLAG_READ_WRITE)\ - _op_(ASDR ,816 , Reserved ,FLAG_READ_WRITE)\ - _op_(PSSCR_SU ,823 , Reserved ,FLAG_READ_WRITE)\ - _op_(IC ,848 , T_IC ,FLAG_READ_WRITE)\ - _op_(VTB ,849 , L_VTB ,FLAG_READ_WRITE)\ - _op_(LDBAR ,850 , L_LDBAR ,FLAG_READ_WRITE)\ - _op_(MMCRC ,851 , MMCRC ,FLAG_READ_WRITE)\ - _op_(PMSR ,853 , PMSR ,FLAG_READ_ONLY )\ - _op_(PMMAR ,854 , PMMAR ,FLAG_READ_WRITE)\ - _op_(PSSCR ,855 , V_PSSCR ,FLAG_READ_WRITE)\ - _op_(L2QOSR ,861 , L_PMMAR ,FLAG_WRITE_ONLY)\ - _op_(WORC ,863 , Reserved ,FLAG_READ_WRITE)\ - _op_(TRIG0 ,880 , Reserved ,FLAG_WRITE_ONLY)\ - _op_(TRIG1 ,881 , Reserved ,FLAG_WRITE_ONLY)\ - _op_(TRIG2 ,882 , Reserved ,FLAG_WRITE_ONLY)\ - _op_(PMCR ,884 , PMCR ,FLAG_READ_WRITE)\ - _op_(RWMR ,885 , PWMR ,FLAG_READ_WRITE)\ - _op_(WORT ,895 , Reserved ,FLAG_READ_WRITE)\ - _op_(PPR ,896 , Reserved ,FLAG_READ_WRITE)\ - _op_(PPR32 ,898 , Reserved ,FLAG_READ_WRITE)\ - _op_(TSCR ,921 , Reserved ,FLAG_READ_WRITE)\ - _op_(TTR ,922 , Reserved ,FLAG_READ_WRITE)\ - _op_(TRACE ,1006, TRACE ,FLAG_WRITE_ONLY)\ - _op_(HID ,1008, HID ,FLAG_READ_WRITE)\ - _op_(PIR ,1023, PIR ,FLAG_WRITE_ONLY) - -#define DO_SPR_MAP(in_name, in_number, in_spy_name, in_flag)\ + _op_(XER ,1 , N/A ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(DSCR_RU ,3 , N/A ,FLAG_READ_WRITE ,SPR_PER_PT ,25)\ + _op_(LR ,8 , ECP.IFU.T_LR ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(CTR ,9 , ECP.IFU.T_CTR ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(UAMR ,13 , N/A ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(DSCR ,17 , ECP.LS.LSPRQX_DSCR ,FLAG_READ_WRITE ,SPR_PER_PT ,25)\ + _op_(DSISR ,18 , ECP.LS.T_DSISR ,FLAG_READ_WRITE ,SPR_PER_PT ,32)\ + _op_(DAR ,19 , ECP.LS.T_DAR ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(DEC ,22 , EXP.EC.CC.PCC.V_DEC ,FLAG_READ_WRITE ,SPR_PER_PT ,32)\ + _op_(SDR1 ,25 , ECP.LS.V_SDR1_MASTER ,FLAG_READ_WRITE ,SPR_PER_VT ,64)\ + _op_(SRR0 ,26 , ECP.IFU.T_SRR0 ,FLAG_READ_WRITE ,SPR_PER_LPAR_VT ,64)\ + _op_(SRR1 ,27 , ECP.SD.T_SRR1 ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(CFAR ,28 , ECP.IFU.T_CFAR ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(AMR ,29 , ECP.LS.T_AMR_MASTER ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(PIDR ,48 , ECP.LS.T_PID_MASTER ,FLAG_READ_WRITE ,SPR_PER_PT ,32)\ + _op_(IAMR ,61 , ECP.LS.T_IAMR_MASTER ,FLAG_READ_WRITE ,SPR_PER_PT ,32)\ + _op_(TFHAR ,128 , ECP.IFU.T_TFHAR ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(TFIAR ,129 , ECP.IFU.T_TFIAR ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(TEXASR ,130 , ECP.SD.T_TEXASR ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(TEXASRU ,131 , ECP.SD.T_TEXASR ,FLAG_READ_WRITE ,SPR_PER_PT ,32)\ + _op_(CTRL_RU ,136 , EXP.EC.CC.PCC.COMMON.SPR_COMMON.CTRL ,FLAG_READ_ONLY ,SPR_PER_PT ,32)\ + _op_(TIDR ,144 , ECP.LS.T_TIDR ,FLAG_READ_WRITE ,SPR_SHARED ,64)\ + _op_(CTRL ,152 , EXP.EC.CC.PCC.COMMON.SPR_COMMON.CTRL ,FLAG_WRITE_ONLY ,SPR_PER_PT ,32)\ + _op_(FSCR ,153 , ECP.SD.T_FSCR ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(UAMOR ,157 , ECP.LS.T_UAMOR ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(GSR ,158 , N/A ,FLAG_READ_WRITE ,SPR_SHARE_NA ,64)\ + _op_(PSPB ,159 , ECP.PC.PMU.SPR_CORE.V_PSPB ,FLAG_READ_WRITE ,SPR_PER_PT ,32)\ + _op_(DPDES ,176 , EXP.EC.CC.PCC.COMMON.SPR_COMMON.DPDES ,FLAG_READ_WRITE ,SPR_PER_CORE ,8 )\ + _op_(DAWR0 ,180 , ECP.LS.T_DAWR_MASTER ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(RPR ,186 , ECP.IFU.RPR ,FLAG_READ_WRITE ,SPR_PER_CORE ,64)\ + _op_(CIABR ,187 , ECP.IFU.T_CIABR ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(DAWRX0 ,188 , ECP.LS.T_DAWRX_MASTER ,FLAG_READ_WRITE ,SPR_PER_PT ,32)\ + _op_(HFSCR ,190 , ECP.SD.T_HFSCR ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(VRSAVE ,256 , ECP.SD.T_VRSAVE ,FLAG_READ_WRITE ,SPR_PER_PT ,32)\ + _op_(SPRG3_RU ,259 , ECP.PC.T_SPRG3 ,FLAG_READ_ONLY ,SPR_PER_PT ,64)\ + _op_(TB ,268 , EXP.EC.CC.PCC.L_TB ,FLAG_READ_ONLY ,SPR_PER_LPAR_VT ,64)\ + _op_(TBU_RU ,269 , EXP.EC.CC.PCC.L_TBU ,FLAG_READ_ONLY ,SPR_PER_LPAR_VT ,32)\ + _op_(SPRG0 ,272 , ECP.PC.T_SPRG0 ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(SPRG1 ,273 , ECP.PC.T_SPRG1 ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(SPRG2 ,274 , ECP.PC.T_SPRG2 ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(SPRG3 ,275 , ECP.PC.T_SPRG3 ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(SPRC ,276 , EXP.EC.CC.C_MODE_SPRC ,FLAG_READ_WRITE ,SPR_PER_VT ,64)\ + _op_(SPRD ,277 , N/A ,FLAG_READ_WRITE ,SPR_SHARE_NA ,64)\ + _op_(CIR ,283 , ECP.PC.PMU.SPR_CORE.CIR ,FLAG_READ_ONLY ,SPR_SHARED ,32)\ + _op_(TBL ,284 , EXP.EC.CC.PCC.L_TBL ,FLAG_WRITE_ONLY ,SPR_PER_LPAR_VT ,32)\ + _op_(TBU ,285 , EXP.EC.CC.PCC.L_TBU ,FLAG_WRITE_ONLY ,SPR_PER_LPAR_VT ,32)\ + _op_(TBU40 ,286 , EXP.EC.CC.PCC.L_TBU40 ,FLAG_WRITE_ONLY ,SPR_PER_LPAR_VT ,64)\ + _op_(PVR ,287 , ECP.PC.PMU.SPR_CORE.PVR ,FLAG_READ_ONLY ,SPR_SHARED ,32)\ + _op_(HSPRG0 ,304 , ECP.PC.T_HSPRG0 ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(HSPRG1 ,305 , ECP.PC.T_HSPRG1 ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(HDSISR ,306 , ECP.LS.T_HDSISR ,FLAG_READ_WRITE ,SPR_PER_PT ,32)\ + _op_(HDAR ,307 , ECP.LS.T_HDAR ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(SPURR ,308 , EXP.EC.CC.PCC.V_SPURR ,FLAG_READ_WRITE ,SPR_PER_VT ,64)\ + _op_(PURR ,309 , EXP.EC.CC.PCC.V_PURR ,FLAG_READ_WRITE ,SPR_PER_VT ,64)\ + _op_(HDEC ,310 , EXP.EC.CC.PCC.L_HDEC ,FLAG_READ_WRITE ,SPR_PER_LPAR_VT ,32)\ + _op_(RMOR ,312 , N/A ,FLAG_READ_WRITE ,SPR_PER_LPAR_PT ,64)\ + _op_(HRMOR ,313 , ECP.LS.HRMOR ,FLAG_READ_WRITE ,SPR_SHARED ,64)\ + _op_(HSRR0 ,314 , ECP.IFU.T_HSRR0 ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(HSRR1 ,315 , ECP.SD.T_HSRR1 ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(TFMR ,317 , EXP.EC.CC.PCC.COMMON.TFC.T_TFMR ,FLAG_READ_WRITE ,SPR_PARTIAL_SHARED ,64)\ + _op_(LPCR ,318 , ECP.LS.T_LPCR_MASTER ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(LPIDR ,319 , ECP.LS.T_LPIDR_MASTER ,FLAG_READ_WRITE ,SPR_PER_LPAR_PT ,64)\ + _op_(HMER ,336 , EXP.EC.CC.PCC.COMMON.SPR_COMMON.V_HMER ,FLAG_READ_WRITE ,SPR_PER_VT ,64)\ + _op_(HMEER ,337 , EXP.EC.CC.PCC.COMMON.SPR_COMMON.HMEER ,FLAG_READ_WRITE ,SPR_SHARED ,64)\ + _op_(PCR ,338 , ECP.IFU.T_PCR ,FLAG_READ_WRITE ,SPR_PER_LPAR_PT ,64)\ + _op_(HEIR ,339 , ECP.SD.T_HEIR ,FLAG_READ_WRITE ,SPR_PER_PT ,32)\ + _op_(AMOR ,349 , ECP.LS.AMOR ,FLAG_READ_WRITE ,SPR_PER_LPAR_PT ,64)\ + _op_(TIR ,446 , ECP.PC.PMU.SPR_CORE.TIR ,FLAG_READ_ONLY ,SPR_PER_PT ,8 )\ + _op_(PTCR ,464 , ECP.LS.PTCR ,FLAG_READ_WRITE ,SPR_PER_CORE ,64)\ + _op_(USPRG0 ,496 , N/A ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(USPRG1 ,497 , N/A ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(UDAR ,499 , ECP.LS.T_UDAR ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(SEIDR ,504 , ECP.LS.T_SEIDR ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(URMOR ,505 , ECP.LS.URMOR ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(USRR0 ,506 , ECP.IFU.T_USRR0 ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(USRR1 ,507 , N/A ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(UEIR ,509 , N/A ,FLAG_READ_WRITE ,SPR_PER_PT ,32)\ + _op_(ACMCR ,510 , N/A ,FLAG_READ_WRITE ,SPR_PER_PT ,32)\ + _op_(SEIDBAR ,511 , ECP.LS.SEIDBAR ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(SIER_RU ,768 , ECP.PC.T_SIER ,FLAG_READ_ONLY ,SPR_PER_PT ,64)\ + _op_(MMCR2_RU ,769 , ECP.PC.T_MMCR2 ,FLAG_READ_ONLY ,SPR_PER_PT ,64)\ + _op_(MMCRA_RU ,770 , ECP.PC.T_MMCRA ,FLAG_READ_ONLY ,SPR_PER_PT ,64)\ + _op_(PMC1_RU ,771 , ECP.PC.T_PMC1 ,FLAG_READ_ONLY ,SPR_PER_PT ,32)\ + _op_(PMC2_RU ,772 , ECP.PC.T_PMC2 ,FLAG_READ_ONLY ,SPR_PER_PT ,32)\ + _op_(PMC3_RU ,773 , ECP.PC.T_PMC3 ,FLAG_READ_ONLY ,SPR_PER_PT ,32)\ + _op_(PMC4_RU ,774 , ECP.PC.T_PMC4 ,FLAG_READ_ONLY ,SPR_PER_PT ,32)\ + _op_(PMC5_RU ,775 , ECP.PC.T_PMC5 ,FLAG_READ_ONLY ,SPR_PER_PT ,32)\ + _op_(PMC6_RU ,776 , ECP.PC.T_PMC6 ,FLAG_READ_ONLY ,SPR_PER_PT ,32)\ + _op_(MMCR0_RU ,779 , ECP.PC.T_MMCR0 ,FLAG_READ_ONLY ,SPR_PER_PT ,32)\ + _op_(SIAR_RU ,780 , ECP.IFU.T_SIAR ,FLAG_READ_ONLY ,SPR_PER_PT ,64)\ + _op_(SDAR_RU ,781 , ECP.LS.T_SDAR ,FLAG_READ_ONLY ,SPR_PER_PT ,64)\ + _op_(MMCR1_RU ,782 , ECP.PC.T_MMCR1 ,FLAG_READ_ONLY ,SPR_PER_PT ,32)\ + _op_(SIER ,784 , ECP.PC.T_SIER ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(MMCR2 ,785 , ECP.PC.T_MMCR2 ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(MMCRA ,786 , ECP.PC.T_MMCRA ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(PMC1 ,787 , ECP.PC.T_PMC1 ,FLAG_READ_WRITE ,SPR_PER_PT ,32)\ + _op_(PMC2 ,788 , ECP.PC.T_PMC2 ,FLAG_READ_WRITE ,SPR_PER_PT ,32)\ + _op_(PMC3 ,789 , ECP.PC.T_PMC3 ,FLAG_READ_WRITE ,SPR_PER_PT ,32)\ + _op_(PMC4 ,790 , ECP.PC.T_PMC4 ,FLAG_READ_WRITE ,SPR_PER_PT ,32)\ + _op_(PMC5 ,791 , ECP.PC.T_PMC5 ,FLAG_READ_WRITE ,SPR_PER_PT ,32)\ + _op_(PMC6 ,792 , ECP.PC.T_PMC6 ,FLAG_READ_WRITE ,SPR_PER_PT ,32)\ + _op_(MMCR0 ,795 , ECP.PC.T_MMCR0 ,FLAG_READ_WRITE ,SPR_PER_PT ,32)\ + _op_(SIAR ,796 , ECP.IFU.T_SIAR ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(SDAR ,797 , ECP.LS.T_SDAR ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(MMCR1 ,798 , ECP.PC.T_MMCR1 ,FLAG_READ_WRITE ,SPR_PER_PT ,32)\ + _op_(IMC ,799 , N/A ,FLAG_READ_WRITE ,SPR_SHARED ,64)\ + _op_(BESCRS ,800 , ECP.SD.T_BESCR ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(BESCRSU ,801 , ECP.SD.T_BESCR ,FLAG_READ_WRITE ,SPR_PER_PT ,32)\ + _op_(BESCRR ,802 , ECP.SD.T_BESCR ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(BESCRRU ,803 , ECP.SD.T_BESCR ,FLAG_READ_WRITE ,SPR_PER_PT ,32)\ + _op_(EBBHR ,804 , ECP.IFU.T_EBBHR ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(EBBRR ,805 , ECP.IFU.T_EBBRR ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(BESCR ,806 , ECP.SD.T_BESCR ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(LMRR ,813 , ECP.LS.T_LMRR ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(LMSER ,814 , ECP.LS.T_LMSER ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(TAR ,815 , ECP.IFU.T_TAR ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(ASDR ,816 , ECP.LS.T_ASDR ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(PSSCR_SU ,823 , EXP.EC.CC.PCC.PMC.V_PSSCR ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(IC ,848 , ECP.PC.T_IC ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(VTB ,849 , EXP.EC.CC.PCC.L_VTB ,FLAG_READ_WRITE ,SPR_PER_LPAR_VT ,64)\ + _op_(LDBAR ,850 , ECP.PC.IMA.L_LDBAR ,FLAG_READ_WRITE ,SPR_PER_LPAR_VT ,64)\ + _op_(MMCRC ,851 , ECP.PC.PMU.PMUC.MMCRC ,FLAG_READ_WRITE ,SPR_SHARED ,32)\ + _op_(PMSR ,853 , EXP.EC.CC.PCC.COMMON.POW.PMSR ,FLAG_READ_ONLY ,SPR_SHARED ,32)\ + _op_(PMMAR ,854 , EXP.EC.CC.PCC.COMMON.POW.PMMAR ,FLAG_READ_WRITE ,SPR_SHARED ,64)\ + _op_(PSSCR ,855 , EXP.EC.CC.PCC.PMC.V_PSSCR ,FLAG_READ_WRITE ,SPR_PER_VT ,64)\ + _op_(L2QOSR ,861 , ECP.PC.PC_NW.L_PMMAR ,FLAG_WRITE_ONLY ,SPR_PER_CORE ,64)\ + _op_(WORC ,863 , N/A ,FLAG_READ_WRITE ,SPR_SHARED ,2 )\ + _op_(TRIG0 ,880 , N/A ,FLAG_WRITE_ONLY ,SPR_PER_PT ,64)\ + _op_(TRIG1 ,881 , N/A ,FLAG_WRITE_ONLY ,SPR_PER_PT ,64)\ + _op_(TRIG2 ,882 , N/A ,FLAG_WRITE_ONLY ,SPR_PER_PT ,64)\ + _op_(PMCR ,884 , EXP.EC.CC.PCC.COMMON.POW.PMCR ,FLAG_READ_WRITE ,SPR_PER_CORE ,64)\ + _op_(RWMR ,885 , EXP.EC.CC.PCC.TFDP.TFP.RWMR ,FLAG_READ_WRITE ,SPR_SHARED ,64)\ + _op_(WORT ,895 , ECP.IFU.T_WORT ,FLAG_READ_WRITE ,SPR_PER_PT ,18)\ + _op_(PPR ,896 , ECP.SD.T_PPR ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ + _op_(PPR32 ,898 , N/A ,FLAG_READ_WRITE ,SPR_PER_PT ,32)\ + _op_(TSCR ,921 , ECP.SD.TSCR ,FLAG_READ_WRITE ,SPR_SHARED ,32)\ + _op_(TTR ,922 , ECP.SD.TTR ,FLAG_READ_WRITE ,SPR_SHARED ,64)\ + _op_(TRACE ,1006, N/A ,FLAG_WRITE_ONLY ,SPR_SHARED ,64)\ + _op_(HID ,1008, ECP.PC.THRCTL.TCTLCOM.HID ,FLAG_READ_WRITE ,SPR_SHARED ,64)\ + _op_(PIR ,1023, ECP.PC.PMU.SPR_CORE.PIR ,FLAG_WRITE_ONLY ,SPR_PER_VT ,32)\ + _op_(NIA ,2000, N/A ,FLAG_READ_WRITE ,SPR_SHARE_NA ,64)\ + _op_(MSR ,2001, N/A ,FLAG_READ_WRITE ,SPR_SHARE_NA ,64)\ + _op_(CR ,2002, N/A ,FLAG_READ_WRITE ,SPR_SHARE_NA ,32)\ + _op_(FPSCR ,2003, N/A ,FLAG_READ_WRITE ,SPR_SHARE_NA ,64) + +#define DO_SPR_MAP(in_name, in_number, in_spy_name, in_flag, in_share_type, in_bit_length)\ SPRMapEntry entry##in_name; \ entry##in_name.number = in_number; \ entry##in_name.spy_name = #in_spy_name; \ entry##in_name.flag = in_flag; \ - spr_map[#in_name] = entry##in_name; - -//----------------------------------------------------------------------------------- -//function pointer typedef definition for HWP call support -typedef fapi2::ReturnCode (*p9_spr_name_map_FP_t) (const std::string i_name, const bool i_write, uint32_t& o_number); + entry##in_name.share_type = in_share_type; \ + entry##in_name.bit_length = in_bit_length; \ + SPR_MAP[#in_name] = entry##in_name; extern "C" { @@ -220,10 +243,9 @@ extern "C" { // Function prototype //----------------------------------------------------------------------------------- /// @brief Initial the map between SPR name and SPR number -/// @return FAPI_RC_SUCCESS if the mapping completes successfully +/// @return TRUE if the mapping completes successfully // - fapi2::ReturnCode p9_spr_name_map_init(); - + bool p9_spr_name_map_init(); //----------------------------------------------------------------------------------- /// @brief Check read-write mode for a SPR register access @@ -238,12 +260,41 @@ extern "C" { /// @param[in] i_name => SPR name /// @param[in] i_write => indicate write/read SPR /// @param[out] o_number => SPR number -/// @return FAPI_RC_SUCCESS if the mapping completes successfully +/// @return TRUE if the getting completes successfully // - fapi2::ReturnCode p9_spr_name_map(const std::string i_name, - const bool i_write, - uint32_t& o_number); + bool p9_spr_name_map(const std::string i_name, + const bool i_write, + uint32_t& o_number); + +//----------------------------------------------------------------------------------- +/// @brief Get share type of SPR +/// @param[in] i_name => SPR name +/// @param[out] o_share_type => share type +/// @return TRUE if the getting completes successfully +// + bool p9_get_share_type(const std::string i_name, + Enum_ShareType& o_share_type); + +//----------------------------------------------------------------------------------- +/// @brief Get bit length of SPR +/// @param[in] i_name => SPR name +/// @param[out] o_bit_length => bit length +/// @return TRUE if the getting completes successfully +// + bool p9_get_bit_length(const std::string i_name, + uint8_t& o_bit_length); + +//----------------------------------------------------------------------------------- +/// @brief Get SPR map entry +/// @param[in] i_name => SPR name +/// @param[out] o_spr_entry => SPR map entry +/// @return TRUE if the getting completes successfully +// + bool p9_get_spr_entry(const std::string i_name, + SPRMapEntry& o_spr_entry); + } //extern"C" #endif //_P9_SPR_NAME_MAP_H_ + diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_ram_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_ram_errors.xml index eeb58521a..2ad7d24a2 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_ram_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_ram_errors.xml @@ -31,12 +31,11 @@ - RC_P9_SPR_INVALID_RW_MODE_ACCESS_ERR + RC_P9_SPR_NAME_MAP_ACCESS_ERR - Illegal SPR read/write mode access + Illegal SPR name or read/write mode access REGNAME - RWFLAG CODE MEDIUM @@ -44,22 +43,22 @@ - RC_P9_SPR_INVALID_NAME_ACCESS_ERR + RC_P9_RAM_NOT_SETUP_ERR - Illegal SPR name access + RAM is not setup as active before doing ram or cleanup - REGNAME CODE - MEDIUM + HIGH - RC_P9_RAM_NOT_SETUP_ERR + RC_P9_RAM_THREAD_NOT_STOP_ERR - RAM is not setup as active before doing ram or cleanup + The thread to perform ramming is not stopped + THREAD CODE HIGH -- cgit v1.2.1