From 2efbed24cb84d007138a3c59916f853b9c41e39c Mon Sep 17 00:00:00 2001 From: Ben Gass Date: Thu, 2 Mar 2017 11:32:10 -0600 Subject: Set NDL IOValids based on configured NV links. Change-Id: I8dfc5410f4f4e6ec4b6fc6dc16b54b99da8f1641 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37375 Tested-by: Jenkins Server Reviewed-by: Thi N. Tran Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: DARREN J. DUFFY Reviewed-by: Joseph J. McGill Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37383 Tested-by: FSP CI Jenkins Tested-by: Jenkins OP Build CI Reviewed-by: Daniel M. Crowell --- .../p9/procedures/hwp/nest/p9_chiplet_scominit.C | 90 ++++++++++++++++++++++ .../xml/attribute_info/chip_ec_attributes.xml | 36 +++++++++ 2 files changed, 126 insertions(+) (limited to 'src') diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_chiplet_scominit.C b/src/import/chips/p9/procedures/hwp/nest/p9_chiplet_scominit.C index 55de1457f..9c3de78ad 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_chiplet_scominit.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_chiplet_scominit.C @@ -56,6 +56,7 @@ #include #include #include +#include //------------------------------------------------------------------------------ // Constant definitions @@ -78,6 +79,20 @@ const uint64_t FBC_IOO_DL_FIR_MASK = 0xFCFC3FFFFCFF000CULL; // link 0,1 internal errors are a simulation artifact in dd1 so they need to be masked const uint64_t FBC_IOO_DL_FIR_MASK_SIM_DD1 = 0xFCFC3FFFFCFF000FULL; + +static const uint8_t NV0_POS = 0x0; +static const uint8_t NV1_POS = 0x1; +static const uint8_t NV2_POS = 0x2; +static const uint8_t NV3_POS = 0x3; +static const uint8_t NV4_POS = 0x4; +static const uint8_t NV5_POS = 0x5; + +static const uint8_t PERV_OB_CPLT_CONF1_NVA_IOVALID = 0x6; +static const uint8_t PERV_OB_CPLT_CONF1_NVB_IOVALID = 0x7; +static const uint8_t PERV_OB_CPLT_CONF1_NVC_IOVALID = 0x8; + +static const uint8_t NV_OB0_MASK = 0x1; +static const uint8_t NV_OB3_MASK = 0x2; //------------------------------------------------------------------------------ // Function definitions //------------------------------------------------------------------------------ @@ -92,7 +107,11 @@ fapi2::ReturnCode p9_chiplet_scominit(const fapi2::Target> l_obus_chiplets; std::vector> l_mcs_targets; std::vector> l_capp_targets; + std::vector> l_nv_targets; + fapi2::buffer l_ob0data(0x0); + fapi2::buffer l_ob3data(0x0); uint8_t l_dd1 = 0; + uint8_t l_ndl_iovalid = 0; uint8_t l_is_simulation = 0; fapi2::ATTR_PROC_FABRIC_OPTICS_CONFIG_MODE_Type l_fbc_optics_cfg_mode = { fapi2::ENUM_ATTR_PROC_FABRIC_OPTICS_CONFIG_MODE_SMP }; @@ -100,12 +119,83 @@ fapi2::ReturnCode p9_chiplet_scominit(const fapi2::Target(); + + for (auto l_nv_target : l_nv_targets) + { + fapi2::toString(l_nv_target, l_chipletTargetStr, sizeof(l_chipletTargetStr)); + FAPI_DBG("Setting NDL IOValid for %s...", l_chipletTargetStr); + + uint8_t l_unit_pos; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_nv_target, l_unit_pos), + "Error from FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS)"); + + //Mapping from John Irish (jdirish@us.ibm.com) + //OBus Register bit NV instance NV pos + //OB0 NV0 io_valid(A) STK0.NTL0.. 0 + //OB0 NV1 io_valid(B) STK0.NTL1.. 1 + //OB0 NV2 io_valid(C) STK1.NTL0.. 2 + //OB3 NV2 io_valid(C) STK1.NTL1.. 3 + //OB3 NV1 io_valid(B) STK2.NTL0.. 4 + //OB3 NV0 io_valid(A) STK2.NTL1.. 5 + switch (l_unit_pos) + { + case NV0_POS: + l_ob0data.setBit(); + break; + + case NV1_POS: + l_ob0data.setBit(); + break; + + case NV2_POS: + l_ob0data.setBit(); + break; + + case NV3_POS: + l_ob3data.setBit(); + break; + + case NV4_POS: + l_ob3data.setBit(); + break; + + case NV5_POS: + l_ob3data.setBit(); + break; + + default: + FAPI_ASSERT(false, fapi2::P9_CHIPLET_SCOMINIT_UNSUPPORTED_NV_POS_ERR().set_TARGET(l_nv_target), + "ERROR; Unsupported NV position."); + + } + + } + + if (l_ob0data != 0) + { + FAPI_TRY(putScom(i_target, PERV_OB0_CPLT_CONF1_OR, l_ob0data)); + } + + if (l_ob3data != 0) + { + FAPI_TRY(putScom(i_target, PERV_OB3_CPLT_CONF1_OR, l_ob3data)); + } + + } + l_mcs_targets = i_target.getChildren(); for (auto l_mcs_target : l_mcs_targets) diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index e907802c1..612f2bc8e 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -48,6 +48,42 @@ + + ATTR_CHIP_EC_FEATURE_P9N_DD2_SPY_NAMES + TARGET_TYPE_PROC_CHIP + + Returns true if spy name has changed from dd1 to dd2. + Greater than or equal to 0x20 + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + GREATER_THAN_OR_EQUAL + + + + + + + ATTR_CHIP_EC_FEATURE_P9_NDL_IOVALID + TARGET_TYPE_PROC_CHIP + + Returns true if the chip has NDL IOValid bits + P9N dd2 + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + GREATER_THAN_OR_EQUAL + + + + + ATTR_CHIP_EC_FEATURE_EARLYMODE_FIX TARGET_TYPE_PROC_CHIP -- cgit v1.2.3