From 2b37fd25aed152cf46acb314a54dfdcd018abd9f Mon Sep 17 00:00:00 2001 From: Prem Shanker Jha Date: Thu, 24 May 2018 09:03:35 -0500 Subject: PM: Addressed TODOs in hcode image build HWP. Commit addresses TODOs which were found to be functional. Code has been updated for those which needed an investigation. TODOs which intend design improvement has been deferred for next release. Change-Id: I68eb6c388cc9ff6bb72b79d9de718baa2812beab RTC: 184604 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59317 Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Tested-by: Hostboot CI Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA Reviewed-by: Gregory S. Still Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59347 Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Daniel M. Crowell --- .../p9/procedures/hwp/lib/p9_hcode_image_defines.H | 17 ++++++----------- .../p9/procedures/hwp/pm/p9_hcode_image_build.C | 21 +++++++++++++-------- .../xml/error_info/p9_hcode_image_build_errors.xml | 17 +++++++++++++++-- 3 files changed, 34 insertions(+), 21 deletions(-) (limited to 'src') diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H index 3f8388a92..740187bab 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H @@ -59,7 +59,6 @@ namespace p9_hcodeImageBuild #endif //__cplusplus #endif //__ASSEMBLER__ -//FIXME to make future addition simple, need a better solution /** * @brief returns maximum quad common rings that enter HOMER. */ @@ -255,9 +254,7 @@ HCD_HDR_PAD(IMG_HDR_ALIGN_SIZE); #ifdef __ASSEMBLER__ .endm #else -//FIXME RTC 155018 -//Eventually SGPE Img header has been defined to be of size 96B. Next 36B would be for -//debug pointer.Aligning SGPE image header to 64B boundary. +//SGPE header size is 96B } __attribute__((packed, aligned(IMG_HDR_ALIGN_SIZE))) sgpeHeader_t; #endif @@ -299,9 +296,7 @@ HCD_HDR_PAD(IMG_HDR_ALIGN_SIZE); #ifdef __ASSEMBLER__ .endm #else -//FIXME RTC 155018 -//Eventually CME Img header might be of size 96B. Next 36B would be for -//debug pointer.Aligning CME image header to 64B boundary. +//CME Header size is 96B } __attribute__((packed, aligned(IMG_HDR_ALIGN_SIZE))) cmeHeader_t; #endif @@ -364,9 +359,7 @@ HCD_HDR_UINT32(g_pgpe_doptrace_length, 0 ); // Deep Opeartional #ifdef __ASSEMBLER__ .endm #else -//FIXME RTC 155018 -//Eventually PGPE Img header has been defined to be of size 96B. Next 36B would be for -//debug pointer.Aligning PGPE image header to 64B boundary. +//PGPE Header size is 128B } __attribute__((packed, aligned(IMG_HDR_ALIGN_SIZE))) PgpeHeader_t; #endif @@ -618,6 +611,7 @@ typedef struct uint8_t cmeSramRegion[CME_REGION_SIZE]; } CPMRLayout_t; + /** * @brief models image section associated with PGPE in HOMER. */ @@ -631,7 +625,8 @@ typedef struct uint8_t ppmr_reserved0[PGPE_IMAGE_RESERVE_SIZE]; uint8_t occParmBlock[sizeof(OCCPstateParmBlock)]; // PPMR + 128KB uint8_t occParmBlockReserve[OCC_PSTATE_PARAM_BLOCK_REGION_SIZE - sizeof(OCCPstateParmBlock)]; - uint8_t pstateTable[PGPE_PSTATE_OUTPUT_TABLES_REGION_SIZE]; // PPMR + 144KB + uint8_t pstateTable[sizeof(GeneratedPstateInfo)]; // PPMR + 144KB + uint8_t pstateTableReserve[PGPE_PSTATE_OUTPUT_TABLES_REGION_SIZE - sizeof(GeneratedPstateInfo)]; uint8_t ppmr_reserved1[WOF_TABLE_RESERVE]; uint8_t wofTableSize[OCC_WOF_TABLES_SIZE]; //WOF Tables located ar PPMR base + 768KB } PPMRLayout_t; diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C index 322da4a44..fb8e4b96f 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C @@ -1273,12 +1273,12 @@ void updateCpmrHeaderSR( Homerlayout_t* i_pChipHomer, uint8_t i_fusedState ) pCmeHdr->g_cme_mode_flags = SWIZZLE_4_BYTE(i_fusedState ? 1 : 0); FAPI_INF("CPMR SR"); - FAPI_INF(" Fuse Mode = 0x%08X CME Image Flag = 0x%08X", pCpmrHdr->fusedModeStatus, - SWIZZLE_4_BYTE(pCmeHdr->g_cme_mode_flags)); - FAPI_DBG(" Offset = 0x%08X, Header value 0x%08X (Real offset / 32)", + FAPI_INF("Fuse Mode : 0x%08X", pCpmrHdr->fusedModeStatus ); + FAPI_INF("CME Image Flag : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_mode_flags)); + FAPI_DBG("CME Image Offset : 0x%08X, Header value 0x%08X (Real offset / 32)", SWIZZLE_4_BYTE(pCpmrHdr->cmeImgOffset) * 32, SWIZZLE_4_BYTE(pCpmrHdr->cmeImgOffset)); - FAPI_DBG(" Size = 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeImgLength)); + FAPI_DBG("CME Image Size : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeImgLength)); FAPI_INF("<< updateCpmrHeaderSR"); } @@ -1519,8 +1519,8 @@ fapi2::ReturnCode buildCoreRestoreImage( void* const i_pImageIn, { FAPI_INF(">> buildCoreRestoreImage"); - uint32_t rcTemp = IMG_BUILD_SUCCESS; - fapi2::current_err = fapi2::FAPI2_RC_SUCCESS; + uint32_t rcTemp = IMG_BUILD_SUCCESS; + fapi2::current_err = fapi2::FAPI2_RC_SUCCESS; //Let us find XIP Header for Core Self Restore Image P9XipSection ppeSection; uint8_t* pSelfRestImg = NULL; @@ -1580,7 +1580,6 @@ fapi2::ReturnCode buildCoreRestoreImage( void* const i_pImageIn, .set_ACTUAL_SIZE( ppeSection.iv_size ), "Failed to update CPMR Header in HOMER" ); - if( i_imgType.coreSprBuild ) { //Pad undefined or runtime section with ATTN Opcode @@ -1838,7 +1837,13 @@ fapi2::ReturnCode buildPgpeImage( void* const i_pImageIn, Homerlayout_t* i_pChip i_procFuncModel.getChipLevel(), ppeSection ); - //FIXME RTC 178555 Add size check for PGPE Auxiliary Task binary. + FAPI_ASSERT( ( IMG_BUILD_SUCCESS == rcTemp ), + fapi2::P9_PGPE_AUX_TASK_BIN_SIZE_ERROR() + .set_EC_LEVEL( i_procFuncModel.getChipLevel() ) + .set_CHIP_TYPE( i_procFuncModel.getChipName() ) + .set_MAX_ALLOWED_SIZE( rcTemp ) + .set_ACTUAL_SIZE( ppeSection.iv_size ), + "Failed to copy PGPE Aux Task Binary due to bad size" ); io_ppmrHdr.g_ppmr_aux_task_offset = io_ppmrHdr.g_ppmr_hcode_offset + PGPE_IMAGE_SIZE; io_ppmrHdr.g_ppmr_aux_task_length = ppeSection.iv_size; diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_hcode_image_build_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_hcode_image_build_errors.xml index 21823b931..52f4d111a 100755 --- a/src/import/chips/p9/procedures/xml/error_info/p9_hcode_image_build_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_hcode_image_build_errors.xml @@ -5,7 +5,7 @@ - + @@ -688,5 +688,18 @@ - + + RC_P9_PGPE_AUX_TASK_BIN_SIZE_ERROR + hcode image build procedure failed to build PPMR region due to a bad + size of auxiliary task binary + EC_LEVEL + CHIP_TYPE + MAX_ALLOWED_SIZE + ACTUAL_SIZE + + CODE + HIGH + + + -- cgit v1.2.1