From 1c3233db39fad9fe7e4799f65823bf115afb872d Mon Sep 17 00:00:00 2001
From: Brian Silver <bsilver@us.ibm.com>
Date: Mon, 25 Apr 2016 09:24:34 -0500
Subject: Add 8Gb DRAM support

Change-Id: Ia2ba89169b1bdfe746bce29f5e6c32ef14b2e11c
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23720
Tested-by: Jenkins Server
Tested-by: Hostboot CI
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23722
Tested-by: FSP CI Jenkins
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
---
 .../chips/p9/procedures/hwp/memory/lib/mc/xlate.C  | 13 +++++++-----
 .../chips/p9/procedures/hwp/memory/p9_mss_scrub.C  | 24 +++++++++++++---------
 2 files changed, 22 insertions(+), 15 deletions(-)

(limited to 'src')

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C b/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C
index 6d3ed7568..69b2bd568 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C
@@ -94,8 +94,6 @@ fapi2::ReturnCode mc<TARGET_TYPE_MCS>::setup_xlate_map(const fapi2::Target<TARGE
         // Get the translation array, based on this specific DIMM's config
         dimm::kind l_dimm(d);
 
-        // TK: Get the information from the translation table for this DIMM.
-
         FAPI_DBG("address translation for DIMM %s %dR %dgbx%d in slot %d",
                  mss::c_str(d), l_dimm.iv_master_ranks, l_dimm.iv_dram_density, l_dimm.iv_dram_width, l_slot);
 
@@ -142,20 +140,26 @@ fapi2::ReturnCode mc<TARGET_TYPE_MCS>::setup_xlate_map(const fapi2::Target<TARGE
         }
 
 
-        // Tell the MC which of the row bits are valid.
+        // Tell the MC which of the row bits are valid, and map the DIMM selector
         if (l_dimm.iv_rows >= 16)
         {
             l_xlate.setBit(MCS_PORT02_MCP0XLT0_SLOT0_ROW15_VALID + l_slot_offset);
+            l_xlate.insertFromRight<MCS_PORT02_MCP0XLT0_R15_BIT_MAP, MCS_PORT02_MCP0XLT0_R15_BIT_MAP_LEN>(0b00110);
+            l_xlate.insertFromRight<MCS_PORT02_MCP0XLT0_D_BIT_MAP, MCS_PORT02_MCP0XLT0_D_BIT_MAP_LEN>(0b00101);
         }
 
         if (l_dimm.iv_rows >= 17)
         {
             l_xlate.setBit(MCS_PORT02_MCP0XLT0_SLOT0_ROW16_VALID + l_slot_offset);
+            l_xlate.insertFromRight<MCS_PORT02_MCP0XLT0_R16_BIT_MAP, MCS_PORT02_MCP0XLT0_R16_BIT_MAP_LEN>(0b00101);
+            l_xlate.insertFromRight<MCS_PORT02_MCP0XLT0_D_BIT_MAP, MCS_PORT02_MCP0XLT0_D_BIT_MAP_LEN>(0b00100);
         }
 
         if (l_dimm.iv_rows >= 18)
         {
             l_xlate.setBit(MCS_PORT02_MCP0XLT0_SLOT0_ROW17_VALID + l_slot_offset);
+            l_xlate.insertFromRight<MCS_PORT02_MCP0XLT0_R17_BIT_MAP, MCS_PORT02_MCP0XLT0_R17_BIT_MAP_LEN>(0b00100);
+            l_xlate.insertFromRight<MCS_PORT02_MCP0XLT0_D_BIT_MAP, MCS_PORT02_MCP0XLT0_D_BIT_MAP_LEN>(0b00011);
         }
 
     }
@@ -172,8 +176,7 @@ fapi2::ReturnCode mc<TARGET_TYPE_MCS>::setup_xlate_map(const fapi2::Target<TARGE
     // Master rank 0, 1 bit maps are ignored.
     // Row 16,17 bit maps are ignored.
     // Row 15 maps to Port Address bit 6
-    l_xlate.insertFromRight<MCS_PORT02_MCP0XLT0_D_BIT_MAP, MCS_PORT02_MCP0XLT0_D_BIT_MAP_LEN>(0b00101);
-    l_xlate.insertFromRight<MCS_PORT02_MCP0XLT0_R15_BIT_MAP, MCS_PORT02_MCP0XLT0_R15_BIT_MAP_LEN>(0b00110);
+
 
     // Drop down the column assignments
     l_xlate1.insertFromRight<MCS_PORT02_MCP0XLT1_COL4_BIT_MAP,
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_scrub.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_scrub.C
index 85a221a37..da0552a9b 100644
--- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_scrub.C
+++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_scrub.C
@@ -73,6 +73,9 @@ fapi2::ReturnCode p9_mss_scrub( const fapi2::Target<TARGET_TYPE_MCBIST>& i_targe
             // Setup l_start to represent this rank, and then make the end address from that.
             l_start.set_master_rank(r);
 
+            // For checking 8Gb DRAM, add row 16 to the mix - should see valid traffic in the AET
+            l_start.set_row(0b10);
+
             // l_end starts like as the max as we want to scrub the entire thing. If we're in sim,
             // we'll wratchet that back.
             l_start.get_range<mss::mcbist::address::MRANK>(l_end);
@@ -86,7 +89,8 @@ fapi2::ReturnCode p9_mss_scrub( const fapi2::Target<TARGET_TYPE_MCBIST>& i_targe
 
             // By default we're in maint address mode, not address counting mode. So we give it a start and end, and ignore
             // anything invalid - that's what maint address mode is all about
-            mss::mcbist::config_address_range(i_target, l_start, l_end, r);
+//            mss::mcbist::config_address_range(i_target, l_start, l_end, r);
+            mss::mcbist::config_address_range(i_target, l_start, l_start + 4, r);
 
             // Write
             {
@@ -116,15 +120,15 @@ fapi2::ReturnCode p9_mss_scrub( const fapi2::Target<TARGET_TYPE_MCBIST>& i_targe
             }
         }
 
-        // Write 0's
-        FAPI_TRY( mss::putScom(i_target, MCBIST_MCBFD0Q, 0) );
-        FAPI_TRY( mss::putScom(i_target, MCBIST_MCBFD1Q, 0) );
-        FAPI_TRY( mss::putScom(i_target, MCBIST_MCBFD2Q, 0) );
-        FAPI_TRY( mss::putScom(i_target, MCBIST_MCBFD3Q, 0) );
-        FAPI_TRY( mss::putScom(i_target, MCBIST_MCBFD4Q, 0) );
-        FAPI_TRY( mss::putScom(i_target, MCBIST_MCBFD5Q, 0) );
-        FAPI_TRY( mss::putScom(i_target, MCBIST_MCBFD6Q, 0) );
-        FAPI_TRY( mss::putScom(i_target, MCBIST_MCBFD7Q, 0) );
+        // Write pattern
+        FAPI_TRY( mss::putScom(i_target, MCBIST_MCBFD0Q, 0x1234567890ABCDEF) );
+        FAPI_TRY( mss::putScom(i_target, MCBIST_MCBFD1Q, 0x1234567890ABCDEF) );
+        FAPI_TRY( mss::putScom(i_target, MCBIST_MCBFD2Q, 0x1234567890ABCDEF) );
+        FAPI_TRY( mss::putScom(i_target, MCBIST_MCBFD3Q, 0x1234567890ABCDEF) );
+        FAPI_TRY( mss::putScom(i_target, MCBIST_MCBFD4Q, 0x1234567890ABCDEF) );
+        FAPI_TRY( mss::putScom(i_target, MCBIST_MCBFD5Q, 0x1234567890ABCDEF) );
+        FAPI_TRY( mss::putScom(i_target, MCBIST_MCBFD6Q, 0x1234567890ABCDEF) );
+        FAPI_TRY( mss::putScom(i_target, MCBIST_MCBFD7Q, 0x1234567890ABCDEF) );
 
         // Setup the sim polling based on a heuristic <cough>guess</cough>
         // Looks like ~250ck per address for a write/read program on the sim-dimm, and add a long number of polls
-- 
cgit v1.2.1