From 1b9910cea325b42cf0dadd071b30d648dc7092da Mon Sep 17 00:00:00 2001 From: Greg Still Date: Thu, 6 Jul 2017 13:41:16 -0500 Subject: PM: no EQ (eg no core) support - disables Pstates due to lack of #V VPD - Doesn't start Pstates in AUTO mode - Fixed in setup evid procedure related to same issue - rebased Change-Id: I6f52b5d968e3f66da8c9d33067424bebd333d587 CQ:SW390516 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43083 Tested-by: Jenkins Server Tested-by: Hostboot CI Reviewed-by: BRIAN D. VICTOR Reviewed-by: RAHUL BATRA Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43085 Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell --- .../p9/procedures/hwp/pm/p9_pm_pstate_gpe_init.C | 61 +++--- .../p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C | 34 ++-- .../procedures/hwp/pm/p9_pstate_parameter_block.C | 23 ++- .../chips/p9/procedures/hwp/pm/p9_setup_evid.C | 223 ++++++++++++--------- .../error_info/p9_pm_pstate_gpe_init_errors.xml | 2 +- 5 files changed, 198 insertions(+), 145 deletions(-) (limited to 'src') diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_pstate_gpe_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_pstate_gpe_init.C index c601f64fd..10877ae54 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_pstate_gpe_init.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_pstate_gpe_init.C @@ -70,7 +70,7 @@ fapi2::ReturnCode pstate_gpe_init( fapi2::buffer l_data64; fapi2::buffer l_occ_scratch2; fapi2::buffer l_xcr; - fapi2::buffer l_xsr; + fapi2::buffer l_xsr_iar; fapi2::buffer l_ivpr; uint32_t l_xsr_halt_condition = 0; uint32_t l_timeout_counter = TIMEOUT_COUNT; @@ -124,8 +124,16 @@ fapi2::ReturnCode pstate_gpe_init( l_pstates_mode), "Error getting ATTR_SYSTEM_PSTATES_MODE"); + fapi2::ATTR_PSTATES_ENABLED_Type l_ps_enabled; + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_PSTATES_ENABLED, + i_target, + l_ps_enabled), + "Error getting ATTR_PSTATES_ENABLED"); + + // Boot if not OFF - if (l_pstates_mode != fapi2::ENUM_ATTR_SYSTEM_PSTATES_MODE_OFF) + if (l_pstates_mode != fapi2::ENUM_ATTR_SYSTEM_PSTATES_MODE_OFF && + (l_ps_enabled == fapi2::ENUM_ATTR_PSTATES_ENABLED_TRUE) ) { // Set auto mode if needed if (l_pstates_mode == fapi2::ENUM_ATTR_SYSTEM_PSTATES_MODE_AUTO) @@ -156,30 +164,31 @@ fapi2::ReturnCode pstate_gpe_init( // Now wait for PGPE to boot FAPI_DBG(" Poll for PGPE Active for %d ms", PGPE_TIMEOUT_MS); l_occ_scratch2.flush<0>(); - l_xsr.flush<0>(); + l_xsr_iar.flush<0>(); do { FAPI_TRY(getScom(i_target, PU_OCB_OCI_OCCS2_SCOM, l_occ_scratch2)); - FAPI_TRY(getScom(i_target, PU_GPE2_GPEXIXSR_SCOM, l_xsr)); + FAPI_TRY(getScom(i_target, PU_GPE3_PPE_XIDBGPRO, l_xsr_iar)); FAPI_DBG("OCC Scratch2: 0x%016lx; XSR: 0x%016lx Timeout: %d", - l_occ_scratch2, l_xsr, l_timeout_counter); + l_occ_scratch2, l_xsr_iar, l_timeout_counter); // fapi2::delay takes ns as the arg fapi2::delay(PGPE_POLLTIME_MS * 1000 * 1000, PGPE_POLLTIME_MCYCLES * 1000 * 1000); } while((l_occ_scratch2.getBit() != 1) && - (l_xsr.getBit() != 1) && + (l_xsr_iar.getBit() != 1) && (--l_timeout_counter != 0)); // Extract the halt condition - l_xsr.extractToRight(l_xsr_halt_condition, - p9hcd::HALT_CONDITION_START, - p9hcd::HALT_CONDITION_LEN); - FAPI_DBG("halt state: XSR: 0x%016lx condition: %d", - l_xsr, l_xsr_halt_condition); + l_xsr_iar.extractToRight(l_xsr_halt_condition, + p9hcd::HALT_CONDITION_START, + p9hcd::HALT_CONDITION_LEN); + FAPI_DBG("halt state: XSR/IAR: 0x%016lx condition: %d", + l_xsr_iar, l_xsr_halt_condition); + // Check for a debug halt condition - FAPI_ASSERT(!((l_xsr.getBit() == 1) && + FAPI_ASSERT(!((l_xsr_iar.getBit() == 1) && ((l_xsr_halt_condition == p9hcd::DEBUG_HALT || l_xsr_halt_condition == p9hcd::DBCR_HALT) )), fapi2::PSTATE_GPE_INIT_DEBUG_HALT() @@ -192,7 +201,7 @@ fapi2::ReturnCode pstate_gpe_init( // When PGPE fails to boot, assert out FAPI_ASSERT((l_timeout_counter != 0 && l_occ_scratch2.getBit() == 1 && - l_xsr.getBit() != 1), + l_xsr_iar.getBit() != 1), fapi2::PSTATE_GPE_INIT_TIMEOUT() .set_CHIP(i_target), "Pstate GPE Init timeout"); @@ -207,22 +216,28 @@ fapi2::ReturnCode pstate_gpe_init( do { FAPI_TRY(getScom(i_target, PU_OCB_OCI_OCCS2_SCOM, l_occ_scratch2)); + FAPI_TRY(getScom(i_target, PU_GPE3_PPE_XIDBGPRO, l_xsr_iar)); // fapi2::delay takes ns as the arg fapi2::delay(PGPE_POLLTIME_MS * 1000 * 1000, PGPE_POLLTIME_MCYCLES * 1000 * 1000); } while((l_occ_scratch2.getBit() != 1) && - (l_xsr.getBit() != 1) && + (l_xsr_iar.getBit() != 1) && (--l_timeout_counter != 0)); - // When Pstate protocol fails to start, assert out - FAPI_ASSERT((l_timeout_counter != 0 && - l_occ_scratch2.getBit() == 1 && - l_xsr.getBit() != 1), - fapi2::PSTATE_GPE_INIT_PSTATE_AUTOSTART_TIMEOUT() - .set_CHIP(i_target), - "Pstate GPE Protocol Auto Start timeout"); - - FAPI_INF(" Pstate Auto Start Mode Complete!!!!"); + // When Pstate protocol fails to start, post a log + if (l_timeout_counter != 0 && + l_occ_scratch2.getBit() == 1 && + l_xsr_iar.getBit() != 1) + { + FAPI_INF(" Pstate Auto Start Mode Complete!!!!"); + } + else + { + FAPI_ASSERT_NOEXIT(false, + fapi2::PSTATE_GPE_INIT_PSTATE_AUTOSTART_TIMEOUT() + .set_CHIP(i_target), + "Pstate GPE Protocol Auto Start timeout"); + } } } else diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C index a3f7bf886..a4bec9442 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C @@ -139,20 +139,20 @@ fapi2::ReturnCode p9_pm_stop_gpe_init( for(auto l_core_trgt : l_functional_core_vector) { auto l_ex_trgt = l_core_trgt.getParent(); - FAPI_ASSERT(l_ex_trgt.isFunctional() == true, - fapi2::STOP_GPE_INVALID_CORE_EX_CONFIG() - .set_CORE(l_core_trgt) - .set_EX(l_ex_trgt) - .set_CHIP(i_target), - "Invalid Config - good core without functional EX"); + FAPI_ASSERT_NOEXIT(l_ex_trgt.isFunctional() == true, + fapi2::STOP_GPE_INVALID_CORE_EX_CONFIG(fapi2::FAPI2_ERRL_SEV_RECOVERED) + .set_CORE(l_core_trgt) + .set_EX(l_ex_trgt) + .set_CHIP(i_target), + "Invalid Config - good core without functional EX"); auto l_eq_trgt = l_core_trgt.getParent(); - FAPI_ASSERT(l_eq_trgt.isFunctional() == true, - fapi2::STOP_GPE_INVALID_CORE_EQ_CONFIG() - .set_CORE(l_core_trgt) - .set_EQ(l_eq_trgt) - .set_CHIP(i_target), - "Invalid Config - good core without functional EQ"); + FAPI_ASSERT_NOEXIT(l_eq_trgt.isFunctional() == true, + fapi2::STOP_GPE_INVALID_CORE_EQ_CONFIG(fapi2::FAPI2_ERRL_SEV_RECOVERED) + .set_CORE(l_core_trgt) + .set_EQ(l_eq_trgt) + .set_CHIP(i_target), + "Invalid Config - good core without functional EQ"); } // Check each functional EX has at least one functional core @@ -164,11 +164,11 @@ fapi2::ReturnCode p9_pm_stop_gpe_init( { auto l_functional_core_vector = l_ex_trgt.getChildren (fapi2::TARGET_STATE_FUNCTIONAL); - FAPI_ASSERT(l_functional_core_vector.empty() == false, - fapi2::STOP_GPE_INVALID_EX_CORE_CONFIG() - .set_EX(l_ex_trgt) - .set_CHIP(i_target), - "Invalid Config - good EX without any functional cores"); + FAPI_ASSERT_NOEXIT(l_functional_core_vector.empty() == false, + fapi2::STOP_GPE_INVALID_EX_CORE_CONFIG(fapi2::FAPI2_ERRL_SEV_RECOVERED) + .set_EX(l_ex_trgt) + .set_CHIP(i_target), + "Invalid Config - good EX without any functional cores"); } diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.C b/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.C index d766231cd..d351fce85 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.C @@ -296,13 +296,22 @@ p9_pstate_parameter_block( const fapi2::Target& i_ if (!present_chiplets) { - FAPI_ERR("**** ERROR : There are eq chiplets present"); + FAPI_IMP("**** WARNING : There are no EQ chiplets present which means there is no valid #V VPD"); + FAPI_IMP("**** WARNING : Pstates and all related functions will NOT be enabled."); + l_state.iv_pstates_enabled = false; - FAPI_ASSERT(false, - fapi2::PSTATE_PB_NO_PRESENT_CHIPLETS_ERROR() - .set_CHIP_TARGET(i_target) - .set_PRESENT_CHIPLETS(present_chiplets), - "No eq chiplets are present for a give proc target"); +// FAPI_ASSERT(false, +// fapi2::PSTATE_PB_NO_PRESENT_CHIPLETS_ERROR() +// .set_CHIP_TARGET(i_target) +// .set_PRESENT_CHIPLETS(present_chiplets), +// "No eq chiplets are present for a give proc target"); + + // Set the io_size to 0 so that memory allocation issues won't be + // detected by the caller. + + io_size = 0; + + break; } // --------------------------------------------- @@ -346,7 +355,7 @@ p9_pstate_parameter_block( const fapi2::Target& i_ fapi2::PSTATE_PB_FUNCTION_FAIL(fapi2::FAPI2_ERRL_SEV_RECOVERED) .set_CHIP_TARGET(i_target) .set_FAPI_RC(l_rc), - "Pstate Parameter Block proc_get_mvpd_iddq funciton failed"); + "Pstate Parameter Block proc_get_mvpd_iddq function failed"); fapi2::current_err = fapi2::FAPI2_RC_SUCCESS; } } diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_setup_evid.C b/src/import/chips/p9/procedures/hwp/pm/p9_setup_evid.C index fe046ef53..46dc285a9 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_setup_evid.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_setup_evid.C @@ -214,112 +214,123 @@ avsInitAttributes(const fapi2::Target& i_target, DATABLOCK_GET_ATTR(ATTR_PROC_R_DISTLOSS_VCS_UOHM, i_target, attrs->r_distloss_vcs_uohm); DATABLOCK_GET_ATTR(ATTR_PROC_VRM_VOFFSET_VCS_UV, i_target, attrs->vrm_voffset_vcs_uv); - //We only wish to compute voltage setting defaults if the action - //inputed to the HWP tells us to - if(i_action == COMPUTE_VOLTAGE_SETTINGS) + do { - // query VPD if any of the voltage attributes are zero - if (!attrs->vdd_voltage_mv || - !attrs->vcs_voltage_mv || - !attrs->vdn_voltage_mv) - { - uint8_t l_poundv_bucketId = 0; - fapi2::voltageBucketData_t l_poundv_data; - // Get #V data from MVPD for VDD/VDN and VCS voltage values - FAPI_TRY(proc_get_mvpd_data(i_target, - attr_mvpd_data, - &valid_pdv_points, - &present_chiplets, - l_poundv_bucketId, - &l_poundv_data, - &l_state )); - - // set VDD voltage to PowerSave Voltage from MVPD data (if no override) - if (attrs->vdd_voltage_mv) - { - FAPI_INF("VDD boot voltage override set."); - } - else - { - FAPI_INF("VDD boot voltage override not set, using VPD value and correcting for applicable load line setting"); - uint32_t vpd_vdd_voltage_mv = attr_mvpd_data[POWERSAVE][VPD_PV_VDD_MV]; - attrs->vdd_voltage_mv = - ( (vpd_vdd_voltage_mv * 1000) + // uV - ( ( (attr_mvpd_data[POWERSAVE][VPD_PV_IDD_100MA] / 10) * // A - (attrs->r_loadline_vdd_uohm + attrs->r_distloss_vdd_uohm)) + // uohm -> A*uohm = uV - attrs->vrm_voffset_vdd_uv )) / 1000; // mV - - FAPI_INF("VDD VPD voltage %d mV; Corrected voltage: %d mV; IDD: %d mA; LoadLine: %d uOhm; DistLoss: %d uOhm; Offst: %d uOhm", - vpd_vdd_voltage_mv, - attrs->vdd_voltage_mv, - attr_mvpd_data[POWERSAVE][VPD_PV_IDD_100MA] * 100, - attrs->r_loadline_vdd_uohm, - attrs->r_distloss_vdd_uohm, - attrs->vrm_voffset_vdd_uv); - - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_VDD_BOOT_VOLTAGE, i_target, attrs->vdd_voltage_mv), - "Error from FAPI_ATTR_SET (ATTR_VDD_BOOT_VOLTAGE)"); - } - - // set VCS voltage to UltraTurbo Voltage from MVPD data (if no override) - if (attrs->vcs_voltage_mv) - { - FAPI_INF("VCS boot voltage override set."); - } - else - { - FAPI_INF("VCS boot voltage override not set, using VPD value and correcting for applicable load line setting"); - uint32_t vpd_vcs_voltage_mv = attr_mvpd_data[POWERSAVE][VPD_PV_VCS_MV]; - attrs->vcs_voltage_mv = - ( (vpd_vcs_voltage_mv * 1000) + // uV - ( ( (attr_mvpd_data[POWERSAVE][VPD_PV_ICS_100MA] / 10) * // A - (attrs->r_loadline_vcs_uohm + attrs->r_distloss_vcs_uohm)) + // uohm -> A*uohm = uV - attrs->vrm_voffset_vcs_uv )) / 1000; // mV - - FAPI_INF("VCS VPD voltage %d mV; Corrected voltage: %d mV; IDD: %d mA; LoadLine: %d uOhm; DistLoss: %d uOhm; Offst: %d uOhm", - vpd_vcs_voltage_mv, - attrs->vcs_voltage_mv, - attr_mvpd_data[POWERSAVE][VPD_PV_ICS_100MA] * 100, - attrs->r_loadline_vcs_uohm, - attrs->r_distloss_vcs_uohm, - attrs->vrm_voffset_vcs_uv); - - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_VCS_BOOT_VOLTAGE, i_target, attrs->vcs_voltage_mv), - "Error from FAPI_ATTR_SET (ATTR_VCS_BOOT_VOLTAGE)"); - } - // set VDN voltage to PowerSave Voltage from MVPD data (if no override) - if (attrs->vdn_voltage_mv) + //We only wish to compute voltage setting defaults if the action + //inputed to the HWP tells us to + if(i_action == COMPUTE_VOLTAGE_SETTINGS) + { + // query VPD if any of the voltage attributes are zero + if (!attrs->vdd_voltage_mv || + !attrs->vcs_voltage_mv || + !attrs->vdn_voltage_mv) { - FAPI_INF("VDN boot voltage override set"); + uint8_t l_poundv_bucketId = 0; + fapi2::voltageBucketData_t l_poundv_data; + // Get #V data from MVPD for VDD/VDN and VCS voltage values + FAPI_TRY(proc_get_mvpd_data(i_target, + attr_mvpd_data, + &valid_pdv_points, + &present_chiplets, + l_poundv_bucketId, + &l_poundv_data, + &l_state )); + + if (!present_chiplets) + { + FAPI_IMP("**** WARNING : There are no EQ chiplets present which means there is no valid #V VPD"); + break; + } + + // set VDD voltage to PowerSave Voltage from MVPD data (if no override) + if (attrs->vdd_voltage_mv) + { + FAPI_INF("VDD boot voltage override set."); + } + else + { + FAPI_INF("VDD boot voltage override not set, using VPD value and correcting for applicable load line setting"); + uint32_t vpd_vdd_voltage_mv = attr_mvpd_data[POWERSAVE][VPD_PV_VDD_MV]; + attrs->vdd_voltage_mv = + ( (vpd_vdd_voltage_mv * 1000) + // uV + ( ( (attr_mvpd_data[POWERSAVE][VPD_PV_IDD_100MA] / 10) * // A + (attrs->r_loadline_vdd_uohm + attrs->r_distloss_vdd_uohm)) + // uohm -> A*uohm = uV + attrs->vrm_voffset_vdd_uv )) / 1000; // mV + + FAPI_INF("VDD VPD voltage %d mV; Corrected voltage: %d mV; IDD: %d mA; LoadLine: %d uOhm; DistLoss: %d uOhm; Offst: %d uOhm", + vpd_vdd_voltage_mv, + attrs->vdd_voltage_mv, + attr_mvpd_data[POWERSAVE][VPD_PV_IDD_100MA] * 100, + attrs->r_loadline_vdd_uohm, + attrs->r_distloss_vdd_uohm, + attrs->vrm_voffset_vdd_uv); + + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_VDD_BOOT_VOLTAGE, i_target, attrs->vdd_voltage_mv), + "Error from FAPI_ATTR_SET (ATTR_VDD_BOOT_VOLTAGE)"); + } + + // set VCS voltage to UltraTurbo Voltage from MVPD data (if no override) + if (attrs->vcs_voltage_mv) + { + FAPI_INF("VCS boot voltage override set."); + } + else + { + FAPI_INF("VCS boot voltage override not set, using VPD value and correcting for applicable load line setting"); + uint32_t vpd_vcs_voltage_mv = attr_mvpd_data[POWERSAVE][VPD_PV_VCS_MV]; + attrs->vcs_voltage_mv = + ( (vpd_vcs_voltage_mv * 1000) + // uV + ( ( (attr_mvpd_data[POWERSAVE][VPD_PV_ICS_100MA] / 10) * // A + (attrs->r_loadline_vcs_uohm + attrs->r_distloss_vcs_uohm)) + // uohm -> A*uohm = uV + attrs->vrm_voffset_vcs_uv )) / 1000; // mV + + FAPI_INF("VCS VPD voltage %d mV; Corrected voltage: %d mV; IDD: %d mA; LoadLine: %d uOhm; DistLoss: %d uOhm; Offst: %d uOhm", + vpd_vcs_voltage_mv, + attrs->vcs_voltage_mv, + attr_mvpd_data[POWERSAVE][VPD_PV_ICS_100MA] * 100, + attrs->r_loadline_vcs_uohm, + attrs->r_distloss_vcs_uohm, + attrs->vrm_voffset_vcs_uv); + + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_VCS_BOOT_VOLTAGE, i_target, attrs->vcs_voltage_mv), + "Error from FAPI_ATTR_SET (ATTR_VCS_BOOT_VOLTAGE)"); + } + + // set VDN voltage to PowerSave Voltage from MVPD data (if no override) + if (attrs->vdn_voltage_mv) + { + FAPI_INF("VDN boot voltage override set"); + } + else + { + FAPI_INF("VDN boot voltage override not set, using VPD value and correcting for applicable load line setting"); + uint32_t vpd_vdn_voltage_mv = attr_mvpd_data[POWERBUS][VPD_PV_VDN_MV]; + attrs->vdn_voltage_mv = + ( (vpd_vdn_voltage_mv * 1000) + // uV + ( ( (attr_mvpd_data[POWERBUS][VPD_PV_IDN_100MA] / 10) * // A + (attrs->r_loadline_vdn_uohm + attrs->r_distloss_vdn_uohm)) + // uohm -> A*uohm = uV + attrs->vrm_voffset_vdn_uv )) / 1000; // mV + + FAPI_INF("VDN VPD voltage %d mV; Corrected voltage: %d mV; IDN: %d mA; LoadLine: %d uOhm; DistLoss: %d uOhm; Offst: %d uOhm", + vpd_vdn_voltage_mv, + attrs->vdn_voltage_mv, + attr_mvpd_data[POWERBUS][VPD_PV_IDN_100MA] * 100, + attrs->r_loadline_vdn_uohm, + attrs->r_distloss_vdn_uohm, + attrs->vrm_voffset_vdn_uv); + + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_VDN_BOOT_VOLTAGE, i_target, attrs->vdn_voltage_mv), + "Error from FAPI_ATTR_SET (ATTR_VDN_BOOT_VOLTAGE)"); + } } else { - FAPI_INF("VDN boot voltage override not set, using VPD value and correcting for applicable load line setting"); - uint32_t vpd_vdn_voltage_mv = attr_mvpd_data[POWERBUS][VPD_PV_VDN_MV]; - attrs->vdn_voltage_mv = - ( (vpd_vdn_voltage_mv * 1000) + // uV - ( ( (attr_mvpd_data[POWERBUS][VPD_PV_IDN_100MA] / 10) * // A - (attrs->r_loadline_vdn_uohm + attrs->r_distloss_vdn_uohm)) + // uohm -> A*uohm = uV - attrs->vrm_voffset_vdn_uv )) / 1000; // mV - - FAPI_INF("VDN VPD voltage %d mV; Corrected voltage: %d mV; IDN: %d mA; LoadLine: %d uOhm; DistLoss: %d uOhm; Offst: %d uOhm", - vpd_vdn_voltage_mv, - attrs->vdn_voltage_mv, - attr_mvpd_data[POWERBUS][VPD_PV_IDN_100MA] * 100, - attrs->r_loadline_vdn_uohm, - attrs->r_distloss_vdn_uohm, - attrs->vrm_voffset_vdn_uv); - - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_VDN_BOOT_VOLTAGE, i_target, attrs->vdn_voltage_mv), - "Error from FAPI_ATTR_SET (ATTR_VDN_BOOT_VOLTAGE)"); + FAPI_INF("Using override for all boot voltages (VDD/VCS/VDN)"); } } - else - { - FAPI_INF("Using override for all boot voltages (VDD/VCS/VDN)"); - } } + while(0); // trace values to be used FAPI_INF("VDD boot voltage = %d mV (0x%x)", @@ -371,6 +382,12 @@ p9_setup_evid(const fapi2::Target& i_target, const // initialize the AVS slave on VDD bus FAPI_TRY(avsIdleFrame(i_target, attrs.vdd_bus_num, BRIDGE_NUMBER)); + if (!attrs.vdd_voltage_mv) + { + FAPI_IMP("VDD voltage value is zero,so we can't set boot voltage"); + break; + } + // Set Boot VDD Voltage FAPI_TRY(avsVoltageWrite(i_target, attrs.vdd_bus_num, @@ -400,6 +417,12 @@ p9_setup_evid(const fapi2::Target& i_target, const // VDN bus FAPI_TRY(avsIdleFrame(i_target, attrs.vdn_bus_num, BRIDGE_NUMBER)); + if (!attrs.vdn_voltage_mv) + { + FAPI_IMP("VDN voltage value is zero,so we can't set boot voltage"); + break; + } + // Set Boot VDN Voltage FAPI_TRY(avsVoltageWrite(i_target, attrs.vdn_bus_num, @@ -436,6 +459,12 @@ p9_setup_evid(const fapi2::Target& i_target, const // VCS bus FAPI_TRY(avsIdleFrame(i_target, attrs.vcs_bus_num, BRIDGE_NUMBER)); + if (!attrs.vcs_voltage_mv) + { + FAPI_IMP("VCS voltage value is zero,so we can't set boot voltage"); + break; + } + // Set Boot VCS voltage FAPI_TRY(avsVoltageWrite(i_target, attrs.vcs_bus_num, diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_pm_pstate_gpe_init_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_pm_pstate_gpe_init_errors.xml index 0e4600a43..f4a92a764 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_pm_pstate_gpe_init_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_pm_pstate_gpe_init_errors.xml @@ -39,7 +39,7 @@ RC_PSTATE_GPE_INIT_TIMEOUT - Pstate GPE init timed out while waiting for PGPE ACtive in OCC + Pstate GPE init timed out while waiting for PGPE Active in OCC SCRATCH2. -- cgit v1.2.1