From 1b5a02cab7f8c7f0de2536a46ae8c8448023e484 Mon Sep 17 00:00:00 2001 From: Dan Crowell Date: Tue, 17 Jul 2018 09:55:12 -0500 Subject: Use Cumulus DD1.3 SBE image instead of DD1.0 Adding support for Cumulus DD1.3 SBE images in the FSP PNOR Dropping support for Cumulus DD1.0 SBE image from FSP PNOR CMVC-Prereq: 1060757 CMVC-Prereq: 1063108 CMVC-Prereq: 1061378 Change-Id: Ia315c6f786ef6c522acf4e580ad435b0180513b3 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/62636 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell --- src/build/citest/etc/bbuild | 3 +- src/build/citest/etc/workarounds.postsimsetup | 9 ++++ src/build/citest/etc/workarounds.presimsetup | 5 ++ src/build/mkrules/hbfw/img/makefile | 5 +- src/build/simics/standalone.simics | 4 +- src/usr/fapi2/test/fapi2GetChipletNumTest.H | 23 ++------- .../common/xmltohb/simics_CUMULUS.system.xml | 12 +++-- .../common/xmltohb/simics_CUMULUS_CDIMM.system.xml | 58 ++++++++++++++++++++++ src/usr/vpd/makefile | 9 +--- 9 files changed, 92 insertions(+), 36 deletions(-) (limited to 'src') diff --git a/src/build/citest/etc/bbuild b/src/build/citest/etc/bbuild index 14fddbc07..5d549ca19 100644 --- a/src/build/citest/etc/bbuild +++ b/src/build/citest/etc/bbuild @@ -1,2 +1 @@ -/esw/fips920/Builds/b0710c_1827.920 - +/esw/fips930/Builds/b0731a_1832.930 diff --git a/src/build/citest/etc/workarounds.postsimsetup b/src/build/citest/etc/workarounds.postsimsetup index 82a1c72fe..8708e2b03 100755 --- a/src/build/citest/etc/workarounds.postsimsetup +++ b/src/build/citest/etc/workarounds.postsimsetup @@ -38,3 +38,12 @@ cp $BACKING_BUILD/src/simu/data/cec-chip/centaur_memory.act $sb/simu/data/cec-ch chmod 777 $sb/simu/data/cec-chip/centaur_memory.act patch -p0 $sb/simu/data/cec-chip/centaur_memory.act $PROJECT_ROOT/src/build/citest/etc/patches/centaur_memory.act.patch + +########################################################################## +echo "+++ SBE support for Cumulus DD1.3 +++" +#Pull in the code +sbex -t 1060757 +#Build sbei to create p9c_13.sbe_seeprom.hdr.bin +mkdir -p $sb/sbei/sbfw/ +cd $sb/sbei/sbfw/ +mk diff --git a/src/build/citest/etc/workarounds.presimsetup b/src/build/citest/etc/workarounds.presimsetup index a4d682dd7..08da3baed 100755 --- a/src/build/citest/etc/workarounds.presimsetup +++ b/src/build/citest/etc/workarounds.presimsetup @@ -35,12 +35,17 @@ #echo "WSALIAS DEFAULT FIPSLEVEL env/gfwb/simics-4.2.0/simics-4.2.83/fips/fld36/fi120201a700.42" >> $sb/simu/data/simicsInfo #echo "WSALIAS DEFAULT SIMICSLEVEL env/vtechb/simics-4.2.0/simics-4.2.83/bin" >> $sb/simu/data/simicsInfo +########################################################################## +echo "+++ Update standalone configs to use modern proc levels +++" +sbex -t 1063108 + echo "+++ Need to alter where we look for pnor images so they will be picked up properly" mkdir -p $sb/simu/data ############################################################################### ### NOTE - if you need to sbex a simicsInfo track it needs to be done BEFORE ### executing the code below +### NOTE - these lines are permanent to allow external PNOR testing ############################################################################### cp $bb/src/simu/data/simicsInfo $sb/simu/data/ chmod +w $sb/simu/data/simicsInfo diff --git a/src/build/mkrules/hbfw/img/makefile b/src/build/mkrules/hbfw/img/makefile index 5cf263bc2..002a46b2d 100755 --- a/src/build/mkrules/hbfw/img/makefile +++ b/src/build/mkrules/hbfw/img/makefile @@ -266,17 +266,16 @@ SBE_BUILD_SCRIPT = ${buildSbePart.pl:P} NIMBUS_SBE_IMG = p9n.SbePartition.bin CUMULUS_SBE_IMG = p9c.SbePartition.bin -P9N_EC10_BIN = ${SBEI_OBJPATH:Fp9n_10.sbe_seeprom.hdr.bin} P9N_EC20_BIN = ${SBEI_OBJPATH:Fp9n_20.sbe_seeprom.hdr.bin} P9N_EC21_BIN = ${SBEI_OBJPATH:Fp9n_21.sbe_seeprom.hdr.bin} P9N_EC22_BIN = ${SBEI_OBJPATH:Fp9n_22.sbe_seeprom.hdr.bin} -P9C_EC10_BIN = ${SBEI_OBJPATH:Fp9c_10.sbe_seeprom.hdr.bin} +P9C_EC13_BIN = ${SBEI_OBJPATH:Fp9c_13.sbe_seeprom.hdr.bin} P9C_EC11_BIN = ${SBEI_OBJPATH:Fp9c_11.sbe_seeprom.hdr.bin} P9C_EC12_BIN = ${SBEI_OBJPATH:Fp9c_12.sbe_seeprom.hdr.bin} SBE_PART_INFO = \ ${NIMBUS_SBE_IMG}:20=${P9N_EC20_BIN},21=${P9N_EC21_BIN},22=${P9N_EC22_BIN} \ - ${CUMULUS_SBE_IMG}:10=${P9C_EC10_BIN},11=${P9C_EC11_BIN},12=${P9C_EC12_BIN} + ${CUMULUS_SBE_IMG}:13=${P9C_EC13_BIN},11=${P9C_EC11_BIN},12=${P9C_EC12_BIN} __SBE_PART_BUILD/% : .SPECTARG .PMAKE diff --git a/src/build/simics/standalone.simics b/src/build/simics/standalone.simics index 92dcaacb6..76027b8b1 100755 --- a/src/build/simics/standalone.simics +++ b/src/build/simics/standalone.simics @@ -68,7 +68,7 @@ echo "Enable the SBE" # Set Boot Freq valid bit (bit 3) and valid data bit (bit 7) ($hb_masterproc).proc_chip.invoke parallel_store SCOM 0x5003F "31000000_00000000" 64 ($hb_masterproc).proc_chip.invoke parallel_store SCOM 0x5003A "00000000_00000000" 64 -# Set the Nest PLL Bucket ID to 3 in the 4th byte of Mbox Scratch Reg 4 -($hb_masterproc).proc_chip.invoke parallel_store SCOM 0x5003B "00000003_00000000" 64 +# Set the Nest PLL Bucket ID to 5 in the 4th byte of Mbox Scratch Reg 4 +($hb_masterproc).proc_chip.invoke parallel_store SCOM 0x5003B "00000005_00000000" 64 ($hb_masterproc).proc_chip.invoke parallel_store FSIMBOX 0x01 "80000000" 32 ($hb_masterproc).proc_chip.invoke parallel_store FSIMBOX 0x08 "00080000" 32 diff --git a/src/usr/fapi2/test/fapi2GetChipletNumTest.H b/src/usr/fapi2/test/fapi2GetChipletNumTest.H index ce50757d9..9c813f377 100644 --- a/src/usr/fapi2/test/fapi2GetChipletNumTest.H +++ b/src/usr/fapi2/test/fapi2GetChipletNumTest.H @@ -98,7 +98,6 @@ class Fapi2GetChipletNum : public CxxTest::TestSuite TS_FAIL("testVerifyiPhbChipletNum: Mismatch HUID %.8X - Expected: %.8X:, Found: %.8X", TARGETING::get_huid(l_Target), l_exp_chiplet_id, l_chiplet_id); - break; } } } while(0); @@ -153,7 +152,6 @@ class Fapi2GetChipletNum : public CxxTest::TestSuite TS_FAIL("testVerifyObusBrickChipletNum: Mismatch HUID %.8X - Expected: %.8X:, Found: %.8X", TARGETING::get_huid(l_Target), l_exp_chiplet_id, l_chiplet_id); - break; } } } while(0); @@ -206,7 +204,6 @@ class Fapi2GetChipletNum : public CxxTest::TestSuite TS_FAIL("testVerifyPecChipletNum: Mismatch HUID %.8X - Expected: %.8X:, Found: %.8X", TARGETING::get_huid(l_Target), l_exp_chiplet_id, l_chiplet_id); - break; } } } while(0); @@ -266,7 +263,6 @@ class Fapi2GetChipletNum : public CxxTest::TestSuite TS_FAIL("testVerifyCappChipletNum: Mismatch HUID %.8X - Expected: %.8X:, Found: %.8X", TARGETING::get_huid(l_Target), l_exp_chiplet_id, l_chiplet_id); - break; } } } while(0); @@ -326,7 +322,6 @@ class Fapi2GetChipletNum : public CxxTest::TestSuite TS_FAIL("testVerifyMcbistChipletNum: Mismatch HUID %.8X - Expected: %.8X:, Found: %.8X", TARGETING::get_huid(l_Target), l_exp_chiplet_id, l_chiplet_id); - break; } } } while(0); @@ -395,7 +390,6 @@ class Fapi2GetChipletNum : public CxxTest::TestSuite TS_FAIL("testVerifyMcsChipletNum: Mismatch HUID %.8X - Expected: %.8X:, Found: %.8X", TARGETING::get_huid(l_Target), l_exp_chiplet_id, l_chiplet_id); - break; } } } while(0); @@ -455,7 +449,6 @@ class Fapi2GetChipletNum : public CxxTest::TestSuite TS_FAIL("testVerifyMcaChipletNum: Mismatch HUID %.8X - Expected: %.8X:, Found: %.8X", TARGETING::get_huid(l_Target), l_exp_chiplet_id, l_chiplet_id); - break; } } } while(0); @@ -508,16 +501,15 @@ class Fapi2GetChipletNum : public CxxTest::TestSuite FAPI_DBG("testVerifyMcChipletNum HUID: %.8X, ChipletId: %.8X", TARGETING::get_huid(l_Target), l_chiplet_id); - // MC 0,1 maps to pervasive ids 0x07 + // MC 0,1 maps to pervasive ids 0x07,0x08 l_chip_unit = l_Target->getAttr(); - l_exp_chiplet_id = l_chip_unit / 4 + START_MC_CHIPLET_NUM; + l_exp_chiplet_id = l_chip_unit + START_MC_CHIPLET_NUM; if (l_chiplet_id != l_exp_chiplet_id) { TS_FAIL("testVerifyMcChipletNum: Mismatch HUID %.8X - Expected: %.8X:, Found: %.8X", TARGETING::get_huid(l_Target), l_exp_chiplet_id, l_chiplet_id); - break; } } @@ -572,15 +564,15 @@ class Fapi2GetChipletNum : public CxxTest::TestSuite TARGETING::get_huid(l_Target), l_chiplet_id); // MI 0,1 maps to pervasive ids 0x07 + // MI 2,3 maps to pervasive ids 0x08 l_chip_unit = l_Target->getAttr(); - l_exp_chiplet_id = l_chip_unit / 4 + START_MI_CHIPLET_NUM; + l_exp_chiplet_id = l_chip_unit / 2 + START_MI_CHIPLET_NUM; if (l_chiplet_id != l_exp_chiplet_id) { TS_FAIL("testVerifyMiChipletNum: Mismatch HUID %.8X - Expected: %.8X:, Found: %.8X", TARGETING::get_huid(l_Target), l_exp_chiplet_id, l_chiplet_id); - break; } } @@ -644,7 +636,6 @@ class Fapi2GetChipletNum : public CxxTest::TestSuite TS_INFO("testVerifyDmiChipletNum: Mismatch HUID %.8X - Expected: %.8X:, Found: %.8X", TARGETING::get_huid(l_Target), l_exp_chiplet_id, l_chiplet_id); - break; } } @@ -712,7 +703,6 @@ class Fapi2GetChipletNum : public CxxTest::TestSuite TS_FAIL("testVerifyObusChipletNum: Mismatch HUID %.8X - Expected: %.8X:, Found: %.8X", TARGETING::get_huid(l_Target), l_exp_chiplet_id, l_chiplet_id); - break; } } } while(0); @@ -761,7 +751,6 @@ class Fapi2GetChipletNum : public CxxTest::TestSuite TS_FAIL("testVerifyXbusChipletNum: Mismatch HUID %.8X - Expected: %.8X:, Found: %.8X", TARGETING::get_huid(l_Target), START_XBUS_CHIPLET_NUM, l_chiplet_id); - break; } } } while(0); @@ -812,7 +801,6 @@ class Fapi2GetChipletNum : public CxxTest::TestSuite TS_FAIL("testVerifyPervChipletNum: Mismatch HUID %.8X - Expected: %.8X:, Found: %.8X", TARGETING::get_huid(l_Target), l_chip_unit, l_chiplet_id); - break; } } } while(0); @@ -866,7 +854,6 @@ class Fapi2GetChipletNum : public CxxTest::TestSuite TS_FAIL("testVerifyEQChipletNum: Mismatch HUID %.8X - Expected: %.8X:, Found: %.8X", TARGETING::get_huid(l_Target), l_exp_chiplet_id, l_chiplet_id); - break; } } } while(0); @@ -928,7 +915,6 @@ class Fapi2GetChipletNum : public CxxTest::TestSuite TS_FAIL("testVerifyEXChipletNum: Mismatch HUID %.8X - Expected: %.8X:, Found: %.8X", TARGETING::get_huid(l_Target), l_exp_chiplet_id, l_chiplet_id); - break; } } } while(0); @@ -983,7 +969,6 @@ class Fapi2GetChipletNum : public CxxTest::TestSuite TS_FAIL("testVerifyCoreChipletNum: Mismatch HUID %.8X - Expected: %.8X:, Found: %.8X", TARGETING::get_huid(l_Target), l_exp_chiplet_id, l_chiplet_id); - break; } } } while(0); diff --git a/src/usr/targeting/common/xmltohb/simics_CUMULUS.system.xml b/src/usr/targeting/common/xmltohb/simics_CUMULUS.system.xml index cc7147c48..0bc77fb14 100644 --- a/src/usr/targeting/common/xmltohb/simics_CUMULUS.system.xml +++ b/src/usr/targeting/common/xmltohb/simics_CUMULUS.system.xml @@ -128,6 +128,12 @@ 0xFFFF + + + REQUIRED_SYNCH_MODE + 1 + + O_EREPAIR_THRESHOLD_FIELD 1 @@ -6233,7 +6239,7 @@ CHIPLET_ID - 0x07 + 0x08 CLASS @@ -6459,7 +6465,7 @@ CHIPLET_ID - 0x07 + 0x08 CLASS @@ -6531,7 +6537,7 @@ CHIPLET_ID - 0x07 + 0x08 CLASS diff --git a/src/usr/targeting/common/xmltohb/simics_CUMULUS_CDIMM.system.xml b/src/usr/targeting/common/xmltohb/simics_CUMULUS_CDIMM.system.xml index 287ab72e1..2cff7a108 100644 --- a/src/usr/targeting/common/xmltohb/simics_CUMULUS_CDIMM.system.xml +++ b/src/usr/targeting/common/xmltohb/simics_CUMULUS_CDIMM.system.xml @@ -3306,6 +3306,10 @@ CHIP_UNIT 0 + + CHIPLET_ID + 0x07 + CLASS UNIT @@ -3386,6 +3390,10 @@ CHIP_UNIT 1 + + CHIPLET_ID + 0x07 + CLASS UNIT @@ -3465,6 +3473,10 @@ CHIP_UNIT 2 + + CHIPLET_ID + 0x07 + CLASS UNIT @@ -3544,6 +3556,10 @@ CHIP_UNIT 3 + + CHIPLET_ID + 0x07 + CLASS UNIT @@ -3610,6 +3626,8 @@ DMI + + sys0node0proc0mc1mi2dmi4 unit-dmi-cumulus @@ -3623,6 +3641,10 @@ CHIP_UNIT 4 + + CHIPLET_ID + 0x08 + CLASS UNIT @@ -3702,6 +3724,10 @@ CHIP_UNIT 5 + + CHIPLET_ID + 0x08 + CLASS UNIT @@ -3781,6 +3807,10 @@ CHIP_UNIT 6 + + CHIPLET_ID + 0x08 + CLASS UNIT @@ -3860,6 +3890,10 @@ CHIP_UNIT 7 + + CHIPLET_ID + 0x08 + CLASS UNIT @@ -5351,6 +5385,10 @@ CHIP_UNIT 0 + + CHIPLET_ID + 0x07 + CLASS UNIT @@ -6193,6 +6231,10 @@ CHIP_UNIT 1 + + CHIPLET_ID + 0x08 + CLASS UNIT @@ -6271,6 +6313,10 @@ CHIP_UNIT 0 + + CHIPLET_ID + 0x07 + CLASS UNIT @@ -6339,6 +6385,10 @@ CHIP_UNIT 1 + + CHIPLET_ID + 0x07 + CLASS UNIT @@ -6407,6 +6457,10 @@ CHIP_UNIT 2 + + CHIPLET_ID + 0x08 + CLASS UNIT @@ -6475,6 +6529,10 @@ CHIP_UNIT 3 + + CHIPLET_ID + 0x08 + CLASS UNIT diff --git a/src/usr/vpd/makefile b/src/usr/vpd/makefile index 293cb3045..e74cfa2cd 100644 --- a/src/usr/vpd/makefile +++ b/src/usr/vpd/makefile @@ -47,14 +47,9 @@ BINARY_FILES += $(IMGDIR)/procmvpd_ven.dat:dd8507bec946283260f82af212ed32feaeb33 BINARY_FILES += $(IMGDIR)/vpo_sysmvpd.dat:f83bbcdd56defb5d155399774c4d721de25a8e96 BINARY_FILES += $(IMGDIR)/vpo_djvpd.dat:eb4dce98f19ebfe77243be1c56d3d0eaa1889d90 -# Nimbus Module VPD -# Copied from /afs/btv.ibm.com/u/sgrom/public/vpd_images/p9_dd10/module-p9-dd10-simics_v15_rs4v2.bin -# on 1/3/2017 -# Modified PG record to have proper XBUS data and only the first 4 cores +# P9 Module VPD BINARY_FILES += $(IMGDIR)/procmvpd_p9n.dat:a351f3cd5ba8a81a50c3e5a0dea5fea03e55769d -BINARY_FILES += $(IMGDIR)/procmvpd_p9c.dat:d9299c4027c597c31337b46ed311edc131ec93bc - -#Update to Centaur DD2.0 for CCIN 31E8 +BINARY_FILES += $(IMGDIR)/procmvpd_p9c.dat:939f91a9359b917c525dd7cd4ea80a03b1c08714 # CDIMM Format - download 4k cvpd file BINARY_FILES += $(IMGDIR)/cvpd_cdimm.dat:b12431fbc14304edd31e74405cdcb27560a8e00b -- cgit v1.2.1