From 07e1c50a631d79121228354e94e2158336c843c5 Mon Sep 17 00:00:00 2001 From: "Richard J. Knight" Date: Tue, 27 Nov 2012 06:48:35 -0600 Subject: Add proc_mpipl_ex_cleanup and proc_mpipl_chip_cleanup to hostboot This commit inclues code for RTC stories 41407 and 41408, both procedures are run in the same istep. Change-Id: If1d446061fb12a3331e090908f85fbf38f694ac2 Depends-on: I185ab08b59ca0b76bf72246de82b5b8d32b60b14 RTC:41407 RTC:41408 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2464 Tested-by: Jenkins Server Reviewed-by: Brian H. Horton Reviewed-by: A. Patrick Williams III --- src/include/usr/hwpf/istepreasoncodes.H | 1 + .../hwp/dram_initialization/dram_initialization.C | 103 +++++- .../hwp/dram_initialization/dram_initialization.H | 4 + .../host_mpipl_service/proc_mpipl_chip_cleanup.C | 165 ++++++++++ .../host_mpipl_service/proc_mpipl_chip_cleanup.H | 71 +++++ .../proc_mpipl_chip_cleanup_errors.xml | 30 ++ .../host_mpipl_service/proc_mpipl_ex_cleanup.C | 353 +++++++++++++++++++++ .../host_mpipl_service/proc_mpipl_ex_cleanup.H | 69 ++++ src/usr/hwpf/hwp/dram_initialization/makefile | 6 +- src/usr/hwpf/makefile | 3 +- 10 files changed, 797 insertions(+), 8 deletions(-) create mode 100644 src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_chip_cleanup.C create mode 100644 src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_chip_cleanup.H create mode 100644 src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_chip_cleanup_errors.xml create mode 100644 src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_ex_cleanup.C create mode 100644 src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_ex_cleanup.H (limited to 'src') diff --git a/src/include/usr/hwpf/istepreasoncodes.H b/src/include/usr/hwpf/istepreasoncodes.H index 85785bb0c..658a79a09 100644 --- a/src/include/usr/hwpf/istepreasoncodes.H +++ b/src/include/usr/hwpf/istepreasoncodes.H @@ -101,6 +101,7 @@ enum istepModuleId ISTEP_PROC_CHECK_SLAVE_SBE_SEEPROM_COMPLETE = 0x34, ISTEP_PROC_PCIE_SCOMINIT = 0x35, ISTEP_PROC_PCIE_CONFIG = 0x36, + ISTEP_HOST_MPIPL_SERVICE = 0x37, }; /** diff --git a/src/usr/hwpf/hwp/dram_initialization/dram_initialization.C b/src/usr/hwpf/hwp/dram_initialization/dram_initialization.C index 8e8579829..45170890b 100644 --- a/src/usr/hwpf/hwp/dram_initialization/dram_initialization.C +++ b/src/usr/hwpf/hwp/dram_initialization/dram_initialization.C @@ -63,6 +63,8 @@ // Uncomment these files as they become available: // #include "host_startPRD_dram/host_startPRD_dram.H" +#include "host_mpipl_service/proc_mpipl_ex_cleanup.H" +#include "host_mpipl_service/proc_mpipl_chip_cleanup.H" #include "mss_extent_setup/mss_extent_setup.H" // #include "mss_memdiag/mss_memdiag.H" // #include "mss_scrub/mss_scrub.H" @@ -391,7 +393,6 @@ void* call_proc_setup_bars( void *io_pArgs ) TARGETING::TargetHandleList l_cpuTargetList; getAllChips(l_cpuTargetList, TYPE_PROC ); - // ----------------------------------------------------------------------- // run mss_setup_bars on all CPUs. // ----------------------------------------------------------------------- @@ -777,16 +778,106 @@ void* call_proc_exit_cache_contained( void *io_pArgs ) // void* call_host_mpipl_service( void *io_pArgs ) { - errlHndl_t l_errl = NULL; - TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + IStepError l_StepError; + + errlHndl_t l_err = NULL; + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_host_mpipl_service entry" ); - TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "call_host_mpipl_service exit" ); + // call proc_mpipl_chip_cleanup.C + TARGETING::TargetHandleList l_procTargetList; + getAllChips(l_procTargetList, TYPE_PROC ); - return l_errl; + // --------------------------------------------------------------- + // run proc_mpipl_chip_cleanup.C on all proc chips + // --------------------------------------------------------------- + for (TargetHandleList::iterator l_iter = l_procTargetList.begin(); + l_iter != l_procTargetList.end(); ++l_iter) + { + // make a local copy of the target for ease of use + const TARGETING::Target* l_pProcTarget = *l_iter; + + // dump physical path to targets + EntityPath l_path; + l_path = l_pProcTarget->getAttr(); + l_path.dump(); + + // cast OUR type of target to a FAPI type of target. + const fapi::Target l_fapi_pProcTarget( + TARGET_TYPE_PROC_CHIP, + reinterpret_cast + (const_cast + (l_pProcTarget)) ); + + // call the HWP with each fapi::Target + FAPI_INVOKE_HWP(l_err, proc_mpipl_chip_cleanup, + l_fapi_pProcTarget ); + + if ( l_err ) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR : returned from proc_mpipl_chip_cleanup" ); + + // capture the target data in the elog + ERRORLOG::ErrlUserDetailsTarget(l_pProcTarget).addToLog( l_err ); + + // since we are doing an mpipl break out, the mpipl has failed + break; + } + + // --------------------------------------------------------------- + // run proc_mpipl_ex_cleanup.C on all proc chips + // --------------------------------------------------------------- + // call the HWP with each fapi::Target + FAPI_INVOKE_HWP(l_err, + proc_mpipl_ex_cleanup, + l_fapi_pProcTarget ); + + if ( l_err ) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR : returned from proc_mpipl_ex_cleanup" ); + + // capture the target data in the elog + ERRORLOG::ErrlUserDetailsTarget(l_pProcTarget).addToLog( l_err ); + + // since we are doing an mpipl break out, the mpipl has failed + break; + } + } + + if( l_err ) + { + + /*@ + * @errortype + * @reasoncode ISTEP_DRAM_INITIALIZATION_FAILED + * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE + * @moduleid TARGETING::ISTEP_HOST_MPIPL_SERVICE + * @userdata1 bytes 0-1: plid identifying first error + * bytes 2-3: reason code of first error + * @userdata2 bytes 0-1: total number of elogs + * included + * bytes 2-3: N/A + * @devdesc call to proc_mpipl_ex_cleanup or + * proc_mpipl_chip_cleanup has failed + * see error log identified by the plid + * in user data 1 + */ + l_StepError.addErrorDetails( + ISTEP_DRAM_INITIALIZATION_FAILED, + ISTEP_HOST_MPIPL_SERVICE, + l_err ); + + errlCommit( l_err, HWPF_COMP_ID ); + } + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "call_host_mpipl_service exit" ); + return l_StepError.getErrorHandle(); } }; // end namespace diff --git a/src/usr/hwpf/hwp/dram_initialization/dram_initialization.H b/src/usr/hwpf/hwp/dram_initialization/dram_initialization.H index 04f3206b8..c45a08563 100644 --- a/src/usr/hwpf/hwp/dram_initialization/dram_initialization.H +++ b/src/usr/hwpf/hwp/dram_initialization/dram_initialization.H @@ -218,6 +218,10 @@ void* call_proc_exit_cache_contained( void *io_pArgs ); * * return pointer to any errlogs * + * NOTE: this step will only run as part of an mpipl, + * the istep dispatcher will not call this step for + * the normal ipl flow + * */ void* call_host_mpipl_service( void *io_pArgs); diff --git a/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_chip_cleanup.C b/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_chip_cleanup.C new file mode 100644 index 000000000..5a2aa8935 --- /dev/null +++ b/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_chip_cleanup.C @@ -0,0 +1,165 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_chip_cleanup.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: proc_mpipl_chip_cleanup.C,v 1.3 2012/11/27 21:43:30 belldi Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_mpipl_chip_cleanup.C,v $ +//------------------------------------------------------------------------------ +// *| +// *! (C) Copyright International Business Machines Corp. 2012 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +// *| +// *! TITLE : proc_mpipl_chip_cleanup.C +// *! DESCRIPTION : To enable MCD recovery +// *! +// *! OWNER NAME : Dion Bell Email: belldi@us.ibm.com +// *! BACKUP NAME : Dion Bell Email: belldi@us.ibm.com +// *! +// *! +// *! +// *! +// *! +// *! Additional Note(s): +// *! +// *! +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include "proc_mpipl_chip_cleanup.H" + +//------------------------------------------------------------------------------ +// eCMD Includes +//------------------------------------------------------------------------------ + + +extern "C" +{ + //------------------------------------------------------------------------------ + // Function definitions + //------------------------------------------------------------------------------ + + //------------------------------------------------------------------------------ + // name: proc_mpipl_chip_cleanup + //------------------------------------------------------------------------------ + // purpose: + // To enable MCD recovery + // + // Note: PHBs are left in ETU reset state after executing proc_mpipl_nest_cleanup, which runs before this procedure. PHYP releases PHBs from ETU reset post HostBoot IPL. + // + // SCOM regs + // + // 1) MCD even recovery control register + // 0000000002013410 (SCOM) + // bit 0 (MCD_REC_EVEN_ENABLE): 0 to 1 transition needed to start, reset to 0 at end of request. + // bit 5 (MCD_REC_EVEN_REQ_PEND) + // + // + // 2) MCD odd recovery control register + // 0000000002013411 (SCOM) + // bit 0 (MCD_REC_ODD_ENABLE): 0 to 1 transition needed to start, reset to 0 at end of request. + // bit 5 (MCD_REC_ODD_REQ_PEND) + // + // parameters: + // 'i_target' is reference to chip target + // + // returns: + // FAPI_RC_SUCCESS (success, MCD recovery enabled for odd and even slices) + // + // RC_MCD_RECOVERY_NOT_DISABLED_RC (MCD recovery for even or odd slice is not disabled; therefore can't re-enable MCD recovery) + // (Note: refer to file eclipz/chips/p8/working/procedures/xml/error_info/proc_mpipl_chip_cleanup_errors.xml) + // + // getscom/putscom fapi errors + // fapi error assigned from eCMD function failure + // + //------------------------------------------------------------------------------ + fapi::ReturnCode proc_mpipl_chip_cleanup(const fapi::Target &i_target){ + const char *procedureName = "proc_mpipl_chip_cleanup"; //Name of this procedure + fapi::ReturnCode rc; //fapi return code value + uint32_t rc_ecmd = 0; //ecmd return code value + const uint32_t data_size = 64; //Size of data buffer + ecmdDataBufferBase fsi_data(data_size); + const int MAX_MCD_DIRS = 2; //Max of 2 MCD Directories (even and odd) + const uint64_t ARY_MCD_RECOVERY_CTRL_REGS_ADDRS[MAX_MCD_DIRS] = { + 0x0000000002013410, //MCD even recovery control register address + 0x0000000002013411 //MCD odd recovery control register address + }; + const uint32_t MCD_RECOVERY_CTRL_REG_BIT_POS0 = 0; //Bit 0 of MCD even and odd recovery control regs + const char *ARY_MCD_DIR_STRS[MAX_MCD_DIRS] = { + "Even", //Ptr to char string "Even" for even MCD + "Odd" //Ptr to char string "Odd" for odd MCD + }; + + //Verify MCD recovery was previously disabled for even and odd slices + //If not, this is an error condition + for (int counter = 0; counter < MAX_MCD_DIRS; counter++) { + FAPI_DBG("Verifying MCD %s Recovery is disabled\n", ARY_MCD_DIR_STRS[counter]); + + //Get data from MCD Even or Odd Recovery Ctrl reg + rc = fapiGetScom(i_target, ARY_MCD_RECOVERY_CTRL_REGS_ADDRS[counter], fsi_data); + if (rc) { + FAPI_ERR("%s: fapiGetScom error (addr: 0x%08llX)\n", procedureName, ARY_MCD_RECOVERY_CTRL_REGS_ADDRS[counter]); + return rc; + } + + //Check whether bit 0 is 0, meaning MCD recovery is disabled as expected + if( fsi_data.getBit(MCD_RECOVERY_CTRL_REG_BIT_POS0) ) { + FAPI_ERR("%s: MCD %s Recovery not disabled as expected\n", procedureName, ARY_MCD_DIR_STRS[counter]); + FAPI_SET_HWP_ERROR(rc, RC_MCD_RECOVERY_NOT_DISABLED_RC); + return rc; + } + } + + //Assert bit 0 of MCD Recovery Ctrl regs to enable MCD recovery + for (int counter = 0; counter < MAX_MCD_DIRS; counter++) { + FAPI_DBG("Enabling MCD %s Recovery\n", ARY_MCD_DIR_STRS[counter]); + + //Get data from MCD Even or Odd Recovery Control reg + rc = fapiGetScom(i_target, ARY_MCD_RECOVERY_CTRL_REGS_ADDRS[counter], fsi_data); + if (rc) { + FAPI_ERR("%s: fapiGetScom error (addr: 0x%08llX)\n", procedureName, ARY_MCD_RECOVERY_CTRL_REGS_ADDRS[counter]); + return rc; + } + + //Assert bit 0 of MCD Even or Odd Recovery Control reg to enable recovery + rc_ecmd = fsi_data.setBit(MCD_RECOVERY_CTRL_REG_BIT_POS0 ); + if(rc_ecmd) { + FAPI_ERR("%s: Error (%u) asserting bit pos %u in ecmdDataBufferBase that stores value of MCD %s Recovery Control reg (addr: 0x%08llX)\n", procedureName, rc_ecmd, MCD_RECOVERY_CTRL_REG_BIT_POS0, ARY_MCD_DIR_STRS[counter], ARY_MCD_RECOVERY_CTRL_REGS_ADDRS[counter]); + rc.setEcmdError(rc_ecmd); + return rc; + } + + //Write data to MCD Even or Odd Recovery Control reg + rc = fapiPutScom(i_target, ARY_MCD_RECOVERY_CTRL_REGS_ADDRS[counter], fsi_data); + if (rc) { + FAPI_ERR("%s: fapiPutScom error (addr: 0x%08llX)\n", procedureName, ARY_MCD_RECOVERY_CTRL_REGS_ADDRS[counter]); + return rc; + } + } + + return rc; + } + + + +} // extern "C" diff --git a/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_chip_cleanup.H b/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_chip_cleanup.H new file mode 100644 index 000000000..0784d68cc --- /dev/null +++ b/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_chip_cleanup.H @@ -0,0 +1,71 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_chip_cleanup.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: proc_mpipl_chip_cleanup.H,v 1.2 2012/11/27 21:37:11 belldi Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_mpipl_chip_cleanup.H,v $ +//------------------------------------------------------------------------------ +// *| +// *! (C) Copyright International Business Machines Corp. 2012 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +// *| +// *! TITLE : proc_mpipl_chip_cleanup.H +// *! DESCRIPTION : To enable MCD recovery +// *! +// *! OWNER NAME : Dion Bell Email: belldi@us.ibm.com +// *! BACKUP NAME : Dion Bell Email: belldi@us.ibm.com +// *! +//------------------------------------------------------------------------------ + +#ifndef _PROC_MPIPL_CHIP_CLEANUP_H_ +#define _PROC_MPIPL_CHIP_CLEANUP_H_ + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include + +//------------------------------------------------------------------------------ +// Structure Definition(s) +//------------------------------------------------------------------------------ + +// function pointer typedef definition for HWP call support +typedef fapi::ReturnCode (*proc_mpipl_chip_cleanup_FP_t) (const fapi::Target &); + +extern "C" +{ + /** + * @brief To enable MCD recovery + * + * @param[in] (1) 'i_target' Reference to chip target + * + * @return ReturnCode + * + * + */ + fapi::ReturnCode proc_mpipl_chip_cleanup(const fapi::Target & i_target); + + + +} //extern "C" + +#endif diff --git a/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_chip_cleanup_errors.xml b/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_chip_cleanup_errors.xml new file mode 100644 index 000000000..a8f1664c2 --- /dev/null +++ b/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_chip_cleanup_errors.xml @@ -0,0 +1,30 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + RC_MCD_RECOVERY_NOT_DISABLED_RC + MCD recovery is not disabled as expected + + diff --git a/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_ex_cleanup.C b/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_ex_cleanup.C new file mode 100644 index 000000000..246fafe9d --- /dev/null +++ b/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_ex_cleanup.C @@ -0,0 +1,353 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_ex_cleanup.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: proc_mpipl_ex_cleanup.C,v 1.3 2012/11/27 23:11:57 belldi Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_mpipl_ex_cleanup.C,v $ +//------------------------------------------------------------------------------ +// *| +// *! (C) Copyright International Business Machines Corp. 2012 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +// *| +// *! TITLE : proc_mpipl_ex_cleanup.C +// *! DESCRIPTION : Undo step that prepared fast-winkled cores for scanning and set up deep winkle mode +// *! +// *! OWNER NAME : Dion Bell Email: belldi@us.ibm.com +// *! BACKUP NAME : Dion Bell Email: belldi@us.ibm.com +// *! +// *! +// *! +// *! +// *! Additional Note(s): +// *! +// *! +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include "proc_mpipl_ex_cleanup.H" + +extern "C" +{ + + //------------------------------------------------------------------------------ + // name: proc_mpipl_ex_cleanup + //------------------------------------------------------------------------------ + // purpose: + // Undo step that prepared fast-winkled cores for scanning and set up deep winkle mode + // SCOM regs: + // 1) GP3 Register (NA in PERV CPLT) + // + // Murano (6 regs) + // 00000000140F0014 (PCB2) + // 00000000150F0014 (PCB2) + // 00000000160F0014 (PCB2) + // 000000001C0F0014 (PCB2) + // 000000001D0F0014 (PCB2) + // 000000001E0F0014 (PCB2) + // + // + // Venice (12 regs) + // 00000000110F0014 (PCB2) + // 00000000120F0014 (PCB2) + // 00000000130F0014 (PCB2) + // 00000000140F0014 (PCB2) + // 00000000150F0014 (PCB2) + // 00000000160F0014 (PCB2) + // 00000000190F0014 (PCB2) + // 000000001A0F0014 (PCB2) + // 000000001B0F0014 (PCB2) + // 000000001C0F0014 (PCB2) + // 000000001D0F0014 (PCB2) + // 000000001E0F0014 (PCB2) + // + // bit 27 (TP_LVLTRANS_FENCE): Electrical winkel fence. Mainly used by power management. + // + // 2) PowerManagement GP0 reg + // + // Murano (6 regs) + // 00000000140F0102(PCB2) + // 00000000150F0102(PCB2) + // 00000000160F0102(PCB2) + // 000000001C0F0102(PCB2) + // 000000001D0F0102(PCB2) + // 000000001E0F0102(PCB2) + // + // Venice (12 regs) + // 00000000110F0102(PCB2) + // 00000000120F0102(PCB2) + // 00000000130F0102(PCB2) + // 00000000140F0102(PCB2) + // 00000000150F0102(PCB2) + // 00000000160F0102(PCB2) + // 00000000190F0102(PCB2) + // 000000001A0F0102(PCB2) + // 000000001B0F0102(PCB2) + // 000000001C0F0102(PCB2) + // 000000001D0F0102(PCB2) + // 000000001E0F0102(PCB2) + // + // bit 22 (TP_TC_PERVASIVE_ECO_FENCE): Pervasive ECO fence + // + // bit 39 (PM_SLV_WINKLE_FENCE): Fence off the powered off chiplet in winkle. - Logical fence/hold for pcb_slave and pcb_slave_pm. For electrical fence see bit 23. + // + // 3) PowerManagement GP1 + // + // Murano (6 regs) + // 0x00000000140F0105 (PCB2) + // 0x00000000150F0105 (PCB2) + // 0x00000000160F0105 (PCB2) + // 0x000000001C0F0105 (PCB2) + // 0x000000001D0F0105 (PCB2) + // 0x000000001E0F0105 (PCB2) + // + // Venice (12 regs) + // 0x00000000110F0105 (PCB2) + // 0x00000000120F0105 (PCB2) + // 0x00000000130F0105 (PCB2) + // 0x00000000140F0105 (PCB2) + // 0x00000000150F0105 (PCB2) + // 0x00000000160F0105 (PCB2) + // 0x00000000190F0105 (PCB2) + // 0x000000001A0F0105 (PCB2) + // 0x000000001B0F0105 (PCB2) + // 0x000000001C0F0105 (PCB2) + // 0x000000001D0F0105 (PCB2) + // 0x000000001E0F0105 (PCB2) + // + // Bit 5: WINKLE_POWER_OFF_SEL: Winkle Power Off Select: + // Selects which voltage level to place the Core and ECO domain PFETs upon Winkle entry. 0 = Vret (Fast Winkle Mode), 1 = Voff (Deep Winkle Mode). Depending on the setting of pmicr_latency_en, this bit is controlled with a PCB-write (0) or by the PMICR in the core (1). + // + // Bit 15: PMICR_LATENCY_EN: Selects how the sleep/winkle latency (which is deep/fast) is controlled. If asserted the PMICR controls the winkle/sleep_power_off_sel in PMGP1, otherwise those bits are controlled via SCOM by OCC. + + // parameters: + // 'i_target' is chip target + // + // returns: + // FAPI_RC_SUCCESS (success, EX chiplets entered fast winkle) + // + // getscom/putscom/getattribute fapi errors + // fapi error assigned from eCMD function failure + // + //------------------------------------------------------------------------------ + fapi::ReturnCode proc_mpipl_ex_cleanup(const fapi::Target & i_target) { + const char *procedureName = "proc_mpipl_ex_cleanup"; + fapi::ReturnCode rc; //fapi return code + uint32_t rc_ecmd; //ecmd return code value + const uint32_t data_size = 64; //Size of data buffer + ecmdDataBufferBase fsi_data(data_size); //64-bit data buffer + uint8_t attr_chip_unit_pos; //EX chiplet's unit offset within chip with respect to similar EX units + const uint64_t EX_OFFSET_MULT = 0x01000000; //Multiplier used to calculate offset for respective EX chiplet + uint64_t EX_GP3_REG_0x1X0F0014; //Addr of GP3 reg PCB2 for respective EX chiplet + const uint64_t EX_GP3_REG_PCB2_ADDR = 0x00000000100F0014; //Addr of GP3 reg PCB2 (minus offset for EX chiplet) + const uint32_t EX_GP3_REG_PCB2_BIT_POS27 = 27; //Bit 27 of GP3 reg PCB2 + uint64_t EX_PMGP0_REG_0x1X0F0102; //Addr of PM GP0 reg PCB2 for respective EX chiplet + const uint64_t EX_PMGP0_REG_PCB2_ADDR = 0x00000000100F0102; //Addr of PM GP0 reg PCB2 (minus offset for EX chiplet) + const uint32_t EX_PMGP0_REG_PCB2_BIT_POS22 = 22; //Bit 22 of PM GP0 reg PCB2 + const uint32_t EX_PMGP0_REG_PCB2_BIT_POS39 = 39; //Bit 39 of PM GP0 reg PCB2 + uint64_t EX_PMGP1_REG_0x1X0F0103; //Variable address, PM GP1 reg PCB for respective EX chiplet + const uint64_t EX_PMGP1_REG_PCB_ADDR = 0x00000000100F0103; //PM GP1 reg PCB addr (minus offset for EX chiplet) + uint64_t EX_PMGP1_REG_0x1X0F0104; //Variable address, PM GP1 reg PCB1 for respective EX chiplet + const uint64_t EX_PMGP1_REG_PCB1_ADDR = 0x00000000100F0104; //PM GP1 reg PCB1 addr (minus offset for EX chiplet) + uint64_t EX_PMGP1_REG_0x1X0F0105; //Variable address, PM GP1 reg PCB2 for respective EX chiplet + const uint64_t EX_PMGP1_REG_PCB2_ADDR = 0x00000000100F0105; //PM GP1 reg PCB2 addr (minus offset for EX chiplet) + const uint32_t EX_PMGP1_REG_PCB2_BIT_POS5 = 5; //Bit 5 (WINKLE_POWER_OFF_SEL) of PM GP1 reg PCB2 + const uint32_t EX_PMGP1_REG_PCB2_BIT_POS15 = 15; //Bit 15 (PMICR_LATENCY_EN) of PM GP1 reg PCB2 + + fapi::TargetType l_chiplet_type = fapi::TARGET_TYPE_EX_CHIPLET; //Type of chiplet is EX chiplet + fapi::TargetState l_chiplet_state = fapi::TARGET_STATE_FUNCTIONAL; //State of chiplet is functional + std::vector v_ex_chiplets; //Vector of EX chiplets + std::vector::iterator entry_pos; //Position of entry + std::vector::iterator end_pos; //End of vector + + rc = fapiGetChildChiplets(i_target, l_chiplet_type, v_ex_chiplets, l_chiplet_state); //Get vector of EX chiplets + entry_pos = v_ex_chiplets.begin(); //first element of vector + end_pos = v_ex_chiplets.end(); //end of vector + + //Parse thru EX chiplets and prepare fast-winkled cores for scanning + while(entry_pos != end_pos ) { + // Get EX chiplet number + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &(*entry_pos), attr_chip_unit_pos); + if (rc) { + FAPI_ERR("%s: fapiGetAttribute error (ATTR_CHIP_UNIT_POS)\n", procedureName); + return rc; + } + FAPI_DBG("EX chiplet pos = 0x%02X\n", attr_chip_unit_pos); + + EX_GP3_REG_0x1X0F0014 = EX_GP3_REG_PCB2_ADDR + (EX_OFFSET_MULT * attr_chip_unit_pos); //Addr of GP3 reg (PCB2) for respective EX chiplet + FAPI_DBG("GP3 reg (PCB2), addr=0x%08llX\n", EX_GP3_REG_0x1X0F0014); + + EX_PMGP0_REG_0x1X0F0102 = EX_PMGP0_REG_PCB2_ADDR + (EX_OFFSET_MULT * attr_chip_unit_pos); //Addr of PM GP0 reg (PCB2) for respective EX chiplet + FAPI_DBG("PM GP0 reg (PCB2), addr=0x%08llX\n", EX_PMGP0_REG_0x1X0F0102 ); + + EX_PMGP1_REG_0x1X0F0103 = EX_PMGP1_REG_PCB_ADDR + (EX_OFFSET_MULT * attr_chip_unit_pos); //Addr of PM GP1 reg (PCB) for respective EX chiplet + FAPI_DBG("PM GP1 reg (PCB), addr=0x%08llX\n", EX_PMGP1_REG_0x1X0F0103); + + EX_PMGP1_REG_0x1X0F0104 = EX_PMGP1_REG_PCB1_ADDR + (EX_OFFSET_MULT * attr_chip_unit_pos); //Addr of PM GP1 reg (PCB1) for respective EX chiplet + FAPI_DBG("PM GP1 reg (PCB1), addr=0x%08llX\n", EX_PMGP1_REG_0x1X0F0104); + + EX_PMGP1_REG_0x1X0F0105 = EX_PMGP1_REG_PCB2_ADDR + (EX_OFFSET_MULT * attr_chip_unit_pos); //Addr of PM GP1 reg (PCB2) for respective EX chiplet + FAPI_DBG("PM GP1 reg (PCB2), addr=0x%08llX\n", EX_PMGP1_REG_0x1X0F0105); + + + //Undo step that prepared fast-winkled cores for scanning + // + //1) Drop PB Electrical Fence (EX_GP3_OR_0x100F0014(27)=1) + rc_ecmd = fsi_data.flushTo0(); + if(rc_ecmd) { + FAPI_ERR("%s: Error (%u): Could not flush ecmdDataBufferBase to 0's\n", procedureName, rc_ecmd); + rc.setEcmdError(rc_ecmd); + return rc; + } + + FAPI_DBG("Asserting bit 27 of ecmdDataBufferBase that stores value of GP3 reg (addr: 0x%08llX)\n", EX_GP3_REG_0x1X0F0014); + rc_ecmd = fsi_data.setBit(EX_GP3_REG_PCB2_BIT_POS27); + if(rc_ecmd) { + FAPI_ERR("%s: Error (%u): Could not assert bit 27 of ecmdDataBufferBase that stores value of GP3 reg (addr: 0x%08llX)\n", procedureName, rc_ecmd, EX_GP3_REG_0x1X0F0014); + rc.setEcmdError(rc_ecmd); + return rc; + } + + FAPI_DBG("ecmdDataBufferBase storing value of GP3 reg (addr: 0x%08llX), val=0x%016llX\n", EX_GP3_REG_0x1X0F0014, fsi_data.getDoubleWord((uint32_t) 0)); + rc = fapiPutScom( i_target, EX_GP3_REG_0x1X0F0014, fsi_data ); + if (rc) { + FAPI_ERR("%s: fapiPutScom error (addr: 0x%08llX)\n", procedureName, EX_GP3_REG_0x1X0F0014); + return rc; + } + + //2) Drop logical Pervasive/PCBS-PM fence (EX_PMGP0_OR_0x100F0102(39)=1) + rc_ecmd = fsi_data.flushTo0(); + if(rc_ecmd) { + FAPI_ERR("%s: Error (%u): Could not flush ecmdDataBufferBase to 0's\n", procedureName, rc_ecmd); + rc.setEcmdError(rc_ecmd); + return rc; + } + + FAPI_DBG("Asserting bit 39 of ecmdDataBufferBase that stores value of PM GP0 reg (addr: 0x%08llX)\n", EX_PMGP0_REG_0x1X0F0102 ); + rc_ecmd = fsi_data.setBit(EX_PMGP0_REG_PCB2_BIT_POS39); + if(rc_ecmd) { + FAPI_ERR("%s: Error (%u): Could not assert bit 39 of ecmdDataBufferBase that stores value of PM GP0 reg (addr: 0x%08llX)\n", procedureName, rc_ecmd, EX_PMGP0_REG_0x1X0F0102); + rc.setEcmdError(rc_ecmd); + return rc; + } + + FAPI_DBG("ecmdDataBufferBase storing value of PM GP0 reg (addr: 0x%08llX), val=0x%016llX\n", EX_PMGP0_REG_0x1X0F0102, fsi_data.getDoubleWord((uint32_t) 0)); + rc = fapiPutScom( i_target, EX_PMGP0_REG_0x1X0F0102, fsi_data ); + if (rc) { + FAPI_ERR("%s: fapiPutScom error (addr: 0x%08llX)\n", procedureName, EX_PMGP0_REG_0x1X0F0102); + return rc; + } + + //3) Drop Pervasive Extended Cache Option (ECO) fence (EX_PMGP0_OR_0x100F0102(22)=1) + rc_ecmd = fsi_data.flushTo0(); + if(rc_ecmd) { + FAPI_ERR("%s: Error (%u): Could not flush ecmdDataBufferBase to 0's\n", procedureName, rc_ecmd); + rc.setEcmdError(rc_ecmd); + return rc; + } + + FAPI_DBG("Asserting bit 22 of ecmdDataBufferBase that stores value of PM GP0 reg (addr: 0x%08llX)\n", EX_PMGP0_REG_0x1X0F0102 ); + rc_ecmd = fsi_data.setBit(EX_PMGP0_REG_PCB2_BIT_POS22); + if(rc_ecmd) { + FAPI_ERR("%s: Error (%u): Could not assert bit 22 of ecmdDataBufferBase that stores value of PM GP0 reg (addr: 0x%08llX)\n", procedureName, rc_ecmd, EX_PMGP0_REG_0x1X0F0102); + rc.setEcmdError(rc_ecmd); + return rc; + } + + FAPI_DBG("ecmdDataBufferBase storing value of PM GP0 reg (addr: 0x%08llX), val=0x%016llX\n", EX_PMGP0_REG_0x1X0F0102, fsi_data.getDoubleWord((uint32_t) 0)); + rc = fapiPutScom( i_target, EX_PMGP0_REG_0x1X0F0102, fsi_data ); + if (rc) { + FAPI_ERR("%s: fapiPutScom error (addr: 0x%08llX)\n", procedureName, EX_PMGP0_REG_0x1X0F0102); + return rc; + } + + + + // Check bit 15 (PMICR_LATENCY_EN) of PM GP1 reg is 0, so bit 5 (WINKLE_POWER_OFF_SEL) of PM GP1 reg is controlled via SCOM write + // + FAPI_DBG("Checking bit 15 (PMICR_LATENCY_EN) of PM GP1 reg (addr: 0x%08llX) is 0\n", EX_PMGP1_REG_0x1X0F0103); + rc = fapiGetScom(i_target, EX_PMGP1_REG_0x1X0F0103, fsi_data); + if (rc) { + FAPI_ERR("%s: fapiGetScom error (addr: 0x%08llX)\n", procedureName, EX_PMGP1_REG_0x1X0F0103); + return rc; + } + FAPI_DBG("PM GP1 reg (addr: 0x%08llX), val=0x%016llX\n", EX_PMGP1_REG_0x1X0F0103, fsi_data.getDoubleWord((uint32_t) 0)); + + //Check whether bit 15 (PMICR_LATENCY_EN) of PowerManagement GP1 reg is 1 + if( fsi_data.getBit(EX_PMGP1_REG_PCB2_BIT_POS15) ) { + FAPI_DBG("Bit pos %u (PMICR_LATENCY_EN) of PM GP1 reg (addr: 0x%08llX) is 1\n", EX_PMGP1_REG_PCB2_BIT_POS15, EX_PMGP1_REG_0x1X0F0103); + FAPI_DBG("Clearing bit pos %u (PMICR_LATENCY_EN) of PM GP1 reg (addr: 0x%08llX)\n", EX_PMGP1_REG_PCB2_BIT_POS15, EX_PMGP1_REG_0x1X0F0103); + + //Clear bit 15 (PMICR_LATENCY_EN) of PM GP1 reg + rc_ecmd = fsi_data.flushTo1(); + if(rc_ecmd) { + FAPI_ERR("%s: Error (%u): Could not flush ecmdDataBufferBase to 1's\n", procedureName, rc_ecmd); + rc.setEcmdError(rc_ecmd); + return rc; + } + rc_ecmd = fsi_data.clearBit(EX_PMGP1_REG_PCB2_BIT_POS15); + if(rc_ecmd) { + FAPI_ERR("%s: Could not clear bit pos %u of PM GP1 reg (addr: 0x%08llX)\n", procedureName, EX_PMGP1_REG_PCB2_BIT_POS15, EX_PMGP1_REG_0x1X0F0104); + rc.setEcmdError(rc_ecmd); + return rc; + } + + //Write data to PM GP1 reg + rc = fapiPutScom(i_target, EX_PMGP1_REG_0x1X0F0104, fsi_data); + if (rc) { + FAPI_ERR("%s: fapiPutScom error (addr: 0x%08llX)\n", procedureName, EX_PMGP1_REG_0x1X0F0104); + return rc; + } + } + + // Assert bit 5 (WINKLE_POWER_OFF_SEL) of PM GP1 reg + rc_ecmd = fsi_data.flushTo0(); + if(rc_ecmd) { + FAPI_ERR("%s: Error (%u): Could not flush ecmdDataBufferBase to 0's\n", procedureName, rc_ecmd); + rc.setEcmdError(rc_ecmd); + return rc; + } + rc_ecmd = fsi_data.setBit(EX_PMGP1_REG_PCB2_BIT_POS5); + if(rc_ecmd) { + FAPI_ERR("%s: Could not assert bit pos %u of PM GP1 reg (addr: 0x%08llX)\n", procedureName, EX_PMGP1_REG_PCB2_BIT_POS5, EX_PMGP1_REG_0x1X0F0105); + rc.setEcmdError(rc_ecmd); + return rc; + } + rc = fapiPutScom(i_target, EX_PMGP1_REG_0x1X0F0105, fsi_data); + if (rc) { + FAPI_ERR("%s: fapiPutScom error (addr: 0x%08llX)\n", procedureName, EX_PMGP1_REG_0x1X0F0105); + return rc; + } + + entry_pos++; //Point to next EX chiplet + } + + //Exiting fapi function + FAPI_DBG("Exiting fapi function: %s\n", procedureName); + + return rc; + } + + + +} // extern "C" diff --git a/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_ex_cleanup.H b/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_ex_cleanup.H new file mode 100644 index 000000000..df8b03177 --- /dev/null +++ b/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_ex_cleanup.H @@ -0,0 +1,69 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_ex_cleanup.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: proc_mpipl_ex_cleanup.H,v 1.3 2012/11/27 23:11:35 belldi Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_mpipl_ex_cleanup.H,v $ +//------------------------------------------------------------------------------ +// *| +// *! (C) Copyright International Business Machines Corp. 2012 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +// *| +// *! TITLE : proc_mpipl_ex_cleanup.H +// *! DESCRIPTION : Undo step that prepared fast-winkled cores for scanning and set up deep winkle mode +// *! +// *! OWNER NAME : Dion Bell Email: belldi@us.ibm.com +// *! BACKUP NAME : Dion Bell Email: belldi@us.ibm.com +// *! +//------------------------------------------------------------------------------ + +#ifndef _PROC_MPIPL_EX_CLEANUP_H_ +#define _PROC_MPIPL_EX_CLEANUP_H_ + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include +#include + +//------------------------------------------------------------------------------ +// Structure Definition(s) +//------------------------------------------------------------------------------ + +// function pointer typedef definition for HWP call support +typedef fapi::ReturnCode (*proc_mpipl_ex_cleanup_FP_t) (const fapi::Target &); + +extern "C" +{ + /** + * @brief Undo step that prepared fast-winkled cores for scanning and set up deep winkle mode + * + * @param[in] (1) 'i_target' Reference to chip target + * + * @return ReturnCode + * + * + */ + fapi::ReturnCode proc_mpipl_ex_cleanup(const fapi::Target &i_target); +} + +#endif diff --git a/src/usr/hwpf/hwp/dram_initialization/makefile b/src/usr/hwpf/hwp/dram_initialization/makefile index 38a9cd1b5..a1868d032 100644 --- a/src/usr/hwpf/hwp/dram_initialization/makefile +++ b/src/usr/hwpf/hwp/dram_initialization/makefile @@ -46,6 +46,7 @@ EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/mss_memdiag EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config +EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service ## NOTE: add new object files when you add a new HWP @@ -56,7 +57,9 @@ OBJS = dram_initialization.o \ proc_fab_smp.o \ proc_setup_bars.o \ mss_maint_cmds.o \ - proc_pcie_config.o + proc_pcie_config.o \ + proc_mpipl_ex_cleanup.o \ + proc_mpipl_chip_cleanup.o ## NOTE: add a new directory onto the vpaths when you add a new HWP @@ -67,6 +70,7 @@ VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/mss_memdiag VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config +VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service include ${ROOTPATH}/config.mk diff --git a/src/usr/hwpf/makefile b/src/usr/hwpf/makefile index 5d5311d8a..dd47f32cb 100644 --- a/src/usr/hwpf/makefile +++ b/src/usr/hwpf/makefile @@ -71,7 +71,8 @@ HWP_ERROR_XML_FILES = hwp/fapiHwpErrorInfo.xml \ hwp/runtime_errors/proc_pss_errors.xml \ hwp/runtime_errors/proc_cpu_special_wakeup_errors.xml \ hwp/runtime_errors/p8_poregpe_errors.xml \ - hwp/runtime_errors/p8_pba_init_errors.xml + hwp/runtime_errors/p8_pba_init_errors.xml \ + hwp/dram_initialization/host_mpipl_service/proc_mpipl_chip_cleanup_errors.xml ## these get generated into obj/genfiles/AttributeIds.H -- cgit v1.2.1